llvm.org GIT mirror llvm / 6849f10
ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199212 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
2 changed file(s) with 28 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
37133713 let Inst{3-0} = Rn;
37143714 }
37153715
3716 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3716 let Constraints =
3717 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
37173718 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
37183719 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
37193720 4, IIC_iMAC64, [],
0 ; RUN: llc < %s -march=arm | FileCheck %s
1 ; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=CHECK-V7
12 ; Check generated signed and unsigned multiply accumulate long.
23
34 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
4142 %add = add nsw i64 %mul, %conv2
4243 ret i64 %add
4344 }
45
46 ; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.
47 ; + Without @earlyclobber the v7 code is natural. With it, the first two
48 ; registers must be distinct from the third.
49 ; + Without "$Rd = $R", this can be satisfied without a mov before the umlal
50 ; by trying to use 6 different registers in the MachineInstr. The natural
51 ; evolution of this attempt currently leaves only two movs in the final
52 ; function, both after the umlal. With it, *some* move has to happen
53 ; before the umlal.
54 define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) {
55 ; CHECK-V7-LABEL: MACLongTest5:
56 ; CHECK-V7-LABEL: umlal r0, r1, r0, r0
57
58 ; CHECK-LABEL: MACLongTest5:
59 ; CHECK: mov [[RDLO:r[0-9]+]], r0
60 ; CHECK: umlal [[RDLO]], r1, r0, r0
61 ; CHECK: mov r0, [[RDLO]]
62
63 %conv.trunc = trunc i64 %c to i32
64 %conv = zext i32 %conv.trunc to i64
65 %conv1 = zext i32 %b to i64
66 %mul = mul i64 %conv, %conv
67 %add = add i64 %mul, %c
68 ret i64 %add
69 }