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[ARM] GlobalISel: Legalize s64 G_FCMP Same as the s32 version, for both hard and soft float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307633 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
3 changed file(s) with 942 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
106106
107107 setAction({G_FCMP, s1}, Legal);
108108 setAction({G_FCMP, 1, s32}, Legal);
109 setAction({G_FCMP, 1, s64}, Legal);
109110 } else {
110111 for (auto Ty : {s32, s64})
111112 setAction({G_FADD, Ty}, Libcall);
112113
113114 setAction({G_FCMP, s1}, Legal);
114115 setAction({G_FCMP, 1, s32}, Custom);
116 setAction({G_FCMP, 1, s64}, Custom);
115117
116118 if (AEABI(ST))
117119 setFCmpLibcallsAEABI();
154156 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
155157 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
156158 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
159
160 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
161 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
162 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
163 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
164 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
165 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
166 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
167 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
168 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
169 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
170 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
171 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
172 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
173 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
174 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
175 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
176 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
177 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
178 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
179 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
180 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
181 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
182 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
183 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
184 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
157185 }
158186
159187 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
176204 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
177205 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
178206 {RTLIB::UO_F32, CmpInst::ICMP_NE}};
207
208 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
209 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
210 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
211 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
212 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
213 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
214 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
215 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
216 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
217 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
218 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
219 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
220 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
221 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
222 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
223 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
224 {RTLIB::UO_F64, CmpInst::ICMP_NE}};
179225 }
180226
181227 ARMLegalizerInfo::FCmpLibcallsList
182 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate) const {
228 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
229 unsigned Size) const {
183230 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
184 return FCmp32Libcalls[Predicate];
231 if (Size == 32)
232 return FCmp32Libcalls[Predicate];
233 if (Size == 64)
234 return FCmp64Libcalls[Predicate];
235 llvm_unreachable("Unsupported size for FCmp predicate");
185236 }
186237
187238 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
227278 break;
228279 }
229280 case G_FCMP: {
230 assert(MRI.getType(MI.getOperand(2).getReg()).getSizeInBits() == 32 &&
231 "Unsupported size for FCMP");
232 assert(MRI.getType(MI.getOperand(3).getReg()).getSizeInBits() == 32 &&
233 "Unsupported size for FCMP");
281 assert(MRI.getType(MI.getOperand(2).getReg()) ==
282 MRI.getType(MI.getOperand(3).getReg()) &&
283 "Mismatched operands for G_FCMP");
284 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
234285
235286 auto OriginalResult = MI.getOperand(0).getReg();
236287 auto Predicate =
237288 static_cast(MI.getOperand(1).getPredicate());
238 auto Libcalls = getFCmpLibcalls(Predicate);
289 auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
239290
240291 if (Libcalls.empty()) {
241292 assert((Predicate == CmpInst::FCMP_TRUE ||
247298 }
248299
249300 auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
250 auto *ArgTy = Type::getFloatTy(Ctx);
301 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
302 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
251303 auto *RetTy = Type::getInt32Ty(Ctx);
252304
253305 SmallVector Results;
5454 using FCmpLibcallsMapTy = IndexedMap;
5555
5656 FCmpLibcallsMapTy FCmp32Libcalls;
57 FCmpLibcallsMapTy FCmp64Libcalls;
5758
58 FCmpLibcallsList getFCmpLibcalls(CmpInst::Predicate) const;
59 // Get the libcall(s) corresponding to \p Predicate for operands of \p Size
60 // bits.
61 FCmpLibcallsList getFCmpLibcalls(CmpInst::Predicate, unsigned Size) const;
5962 };
6063 } // End llvm namespace.
6164 #endif
2828
2929 define void @test_fcmp_one_s32() { ret void }
3030 define void @test_fcmp_ueq_s32() { ret void }
31
32 define void @test_fcmp_true_s64() { ret void }
33 define void @test_fcmp_false_s64() { ret void }
34
35 define void @test_fcmp_oeq_s64() { ret void }
36 define void @test_fcmp_ogt_s64() { ret void }
37 define void @test_fcmp_oge_s64() { ret void }
38 define void @test_fcmp_olt_s64() { ret void }
39 define void @test_fcmp_ole_s64() { ret void }
40 define void @test_fcmp_ord_s64() { ret void }
41 define void @test_fcmp_ugt_s64() { ret void }
42 define void @test_fcmp_uge_s64() { ret void }
43 define void @test_fcmp_ult_s64() { ret void }
44 define void @test_fcmp_ule_s64() { ret void }
45 define void @test_fcmp_une_s64() { ret void }
46 define void @test_fcmp_uno_s64() { ret void }
47
48 define void @test_fcmp_one_s64() { ret void }
49 define void @test_fcmp_ueq_s64() { ret void }
3150 ...
3251 ---
3352 name: test_frem_float
929948 ; CHECK: %r0 = COPY [[REXT]]
930949 BX_RET 14, _, implicit %r0
931950 ...
951 ---
952 name: test_fcmp_true_s64
953 # CHECK-LABEL: name: test_fcmp_true_s64
954 legalized: false
955 # CHECK: legalized: true
956 regBankSelected: false
957 selected: false
958 tracksRegLiveness: true
959 registers:
960 - { id: 0, class: _ }
961 - { id: 1, class: _ }
962 - { id: 2, class: _ }
963 - { id: 3, class: _ }
964 - { id: 4, class: _ }
965 - { id: 5, class: _ }
966 - { id: 6, class: _ }
967 - { id: 7, class: _ }
968 body: |
969 bb.0:
970 liveins: %r0, %r1, %r2, %r3
971
972 %0(s32) = COPY %r0
973 %1(s32) = COPY %r1
974 %2(s32) = COPY %r2
975 %3(s32) = COPY %r3
976 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
977 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
978 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
979 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
980 %4(s64) = G_MERGE_VALUES %0(s32), %1
981 %5(s64) = G_MERGE_VALUES %2(s32), %3
982 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
983 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
984 %6(s1) = G_FCMP floatpred(true), %4(s64), %5
985 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
986 ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
987 ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
988 %7(s32) = G_ZEXT %6(s1)
989 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
990 %r0 = COPY %7(s32)
991 ; CHECK: %r0 = COPY [[REXT]]
992 BX_RET 14, _, implicit %r0
993 ...
994 ---
995 name: test_fcmp_false_s64
996 # CHECK-LABEL: name: test_fcmp_false_s64
997 legalized: false
998 # CHECK: legalized: true
999 regBankSelected: false
1000 selected: false
1001 tracksRegLiveness: true
1002 registers:
1003 - { id: 0, class: _ }
1004 - { id: 1, class: _ }
1005 - { id: 2, class: _ }
1006 - { id: 3, class: _ }
1007 - { id: 4, class: _ }
1008 - { id: 5, class: _ }
1009 - { id: 6, class: _ }
1010 - { id: 7, class: _ }
1011 body: |
1012 bb.0:
1013 liveins: %r0, %r1, %r2, %r3
1014
1015 %0(s32) = COPY %r0
1016 %1(s32) = COPY %r1
1017 %2(s32) = COPY %r2
1018 %3(s32) = COPY %r3
1019 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1020 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1021 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1022 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1023 %4(s64) = G_MERGE_VALUES %0(s32), %1
1024 %5(s64) = G_MERGE_VALUES %2(s32), %3
1025 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1026 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1027 %6(s1) = G_FCMP floatpred(false), %4(s64), %5
1028 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
1029 ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0
1030 ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
1031 %7(s32) = G_ZEXT %6(s1)
1032 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1033 %r0 = COPY %7(s32)
1034 ; CHECK: %r0 = COPY [[REXT]]
1035 BX_RET 14, _, implicit %r0
1036 ...
1037 ---
1038 name: test_fcmp_oeq_s64
1039 # CHECK-LABEL: name: test_fcmp_oeq_s64
1040 legalized: false
1041 # CHECK: legalized: true
1042 regBankSelected: false
1043 selected: false
1044 tracksRegLiveness: true
1045 registers:
1046 - { id: 0, class: _ }
1047 - { id: 1, class: _ }
1048 - { id: 2, class: _ }
1049 - { id: 3, class: _ }
1050 - { id: 4, class: _ }
1051 - { id: 5, class: _ }
1052 - { id: 6, class: _ }
1053 - { id: 7, class: _ }
1054 body: |
1055 bb.0:
1056 liveins: %r0, %r1, %r2, %r3
1057
1058 %0(s32) = COPY %r0
1059 %1(s32) = COPY %r1
1060 %2(s32) = COPY %r2
1061 %3(s32) = COPY %r3
1062 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1063 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1064 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1065 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1066 %4(s64) = G_MERGE_VALUES %0(s32), %1
1067 %5(s64) = G_MERGE_VALUES %2(s32), %3
1068 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1069 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1070 %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
1071 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
1072 ; SOFT: ADJCALLSTACKDOWN
1073 ; SOFT-DAG: %r0 = COPY [[X0]]
1074 ; SOFT-DAG: %r1 = COPY [[X1]]
1075 ; SOFT-DAG: %r2 = COPY [[Y0]]
1076 ; SOFT-DAG: %r3 = COPY [[Y1]]
1077 ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1078 ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1079 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1080 ; SOFT: ADJCALLSTACKUP
1081 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1082 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1083 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1084 %7(s32) = G_ZEXT %6(s1)
1085 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1086 %r0 = COPY %7(s32)
1087 ; CHECK: %r0 = COPY [[REXT]]
1088 BX_RET 14, _, implicit %r0
1089 ...
1090 ---
1091 name: test_fcmp_ogt_s64
1092 # CHECK-LABEL: name: test_fcmp_ogt_s64
1093 legalized: false
1094 # CHECK: legalized: true
1095 regBankSelected: false
1096 selected: false
1097 tracksRegLiveness: true
1098 registers:
1099 - { id: 0, class: _ }
1100 - { id: 1, class: _ }
1101 - { id: 2, class: _ }
1102 - { id: 3, class: _ }
1103 - { id: 4, class: _ }
1104 - { id: 5, class: _ }
1105 - { id: 6, class: _ }
1106 - { id: 7, class: _ }
1107 body: |
1108 bb.0:
1109 liveins: %r0, %r1, %r2, %r3
1110
1111 %0(s32) = COPY %r0
1112 %1(s32) = COPY %r1
1113 %2(s32) = COPY %r2
1114 %3(s32) = COPY %r3
1115 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1116 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1117 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1118 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1119 %4(s64) = G_MERGE_VALUES %0(s32), %1
1120 %5(s64) = G_MERGE_VALUES %2(s32), %3
1121 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1122 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1123 %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
1124 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
1125 ; SOFT: ADJCALLSTACKDOWN
1126 ; SOFT-DAG: %r0 = COPY [[X0]]
1127 ; SOFT-DAG: %r1 = COPY [[X1]]
1128 ; SOFT-DAG: %r2 = COPY [[Y0]]
1129 ; SOFT-DAG: %r3 = COPY [[Y1]]
1130 ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1131 ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1132 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1133 ; SOFT: ADJCALLSTACKUP
1134 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1135 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1136 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
1137 %7(s32) = G_ZEXT %6(s1)
1138 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1139 %r0 = COPY %7(s32)
1140 ; CHECK: %r0 = COPY [[REXT]]
1141 BX_RET 14, _, implicit %r0
1142 ...
1143 ---
1144 name: test_fcmp_oge_s64
1145 # CHECK-LABEL: name: test_fcmp_oge_s64
1146 legalized: false
1147 # CHECK: legalized: true
1148 regBankSelected: false
1149 selected: false
1150 tracksRegLiveness: true
1151 registers:
1152 - { id: 0, class: _ }
1153 - { id: 1, class: _ }
1154 - { id: 2, class: _ }
1155 - { id: 3, class: _ }
1156 - { id: 4, class: _ }
1157 - { id: 5, class: _ }
1158 - { id: 6, class: _ }
1159 - { id: 7, class: _ }
1160 body: |
1161 bb.0:
1162 liveins: %r0, %r1, %r2, %r3
1163
1164 %0(s32) = COPY %r0
1165 %1(s32) = COPY %r1
1166 %2(s32) = COPY %r2
1167 %3(s32) = COPY %r3
1168 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1169 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1170 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1171 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1172 %4(s64) = G_MERGE_VALUES %0(s32), %1
1173 %5(s64) = G_MERGE_VALUES %2(s32), %3
1174 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1175 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1176 %6(s1) = G_FCMP floatpred(oge), %4(s64), %5
1177 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
1178 ; SOFT: ADJCALLSTACKDOWN
1179 ; SOFT-DAG: %r0 = COPY [[X0]]
1180 ; SOFT-DAG: %r1 = COPY [[X1]]
1181 ; SOFT-DAG: %r2 = COPY [[Y0]]
1182 ; SOFT-DAG: %r3 = COPY [[Y1]]
1183 ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1184 ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1185 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1186 ; SOFT: ADJCALLSTACKUP
1187 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1188 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1189 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
1190 %7(s32) = G_ZEXT %6(s1)
1191 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1192 %r0 = COPY %7(s32)
1193 ; CHECK: %r0 = COPY [[REXT]]
1194 BX_RET 14, _, implicit %r0
1195 ...
1196 ---
1197 name: test_fcmp_olt_s64
1198 # CHECK-LABEL: name: test_fcmp_olt_s64
1199 legalized: false
1200 # CHECK: legalized: true
1201 regBankSelected: false
1202 selected: false
1203 tracksRegLiveness: true
1204 registers:
1205 - { id: 0, class: _ }
1206 - { id: 1, class: _ }
1207 - { id: 2, class: _ }
1208 - { id: 3, class: _ }
1209 - { id: 4, class: _ }
1210 - { id: 5, class: _ }
1211 - { id: 6, class: _ }
1212 - { id: 7, class: _ }
1213 body: |
1214 bb.0:
1215 liveins: %r0, %r1, %r2, %r3
1216
1217 %0(s32) = COPY %r0
1218 %1(s32) = COPY %r1
1219 %2(s32) = COPY %r2
1220 %3(s32) = COPY %r3
1221 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1222 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1223 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1224 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1225 %4(s64) = G_MERGE_VALUES %0(s32), %1
1226 %5(s64) = G_MERGE_VALUES %2(s32), %3
1227 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1228 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1229 %6(s1) = G_FCMP floatpred(olt), %4(s64), %5
1230 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
1231 ; SOFT: ADJCALLSTACKDOWN
1232 ; SOFT-DAG: %r0 = COPY [[X0]]
1233 ; SOFT-DAG: %r1 = COPY [[X1]]
1234 ; SOFT-DAG: %r2 = COPY [[Y0]]
1235 ; SOFT-DAG: %r3 = COPY [[Y1]]
1236 ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1237 ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1238 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1239 ; SOFT: ADJCALLSTACKUP
1240 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1241 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1242 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
1243 %7(s32) = G_ZEXT %6(s1)
1244 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1245 %r0 = COPY %7(s32)
1246 ; CHECK: %r0 = COPY [[REXT]]
1247 BX_RET 14, _, implicit %r0
1248 ...
1249 ---
1250 name: test_fcmp_ole_s64
1251 # CHECK-LABEL: name: test_fcmp_ole_s64
1252 legalized: false
1253 # CHECK: legalized: true
1254 regBankSelected: false
1255 selected: false
1256 tracksRegLiveness: true
1257 registers:
1258 - { id: 0, class: _ }
1259 - { id: 1, class: _ }
1260 - { id: 2, class: _ }
1261 - { id: 3, class: _ }
1262 - { id: 4, class: _ }
1263 - { id: 5, class: _ }
1264 - { id: 6, class: _ }
1265 - { id: 7, class: _ }
1266 body: |
1267 bb.0:
1268 liveins: %r0, %r1, %r2, %r3
1269
1270 %0(s32) = COPY %r0
1271 %1(s32) = COPY %r1
1272 %2(s32) = COPY %r2
1273 %3(s32) = COPY %r3
1274 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1275 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1276 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1277 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1278 %4(s64) = G_MERGE_VALUES %0(s32), %1
1279 %5(s64) = G_MERGE_VALUES %2(s32), %3
1280 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1281 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1282 %6(s1) = G_FCMP floatpred(ole), %4(s64), %5
1283 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
1284 ; SOFT: ADJCALLSTACKDOWN
1285 ; SOFT-DAG: %r0 = COPY [[X0]]
1286 ; SOFT-DAG: %r1 = COPY [[X1]]
1287 ; SOFT-DAG: %r2 = COPY [[Y0]]
1288 ; SOFT-DAG: %r3 = COPY [[Y1]]
1289 ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1290 ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1291 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1292 ; SOFT: ADJCALLSTACKUP
1293 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1294 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1295 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
1296 %7(s32) = G_ZEXT %6(s1)
1297 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1298 %r0 = COPY %7(s32)
1299 ; CHECK: %r0 = COPY [[REXT]]
1300 BX_RET 14, _, implicit %r0
1301 ...
1302 ---
1303 name: test_fcmp_ord_s64
1304 # CHECK-LABEL: name: test_fcmp_ord_s64
1305 legalized: false
1306 # CHECK: legalized: true
1307 regBankSelected: false
1308 selected: false
1309 tracksRegLiveness: true
1310 registers:
1311 - { id: 0, class: _ }
1312 - { id: 1, class: _ }
1313 - { id: 2, class: _ }
1314 - { id: 3, class: _ }
1315 - { id: 4, class: _ }
1316 - { id: 5, class: _ }
1317 - { id: 6, class: _ }
1318 - { id: 7, class: _ }
1319 body: |
1320 bb.0:
1321 liveins: %r0, %r1, %r2, %r3
1322
1323 %0(s32) = COPY %r0
1324 %1(s32) = COPY %r1
1325 %2(s32) = COPY %r2
1326 %3(s32) = COPY %r3
1327 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1328 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1329 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1330 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1331 %4(s64) = G_MERGE_VALUES %0(s32), %1
1332 %5(s64) = G_MERGE_VALUES %2(s32), %3
1333 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1334 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1335 %6(s1) = G_FCMP floatpred(ord), %4(s64), %5
1336 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
1337 ; SOFT: ADJCALLSTACKDOWN
1338 ; SOFT-DAG: %r0 = COPY [[X0]]
1339 ; SOFT-DAG: %r1 = COPY [[X1]]
1340 ; SOFT-DAG: %r2 = COPY [[Y0]]
1341 ; SOFT-DAG: %r3 = COPY [[Y1]]
1342 ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1343 ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1344 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1345 ; SOFT: ADJCALLSTACKUP
1346 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1347 ; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1348 %7(s32) = G_ZEXT %6(s1)
1349 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1350 %r0 = COPY %7(s32)
1351 ; CHECK: %r0 = COPY [[REXT]]
1352 BX_RET 14, _, implicit %r0
1353 ...
1354 ---
1355 name: test_fcmp_ugt_s64
1356 # CHECK-LABEL: name: test_fcmp_ugt_s64
1357 legalized: false
1358 # CHECK: legalized: true
1359 regBankSelected: false
1360 selected: false
1361 tracksRegLiveness: true
1362 registers:
1363 - { id: 0, class: _ }
1364 - { id: 1, class: _ }
1365 - { id: 2, class: _ }
1366 - { id: 3, class: _ }
1367 - { id: 4, class: _ }
1368 - { id: 5, class: _ }
1369 - { id: 6, class: _ }
1370 - { id: 7, class: _ }
1371 body: |
1372 bb.0:
1373 liveins: %r0, %r1, %r2, %r3
1374
1375 %0(s32) = COPY %r0
1376 %1(s32) = COPY %r1
1377 %2(s32) = COPY %r2
1378 %3(s32) = COPY %r3
1379 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1380 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1381 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1382 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1383 %4(s64) = G_MERGE_VALUES %0(s32), %1
1384 %5(s64) = G_MERGE_VALUES %2(s32), %3
1385 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1386 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1387 %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5
1388 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
1389 ; SOFT: ADJCALLSTACKDOWN
1390 ; SOFT-DAG: %r0 = COPY [[X0]]
1391 ; SOFT-DAG: %r1 = COPY [[X1]]
1392 ; SOFT-DAG: %r2 = COPY [[Y0]]
1393 ; SOFT-DAG: %r3 = COPY [[Y1]]
1394 ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1395 ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1396 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1397 ; SOFT: ADJCALLSTACKUP
1398 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1399 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1400 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
1401 %7(s32) = G_ZEXT %6(s1)
1402 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1403 %r0 = COPY %7(s32)
1404 ; CHECK: %r0 = COPY [[REXT]]
1405 BX_RET 14, _, implicit %r0
1406 ...
1407 ---
1408 name: test_fcmp_uge_s64
1409 # CHECK-LABEL: name: test_fcmp_uge_s64
1410 legalized: false
1411 # CHECK: legalized: true
1412 regBankSelected: false
1413 selected: false
1414 tracksRegLiveness: true
1415 registers:
1416 - { id: 0, class: _ }
1417 - { id: 1, class: _ }
1418 - { id: 2, class: _ }
1419 - { id: 3, class: _ }
1420 - { id: 4, class: _ }
1421 - { id: 5, class: _ }
1422 - { id: 6, class: _ }
1423 - { id: 7, class: _ }
1424 body: |
1425 bb.0:
1426 liveins: %r0, %r1, %r2, %r3
1427
1428 %0(s32) = COPY %r0
1429 %1(s32) = COPY %r1
1430 %2(s32) = COPY %r2
1431 %3(s32) = COPY %r3
1432 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1433 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1434 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1435 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1436 %4(s64) = G_MERGE_VALUES %0(s32), %1
1437 %5(s64) = G_MERGE_VALUES %2(s32), %3
1438 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1439 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1440 %6(s1) = G_FCMP floatpred(uge), %4(s64), %5
1441 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
1442 ; SOFT: ADJCALLSTACKDOWN
1443 ; SOFT-DAG: %r0 = COPY [[X0]]
1444 ; SOFT-DAG: %r1 = COPY [[X1]]
1445 ; SOFT-DAG: %r2 = COPY [[Y0]]
1446 ; SOFT-DAG: %r3 = COPY [[Y1]]
1447 ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1448 ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1449 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1450 ; SOFT: ADJCALLSTACKUP
1451 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1452 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1453 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
1454 %7(s32) = G_ZEXT %6(s1)
1455 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1456 %r0 = COPY %7(s32)
1457 ; CHECK: %r0 = COPY [[REXT]]
1458 BX_RET 14, _, implicit %r0
1459 ...
1460 ---
1461 name: test_fcmp_ult_s64
1462 # CHECK-LABEL: name: test_fcmp_ult_s64
1463 legalized: false
1464 # CHECK: legalized: true
1465 regBankSelected: false
1466 selected: false
1467 tracksRegLiveness: true
1468 registers:
1469 - { id: 0, class: _ }
1470 - { id: 1, class: _ }
1471 - { id: 2, class: _ }
1472 - { id: 3, class: _ }
1473 - { id: 4, class: _ }
1474 - { id: 5, class: _ }
1475 - { id: 6, class: _ }
1476 - { id: 7, class: _ }
1477 body: |
1478 bb.0:
1479 liveins: %r0, %r1, %r2, %r3
1480
1481 %0(s32) = COPY %r0
1482 %1(s32) = COPY %r1
1483 %2(s32) = COPY %r2
1484 %3(s32) = COPY %r3
1485 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1486 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1487 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1488 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1489 %4(s64) = G_MERGE_VALUES %0(s32), %1
1490 %5(s64) = G_MERGE_VALUES %2(s32), %3
1491 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1492 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1493 %6(s1) = G_FCMP floatpred(ult), %4(s64), %5
1494 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
1495 ; SOFT: ADJCALLSTACKDOWN
1496 ; SOFT-DAG: %r0 = COPY [[X0]]
1497 ; SOFT-DAG: %r1 = COPY [[X1]]
1498 ; SOFT-DAG: %r2 = COPY [[Y0]]
1499 ; SOFT-DAG: %r3 = COPY [[Y1]]
1500 ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1501 ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1502 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1503 ; SOFT: ADJCALLSTACKUP
1504 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1505 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1506 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
1507 %7(s32) = G_ZEXT %6(s1)
1508 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1509 %r0 = COPY %7(s32)
1510 ; CHECK: %r0 = COPY [[REXT]]
1511 BX_RET 14, _, implicit %r0
1512 ...
1513 ---
1514 name: test_fcmp_ule_s64
1515 # CHECK-LABEL: name: test_fcmp_ule_s64
1516 legalized: false
1517 # CHECK: legalized: true
1518 regBankSelected: false
1519 selected: false
1520 tracksRegLiveness: true
1521 registers:
1522 - { id: 0, class: _ }
1523 - { id: 1, class: _ }
1524 - { id: 2, class: _ }
1525 - { id: 3, class: _ }
1526 - { id: 4, class: _ }
1527 - { id: 5, class: _ }
1528 - { id: 6, class: _ }
1529 - { id: 7, class: _ }
1530 body: |
1531 bb.0:
1532 liveins: %r0, %r1, %r2, %r3
1533
1534 %0(s32) = COPY %r0
1535 %1(s32) = COPY %r1
1536 %2(s32) = COPY %r2
1537 %3(s32) = COPY %r3
1538 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1539 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1540 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1541 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1542 %4(s64) = G_MERGE_VALUES %0(s32), %1
1543 %5(s64) = G_MERGE_VALUES %2(s32), %3
1544 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1545 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1546 %6(s1) = G_FCMP floatpred(ule), %4(s64), %5
1547 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
1548 ; SOFT: ADJCALLSTACKDOWN
1549 ; SOFT-DAG: %r0 = COPY [[X0]]
1550 ; SOFT-DAG: %r1 = COPY [[X1]]
1551 ; SOFT-DAG: %r2 = COPY [[Y0]]
1552 ; SOFT-DAG: %r3 = COPY [[Y1]]
1553 ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1554 ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1555 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1556 ; SOFT: ADJCALLSTACKUP
1557 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1558 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1559 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
1560 %7(s32) = G_ZEXT %6(s1)
1561 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1562 %r0 = COPY %7(s32)
1563 ; CHECK: %r0 = COPY [[REXT]]
1564 BX_RET 14, _, implicit %r0
1565 ...
1566 ---
1567 name: test_fcmp_une_s64
1568 # CHECK-LABEL: name: test_fcmp_une_s64
1569 legalized: false
1570 # CHECK: legalized: true
1571 regBankSelected: false
1572 selected: false
1573 tracksRegLiveness: true
1574 registers:
1575 - { id: 0, class: _ }
1576 - { id: 1, class: _ }
1577 - { id: 2, class: _ }
1578 - { id: 3, class: _ }
1579 - { id: 4, class: _ }
1580 - { id: 5, class: _ }
1581 - { id: 6, class: _ }
1582 - { id: 7, class: _ }
1583 body: |
1584 bb.0:
1585 liveins: %r0, %r1, %r2, %r3
1586
1587 %0(s32) = COPY %r0
1588 %1(s32) = COPY %r1
1589 %2(s32) = COPY %r2
1590 %3(s32) = COPY %r3
1591 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1592 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1593 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1594 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1595 %4(s64) = G_MERGE_VALUES %0(s32), %1
1596 %5(s64) = G_MERGE_VALUES %2(s32), %3
1597 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1598 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1599 %6(s1) = G_FCMP floatpred(une), %4(s64), %5
1600 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
1601 ; SOFT: ADJCALLSTACKDOWN
1602 ; SOFT-DAG: %r0 = COPY [[X0]]
1603 ; SOFT-DAG: %r1 = COPY [[X1]]
1604 ; SOFT-DAG: %r2 = COPY [[Y0]]
1605 ; SOFT-DAG: %r3 = COPY [[Y1]]
1606 ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1607 ; SOFT-DEFAULT: BLX $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1608 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1609 ; SOFT: ADJCALLSTACKUP
1610 ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1611 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
1612 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
1613 %7(s32) = G_ZEXT %6(s1)
1614 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1615 %r0 = COPY %7(s32)
1616 ; CHECK: %r0 = COPY [[REXT]]
1617 BX_RET 14, _, implicit %r0
1618 ...
1619 ---
1620 name: test_fcmp_uno_s64
1621 # CHECK-LABEL: name: test_fcmp_uno_s64
1622 legalized: false
1623 # CHECK: legalized: true
1624 regBankSelected: false
1625 selected: false
1626 tracksRegLiveness: true
1627 registers:
1628 - { id: 0, class: _ }
1629 - { id: 1, class: _ }
1630 - { id: 2, class: _ }
1631 - { id: 3, class: _ }
1632 - { id: 4, class: _ }
1633 - { id: 5, class: _ }
1634 - { id: 6, class: _ }
1635 - { id: 7, class: _ }
1636 body: |
1637 bb.0:
1638 liveins: %r0, %r1, %r2, %r3
1639
1640 %0(s32) = COPY %r0
1641 %1(s32) = COPY %r1
1642 %2(s32) = COPY %r2
1643 %3(s32) = COPY %r3
1644 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1645 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1646 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1647 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1648 %4(s64) = G_MERGE_VALUES %0(s32), %1
1649 %5(s64) = G_MERGE_VALUES %2(s32), %3
1650 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1651 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1652 %6(s1) = G_FCMP floatpred(uno), %4(s64), %5
1653 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
1654 ; SOFT: ADJCALLSTACKDOWN
1655 ; SOFT-DAG: %r0 = COPY [[X0]]
1656 ; SOFT-DAG: %r1 = COPY [[X1]]
1657 ; SOFT-DAG: %r2 = COPY [[Y0]]
1658 ; SOFT-DAG: %r3 = COPY [[Y1]]
1659 ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1660 ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1661 ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
1662 ; SOFT: ADJCALLSTACKUP
1663 ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
1664 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1665 ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
1666 %7(s32) = G_ZEXT %6(s1)
1667 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1668 %r0 = COPY %7(s32)
1669 ; CHECK: %r0 = COPY [[REXT]]
1670 BX_RET 14, _, implicit %r0
1671 ...
1672 ---
1673 name: test_fcmp_one_s64
1674 # CHECK-LABEL: name: test_fcmp_one_s64
1675 legalized: false
1676 # CHECK: legalized: true
1677 regBankSelected: false
1678 selected: false
1679 tracksRegLiveness: true
1680 registers:
1681 - { id: 0, class: _ }
1682 - { id: 1, class: _ }
1683 - { id: 2, class: _ }
1684 - { id: 3, class: _ }
1685 - { id: 4, class: _ }
1686 - { id: 5, class: _ }
1687 - { id: 6, class: _ }
1688 - { id: 7, class: _ }
1689 body: |
1690 bb.0:
1691 liveins: %r0, %r1, %r2, %r3
1692
1693 %0(s32) = COPY %r0
1694 %1(s32) = COPY %r1
1695 %2(s32) = COPY %r2
1696 %3(s32) = COPY %r3
1697 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1698 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1699 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1700 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1701 %4(s64) = G_MERGE_VALUES %0(s32), %1
1702 %5(s64) = G_MERGE_VALUES %2(s32), %3
1703 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1704 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1705 %6(s1) = G_FCMP floatpred(one), %4(s64), %5
1706 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
1707 ; SOFT: ADJCALLSTACKDOWN
1708 ; SOFT-DAG: %r0 = COPY [[X0]]
1709 ; SOFT-DAG: %r1 = COPY [[X1]]
1710 ; SOFT-DAG: %r2 = COPY [[Y0]]
1711 ; SOFT-DAG: %r3 = COPY [[Y1]]
1712 ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1713 ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1714 ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
1715 ; SOFT: ADJCALLSTACKUP
1716 ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]](s32)
1717 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1718 ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
1719 ; SOFT: ADJCALLSTACKDOWN
1720 ; SOFT-DAG: %r0 = COPY [[X0]]
1721 ; SOFT-DAG: %r1 = COPY [[X1]]
1722 ; SOFT-DAG: %r2 = COPY [[Y0]]
1723 ; SOFT-DAG: %r3 = COPY [[Y1]]
1724 ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1725 ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1726 ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
1727 ; SOFT: ADJCALLSTACKUP
1728 ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32)
1729 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1730 ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
1731 ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
1732 ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
1733 ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
1734 ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
1735 %7(s32) = G_ZEXT %6(s1)
1736 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1737 %r0 = COPY %7(s32)
1738 ; CHECK: %r0 = COPY [[REXT]]
1739 BX_RET 14, _, implicit %r0
1740 ...
1741 ---
1742 name: test_fcmp_ueq_s64
1743 # CHECK-LABEL: name: test_fcmp_ueq_s64
1744 legalized: false
1745 # CHECK: legalized: true
1746 regBankSelected: false
1747 selected: false
1748 tracksRegLiveness: true
1749 registers:
1750 - { id: 0, class: _ }
1751 - { id: 1, class: _ }
1752 - { id: 2, class: _ }
1753 - { id: 3, class: _ }
1754 - { id: 4, class: _ }
1755 - { id: 5, class: _ }
1756 - { id: 6, class: _ }
1757 - { id: 7, class: _ }
1758 body: |
1759 bb.0:
1760 liveins: %r0, %r1, %r2, %r3
1761
1762 %0(s32) = COPY %r0
1763 %1(s32) = COPY %r1
1764 %2(s32) = COPY %r2
1765 %3(s32) = COPY %r3
1766 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
1767 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
1768 ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
1769 ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
1770 %4(s64) = G_MERGE_VALUES %0(s32), %1
1771 %5(s64) = G_MERGE_VALUES %2(s32), %3
1772 ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
1773 ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
1774 %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
1775 ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
1776 ; SOFT: ADJCALLSTACKDOWN
1777 ; SOFT-DAG: %r0 = COPY [[X0]]
1778 ; SOFT-DAG: %r1 = COPY [[X1]]
1779 ; SOFT-DAG: %r2 = COPY [[Y0]]
1780 ; SOFT-DAG: %r3 = COPY [[Y1]]
1781 ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1782 ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1783 ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
1784 ; SOFT: ADJCALLSTACKUP
1785 ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]](s32)
1786 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1787 ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
1788 ; SOFT: ADJCALLSTACKDOWN
1789 ; SOFT-DAG: %r0 = COPY [[X0]]
1790 ; SOFT-DAG: %r1 = COPY [[X1]]
1791 ; SOFT-DAG: %r2 = COPY [[Y0]]
1792 ; SOFT-DAG: %r3 = COPY [[Y1]]
1793 ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1794 ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
1795 ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
1796 ; SOFT: ADJCALLSTACKUP
1797 ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32)
1798 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
1799 ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
1800 ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
1801 ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
1802 ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
1803 ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
1804 %7(s32) = G_ZEXT %6(s1)
1805 ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
1806 %r0 = COPY %7(s32)
1807 ; CHECK: %r0 = COPY [[REXT]]
1808 BX_RET 14, _, implicit %r0
1809 ...