llvm.org GIT mirror llvm / 683224e
[ARM] Unify handling of M-Class system registers This patch cleans up and fixes issues in the M-Class system register handling: 1. It defines the system registers and the encoding (SYSm values) in one place: a new ARMSystemRegister.td using SearchableTable, thereby removing the hand-coded values which existed in multiple places. 2. Some system registers e.g. BASEPRI_MAX_NS which do not exist were being allowed! Ref: ARMv6/7/8M architecture reference manual. Reviewed by: @t.p.northover, @olist01, @john.brawn Differential Revision: https://reviews.llvm.org/D35209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308456 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
15 changed file(s) with 294 addition(s) and 303 deletion(s). Raw diff Collapse all Expand all
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "ARM.h"
14 #include "Utils/ARMBaseInfo.h"
1415 #include "ARMBaseInstrInfo.h"
1516 #include "ARMTargetMachine.h"
1617 #include "MCTargetDesc/ARMAddressingModes.h"
38003801 .Default(-1);
38013802 }
38023803
3803 // Maps a MClass special register string to its value for use in the
3804 // t2MRS_M / t2MSR_M instruction nodes as the SYSm value operand.
3805 // Returns -1 to signify that the string was invalid.
3806 static inline int getMClassRegisterSYSmValueMask(StringRef RegString) {
3807 return StringSwitch(RegString.lower())
3808 .Case("apsr", 0x0)
3809 .Case("iapsr", 0x1)
3810 .Case("eapsr", 0x2)
3811 .Case("xpsr", 0x3)
3812 .Case("ipsr", 0x5)
3813 .Case("epsr", 0x6)
3814 .Case("iepsr", 0x7)
3815 .Case("msp", 0x8)
3816 .Case("psp", 0x9)
3817 .Case("primask", 0x10)
3818 .Case("basepri", 0x11)
3819 .Case("basepri_max", 0x12)
3820 .Case("faultmask", 0x13)
3821 .Case("control", 0x14)
3822 .Case("msplim", 0x0a)
3823 .Case("psplim", 0x0b)
3824 .Case("sp", 0x18)
3825 .Default(-1);
3826 }
3827
38283804 // The flags here are common to those allowed for apsr in the A class cores and
38293805 // those allowed for the special registers in the M class cores. Returns a
38303806 // value representing which flags were present, -1 if invalid.
38383814 .Default(-1);
38393815 }
38403816
3841 static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead,
3842 const ARMSubtarget *Subtarget) {
3843 // Ensure that the register (without flags) was a valid M Class special
3844 // register.
3845 int SYSmvalue = getMClassRegisterSYSmValueMask(Reg);
3846 if (SYSmvalue == -1)
3817 // Maps MClass special registers string to its value for use in the
3818 // t2MRS_M/t2MSR_M instruction nodes as the SYSm value operand.
3819 // Returns -1 to signify that the string was invalid.
3820 static int getMClassRegisterMask(StringRef Reg, const ARMSubtarget *Subtarget) {
3821 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Reg);
3822 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits();
3823 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits))
38473824 return -1;
3848
3849 // basepri, basepri_max and faultmask are only valid for V7m.
3850 if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)
3851 return -1;
3852
3853 if (Subtarget->has8MSecExt() && Flags.lower() == "ns") {
3854 Flags = "";
3855 SYSmvalue |= 0x80;
3856 }
3857
3858 if (!Subtarget->has8MSecExt() &&
3859 (SYSmvalue == 0xa || SYSmvalue == 0xb || SYSmvalue > 0x14))
3860 return -1;
3861
3862 if (!Subtarget->hasV8MMainlineOps() &&
3863 (SYSmvalue == 0x8a || SYSmvalue == 0x8b || SYSmvalue == 0x91 ||
3864 SYSmvalue == 0x93))
3865 return -1;
3866
3867 // If it was a read then we won't be expecting flags and so at this point
3868 // we can return the mask.
3869 if (IsRead) {
3870 if (Flags.empty())
3871 return SYSmvalue;
3872 else
3873 return -1;
3874 }
3875
3876 // We know we are now handling a write so need to get the mask for the flags.
3877 int Mask = getMClassFlagsMask(Flags);
3878
3879 // Only apsr, iapsr, eapsr, xpsr can have flags. The other register values
3880 // shouldn't have flags present.
3881 if ((SYSmvalue < 0x4 && Mask == -1) || (SYSmvalue > 0x4 && !Flags.empty()))
3882 return -1;
3883
3884 // The _g and _nzcvqg versions are only valid if the DSP extension is
3885 // available.
3886 if (!Subtarget->hasDSP() && (Mask & 0x1))
3887 return -1;
3888
3889 // The register was valid so need to put the mask in the correct place
3890 // (the flags need to be in bits 11-10) and combine with the SYSmvalue to
3891 // construct the operand for the instruction node.
3892 return SYSmvalue | Mask << 10;
3825 return (int)(TheReg->Encoding & 0xFFF); // SYSm value
38933826 }
38943827
38953828 static int getARClassRegisterMask(StringRef Reg, StringRef Flags) {
40313964 // is an acceptable value, so check that a mask can be constructed from the
40323965 // string.
40333966 if (Subtarget->isMClass()) {
4034 StringRef Flags = "", Reg = SpecialReg;
4035 if (Reg.endswith("_ns")) {
4036 Flags = "ns";
4037 Reg = Reg.drop_back(3);
4038 }
4039
4040 int SYSmValue = getMClassRegisterMask(Reg, Flags, true, Subtarget);
3967 int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
40413968 if (SYSmValue == -1)
40423969 return false;
40433970
41484075 // If the target was M Class then need to validate the special register value
41494076 // and retrieve the mask for use in the instruction node.
41504077 if (Subtarget->isMClass()) {
4151 // basepri_max gets split so need to correct Reg and Flags.
4152 if (SpecialReg == "basepri_max") {
4153 Reg = SpecialReg;
4154 Flags = "";
4155 }
4156 int SYSmValue = getMClassRegisterMask(Reg, Flags, false, Subtarget);
4078 int SYSmValue = getMClassRegisterMask(SpecialReg, Subtarget);
41574079 if (SYSmValue == -1)
41584080 return false;
41594081
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8
9 include "ARMSystemRegister.td"
810
911 //===----------------------------------------------------------------------===//
1012 // Declarations that describe the ARM register file
0 //===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 include "llvm/TableGen/SearchableTable.td"
10
11 //===----------------------------------------------------------------------===//
12 // Declarations that describe the ARM system-registers
13 //===----------------------------------------------------------------------===//
14
15 // M-Class System Registers.
16 // 'Mask' bits create unique keys for searches.
17 //
18 class MClassSysReg UniqMask1,
19 bits<1> UniqMask2,
20 bits<1> UniqMask3,
21 bits<12> Enc12,
22 string name> : SearchableTable {
23 let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
24 string Name;
25 bits<13> M1Encoding12;
26 bits<10> M2M3Encoding8;
27 bits<12> Encoding;
28
29 let Name = name;
30 let EnumValueField = "M1Encoding12";
31 let EnumValueField = "M2M3Encoding8";
32 let EnumValueField = "Encoding";
33
34 let M1Encoding12{12} = UniqMask1;
35 let M1Encoding12{11-00} = Enc12;
36 let Encoding = Enc12;
37
38 let M2M3Encoding8{9} = UniqMask2;
39 let M2M3Encoding8{8} = UniqMask3;
40 let M2M3Encoding8{7-0} = Enc12{7-0};
41 code Requires = [{ {} }];
42 }
43
44 // [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
45 // Mask1 Mask2 Mask3 Enc12, Name
46 let Requires = [{ {ARM::FeatureDSP} }] in {
47 def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">;
48 def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">;
49 def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">;
50 def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">;
51 def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">;
52 def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">;
53 def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">;
54 def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">;
55 }
56
57 def : MClassSysReg<0, 0, 1, 0x800, "apsr">;
58 def : MClassSysReg<1, 1, 0, 0x800, "apsr_nzcvq">;
59 def : MClassSysReg<0, 0, 1, 0x801, "iapsr">;
60 def : MClassSysReg<1, 1, 0, 0x801, "iapsr_nzcvq">;
61 def : MClassSysReg<0, 0, 1, 0x802, "eapsr">;
62 def : MClassSysReg<1, 1, 0, 0x802, "eapsr_nzcvq">;
63 def : MClassSysReg<0, 0, 1, 0x803, "xpsr">;
64 def : MClassSysReg<1, 1, 0, 0x803, "xpsr_nzcvq">;
65
66 def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
67 def : MClassSysReg<0, 0, 1, 0x806, "epsr">;
68 def : MClassSysReg<0, 0, 1, 0x807, "iepsr">;
69 def : MClassSysReg<0, 0, 1, 0x808, "msp">;
70 def : MClassSysReg<0, 0, 1, 0x809, "psp">;
71
72 let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
73 def : MClassSysReg<0, 0, 1, 0x80a, "msplim">;
74 def : MClassSysReg<0, 0, 1, 0x80b, "psplim">;
75 }
76
77 def : MClassSysReg<0, 0, 1, 0x810, "primask">;
78
79 let Requires = [{ {ARM::HasV7Ops} }] in {
80 def : MClassSysReg<0, 0, 1, 0x811, "basepri">;
81 def : MClassSysReg<0, 0, 1, 0x812, "basepri_max">;
82 def : MClassSysReg<0, 0, 1, 0x813, "faultmask">;
83 }
84
85 def : MClassSysReg<0, 0, 1, 0x814, "control">;
86
87 let Requires = [{ {ARM::Feature8MSecExt} }] in {
88 def : MClassSysReg<0, 0, 1, 0x888, "msp_ns">;
89 def : MClassSysReg<0, 0, 1, 0x889, "psp_ns">;
90 }
91
92 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
93 def : MClassSysReg<0, 0, 1, 0x88a, "msplim_ns">;
94 def : MClassSysReg<0, 0, 1, 0x88b, "psplim_ns">;
95 }
96
97 def : MClassSysReg<0, 0, 1, 0x890, "primask_ns">;
98
99 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
100 def : MClassSysReg<0, 0, 1, 0x891, "basepri_ns">;
101 def : MClassSysReg<0, 0, 1, 0x893, "faultmask_ns">;
102 }
103
104 let Requires = [{ {ARM::Feature8MSecExt} }] in {
105 def : MClassSysReg<0, 0, 1, 0x894, "control_ns">;
106 def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">;
107 }
77 //===----------------------------------------------------------------------===//
88
99 #include "ARMFeatures.h"
10 #include "Utils/ARMBaseInfo.h"
1011 #include "MCTargetDesc/ARMAddressingModes.h"
1112 #include "MCTargetDesc/ARMBaseInfo.h"
1213 #include "MCTargetDesc/ARMMCExpr.h"
40884089 StringRef Mask = Tok.getString();
40894090
40904091 if (isMClass()) {
4091 // See ARMv6-M 10.1.1
4092 std::string Name = Mask.lower();
4093 unsigned FlagsVal = StringSwitch(Name)
4094 // Note: in the documentation:
4095 // ARM deprecates using MSR APSR without a _ qualifier as an alias
4096 // for MSR APSR_nzcvq.
4097 // but we do make it an alias here. This is so to get the "mask encoding"
4098 // bits correct on MSR APSR writes.
4099 //
4100 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4101 // should really only be allowed when writing a special register. Note
4102 // they get dropped in the MRS instruction reading a special register as
4103 // the SYSm field is only 8 bits.
4104 .Case("apsr", 0x800)
4105 .Case("apsr_nzcvq", 0x800)
4106 .Case("apsr_g", 0x400)
4107 .Case("apsr_nzcvqg", 0xc00)
4108 .Case("iapsr", 0x801)
4109 .Case("iapsr_nzcvq", 0x801)
4110 .Case("iapsr_g", 0x401)
4111 .Case("iapsr_nzcvqg", 0xc01)
4112 .Case("eapsr", 0x802)
4113 .Case("eapsr_nzcvq", 0x802)
4114 .Case("eapsr_g", 0x402)
4115 .Case("eapsr_nzcvqg", 0xc02)
4116 .Case("xpsr", 0x803)
4117 .Case("xpsr_nzcvq", 0x803)
4118 .Case("xpsr_g", 0x403)
4119 .Case("xpsr_nzcvqg", 0xc03)
4120 .Case("ipsr", 0x805)
4121 .Case("epsr", 0x806)
4122 .Case("iepsr", 0x807)
4123 .Case("msp", 0x808)
4124 .Case("psp", 0x809)
4125 .Case("primask", 0x810)
4126 .Case("basepri", 0x811)
4127 .Case("basepri_max", 0x812)
4128 .Case("faultmask", 0x813)
4129 .Case("control", 0x814)
4130 .Case("msplim", 0x80a)
4131 .Case("psplim", 0x80b)
4132 .Case("msp_ns", 0x888)
4133 .Case("psp_ns", 0x889)
4134 .Case("msplim_ns", 0x88a)
4135 .Case("psplim_ns", 0x88b)
4136 .Case("primask_ns", 0x890)
4137 .Case("basepri_ns", 0x891)
4138 .Case("basepri_max_ns", 0x892)
4139 .Case("faultmask_ns", 0x893)
4140 .Case("control_ns", 0x894)
4141 .Case("sp_ns", 0x898)
4142 .Default(~0U);
4143
4144 if (FlagsVal == ~0U)
4092 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4093 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
41454094 return MatchOperand_NoMatch;
41464095
4147 if (!hasDSP() && (FlagsVal & 0x400))
4148 // The _g and _nzcvqg versions are only valid if the DSP extension is
4149 // available.
4150 return MatchOperand_NoMatch;
4151
4152 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4153 // basepri, basepri_max and faultmask only valid for V7m.
4154 return MatchOperand_NoMatch;
4155
4156 if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
4157 (FlagsVal > 0x814 && FlagsVal < 0xc00)))
4158 return MatchOperand_NoMatch;
4159
4160 if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
4161 (FlagsVal > 0x890 && FlagsVal <= 0x893)))
4162 return MatchOperand_NoMatch;
4096 unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
41634097
41644098 Parser.Lex(); // Eat identifier token.
4165 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4099 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
41664100 return MatchOperand_Success;
41674101 }
41684102
1818 type = Library
1919 name = ARMAsmParser
2020 parent = ARM
21 required_libraries = ARMDesc ARMInfo MC MCParser Support
21 required_libraries = ARMDesc ARMInfo MC MCParser Support ARMUtils
2222 add_to_library_groups = ARM
1414 tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
1515 tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
1616 tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
17 tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)
1718 add_public_tablegen_target(ARMCommonTableGen)
1819
1920 # Add GlobalISel files if the user wants to build it.
7273 add_subdirectory(Disassembler)
7374 add_subdirectory(InstPrinter)
7475 add_subdirectory(MCTargetDesc)
76 add_subdirectory(Utils)
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "ARMInstPrinter.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseRegisterInfo.h"
1417 #include "MCTargetDesc/ARMAddressingModes.h"
1518 #include "MCTargetDesc/ARMBaseInfo.h"
1619 #include "llvm/MC/MCAsmInfo.h"
788791 const MCSubtargetInfo &STI,
789792 raw_ostream &O) {
790793 const MCOperand &Op = MI->getOperand(OpNum);
791 unsigned SpecRegRBit = Op.getImm() >> 4;
792 unsigned Mask = Op.getImm() & 0xf;
793794 const FeatureBitset &FeatureBits = STI.getFeatureBits();
794
795795 if (FeatureBits[ARM::FeatureMClass]) {
796 unsigned SYSm = Op.getImm();
796
797 unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
797798 unsigned Opcode = MI->getOpcode();
798799
799800 // For writes, handle extended mask bits if the DSP extension is present.
800801 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
801 switch (SYSm) {
802 case 0x400:
803 O << "apsr_g";
804 return;
805 case 0xc00:
806 O << "apsr_nzcvqg";
807 return;
808 case 0x401:
809 O << "iapsr_g";
810 return;
811 case 0xc01:
812 O << "iapsr_nzcvqg";
813 return;
814 case 0x402:
815 O << "eapsr_g";
816 return;
817 case 0xc02:
818 O << "eapsr_nzcvqg";
819 return;
820 case 0x403:
821 O << "xpsr_g";
822 return;
823 case 0xc03:
824 O << "xpsr_nzcvqg";
825 return;
802 auto TheReg =ARMSysReg::lookupMClassSysRegBy12bitSYSmValue(SYSm);
803 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
804 O << TheReg->Name;
805 return;
826806 }
827807 }
828808
829809 // Handle the basic 8-bit mask.
830810 SYSm &= 0xff;
831
832811 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
833812 // ARMv7-M deprecates using MSR APSR without a _ qualifier as an
834813 // alias for MSR APSR_nzcvq.
835 switch (SYSm) {
836 case 0:
837 O << "apsr_nzcvq";
838 return;
839 case 1:
840 O << "iapsr_nzcvq";
841 return;
842 case 2:
843 O << "eapsr_nzcvq";
844 return;
845 case 3:
846 O << "xpsr_nzcvq";
847 return;
814 auto TheReg = ARMSysReg::lookupMClassSysRegAPSRNonDeprecated(SYSm);
815 if (TheReg) {
816 O << TheReg->Name;
817 return;
848818 }
849819 }
850820
851 switch (SYSm) {
852 default:
853 llvm_unreachable("Unexpected mask value!");
854 case 0:
855 O << "apsr";
856 return;
857 case 1:
858 O << "iapsr";
859 return;
860 case 2:
861 O << "eapsr";
862 return;
863 case 3:
864 O << "xpsr";
865 return;
866 case 5:
867 O << "ipsr";
868 return;
869 case 6:
870 O << "epsr";
871 return;
872 case 7:
873 O << "iepsr";
874 return;
875 case 8:
876 O << "msp";
877 return;
878 case 9:
879 O << "psp";
880 return;
881 case 16:
882 O << "primask";
883 return;
884 case 17:
885 O << "basepri";
886 return;
887 case 18:
888 O << "basepri_max";
889 return;
890 case 19:
891 O << "faultmask";
892 return;
893 case 20:
894 O << "control";
895 return;
896 case 10:
897 O << "msplim";
898 return;
899 case 11:
900 O << "psplim";
901 return;
902 case 0x88:
903 O << "msp_ns";
904 return;
905 case 0x89:
906 O << "psp_ns";
907 return;
908 case 0x8a:
909 O << "msplim_ns";
910 return;
911 case 0x8b:
912 O << "psplim_ns";
913 return;
914 case 0x90:
915 O << "primask_ns";
916 return;
917 case 0x91:
918 O << "basepri_ns";
919 return;
920 case 0x92:
921 O << "basepri_max_ns";
922 return;
923 case 0x93:
924 O << "faultmask_ns";
925 return;
926 case 0x94:
927 O << "control_ns";
928 return;
929 case 0x98:
930 O << "sp_ns";
821 auto TheReg = ARMSysReg::lookupMClassSysRegBy8bitSYSmValue(SYSm);
822 if (TheReg) {
823 O << TheReg->Name;
931824 return;
932825 }
826
827 llvm_unreachable("Unexpected mask value!");
828 return;
933829 }
934830
935831 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
936832 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
833 unsigned SpecRegRBit = Op.getImm() >> 4;
834 unsigned Mask = Op.getImm() & 0xf;
835
937836 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
938837 O << "APSR_";
939838 switch (Mask) {
1818 type = Library
1919 name = ARMAsmPrinter
2020 parent = ARM
21 required_libraries = MC Support
21 required_libraries = MC Support ARMUtils
2222 add_to_library_groups = ARM
1515 ;===------------------------------------------------------------------------===;
1616
1717 [common]
18 subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
18 subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
1919
2020 [component_0]
2121 type = TargetGroup
3030 type = Library
3131 name = ARMCodeGen
3232 parent = ARM
33 required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel
33 required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils
3434 add_to_library_groups = ARM
0 //===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides basic encoding and assembly information for ARM.
10 //
11 //===----------------------------------------------------------------------===//
12 #include "ARMBaseInfo.h"
13 #include "llvm/ADT/ArrayRef.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Support/Regex.h"
17
18 using namespace llvm;
19 namespace llvm {
20 namespace ARMSysReg {
21
22 // lookup system register using 12-bit SYSm value.
23 // Note: the search is uniqued using M1 mask
24 const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) {
25 return lookupMClassSysRegByM1Encoding12(SYSm);
26 }
27
28 // returns APSR with _ qualifier.
29 // Note: ARMv7-M deprecates using MSR APSR without a _ qualifier
30 const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) {
31 return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF));
32 }
33
34 // lookup system registers using 8-bit SYSm value
35 const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) {
36 return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF));
37 }
38
39 #define GET_MCLASSSYSREG_IMPL
40 #include "ARMGenSystemRegister.inc"
41
42 }
43 }
0 //===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the ARM target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15
16 #ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
17 #define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
18
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/MC/SubtargetFeature.h"
22 #include "MCTargetDesc/ARMMCTargetDesc.h"
23
24 namespace llvm {
25
26 namespace ARMSysReg {
27 struct MClassSysReg {
28 const char *Name;
29 uint16_t M1Encoding12;
30 uint16_t M2M3Encoding8;
31 uint16_t Encoding;
32 FeatureBitset FeaturesRequired;
33
34 // return true if FeaturesRequired are all present in ActiveFeatures
35 bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
36 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
37 }
38
39 // returns true if TestFeatures are all present in FeaturesRequired
40 bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
41 return (FeaturesRequired & TestFeatures) == TestFeatures;
42 }
43 };
44
45 #define GET_MCLASSSYSREG_DECL
46 #include "ARMGenSystemRegister.inc"
47
48 // lookup system register using 12-bit SYSm value.
49 // Note: the search is uniqued using M1 mask
50 const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
51
52 // returns APSR with _ qualifier.
53 // Note: ARMv7-M deprecates using MSR APSR without a _ qualifier
54 const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
55
56 // lookup system registers using 8-bit SYSm value
57 const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
58
59 } // end namespace ARMSysReg
60
61 } // end namespace llvm
62
63 #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
0 add_llvm_library(LLVMARMUtils
1 ARMBaseInfo.cpp
2 )
0 ;===- ./lib/Target/ARM/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = ARMUtils
20 parent = ARM
21 required_libraries = Support
22 add_to_library_groups = ARM
23
0 ; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE
11 ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE
22
3 ; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns".
3 ; BASELINE: LLVM ERROR: Invalid register name "faultmask_ns".
44
55 define i32 @read_mclass_registers() nounwind {
66 entry:
3030 ; MAINLINE: mrs r1, faultmask_ns
3131 ; MAINLINE: mrs r1, control_ns
3232 ; MAINLINE: mrs r1, sp_ns
33 ; MAINLINE: mrs r1, basepri_max_ns
3433
3534 %0 = call i32 @llvm.read_register.i32(metadata !0)
3635 %1 = call i32 @llvm.read_register.i32(metadata !4)
8180 %add23 = add i32 %add22, %23
8281 %24 = call i32 @llvm.read_register.i32(metadata !36)
8382 %add24 = add i32 %add23, %24
84 %25 = call i32 @llvm.read_register.i32(metadata !37)
85 %add25 = add i32 %add24, %25
86 ret i32 %add25
83 ret i32 %add24
8784 }
8885
8986 define void @write_mclass_registers(i32 %x) nounwind {
126123 ; MAINLINE: msr faultmask_ns, r0
127124 ; MAINLINE: msr control_ns, r0
128125 ; MAINLINE: msr sp_ns, r0
129 ; MAINLINE: msr basepri_max_ns, r0
130126
131127 call void @llvm.write_register.i32(metadata !0, i32 %x)
132128 call void @llvm.write_register.i32(metadata !1, i32 %x)
165161 call void @llvm.write_register.i32(metadata !34, i32 %x)
166162 call void @llvm.write_register.i32(metadata !35, i32 %x)
167163 call void @llvm.write_register.i32(metadata !36, i32 %x)
168 call void @llvm.write_register.i32(metadata !37, i32 %x)
169164 ret void
170165 }
171166
209204 !34 = !{!"faultmask_ns"}
210205 !35 = !{!"control_ns"}
211206 !36 = !{!"sp_ns"}
212 !37 = !{!"basepri_max_ns"}
213
207
214214 // CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
215215
216216 MRS r10, MSPLIM_NS
217 // CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
218 // UNDEF-BASELINE: error: invalid operand for instruction
217 // CHECK: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
219218 MSR PSPLIM_NS, r11
220 // CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
221 // UNDEF-BASELINE: error: invalid operand for instruction
219 // CHECK: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
222220 MRS r12, BASEPRI_NS
223221 // CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
224222 // UNDEF-BASELINE: error: invalid operand for instruction
225 MRS r12, BASEPRI_MAX_NS
226 // CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]
227 // UNDEF-BASELINE: error: invalid operand for instruction
228223 MSR FAULTMASK_NS, r14
229224 // CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
230225 // UNDEF-BASELINE: error: invalid operand for instruction