llvm.org GIT mirror llvm / 6824f12
[SystemZ] Be more careful about inverting CC masks System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Sandiford 6 years ago
56 changed file(s) with 289 addition(s) and 208 deletion(s). Raw diff Collapse all Expand all
2929 const unsigned CCMASK_3 = 1 << 0;
3030 const unsigned CCMASK_ANY = CCMASK_0 | CCMASK_1 | CCMASK_2 | CCMASK_3;
3131
32 // Condition-code mask assignments for floating-point comparisons.
32 // Condition-code mask assignments for integer and floating-point
33 // comparisons.
3334 const unsigned CCMASK_CMP_EQ = CCMASK_0;
3435 const unsigned CCMASK_CMP_LT = CCMASK_1;
3536 const unsigned CCMASK_CMP_GT = CCMASK_2;
36 const unsigned CCMASK_CMP_UO = CCMASK_3;
3737 const unsigned CCMASK_CMP_NE = CCMASK_CMP_LT | CCMASK_CMP_GT;
3838 const unsigned CCMASK_CMP_LE = CCMASK_CMP_EQ | CCMASK_CMP_LT;
3939 const unsigned CCMASK_CMP_GE = CCMASK_CMP_EQ | CCMASK_CMP_GT;
40
41 // Condition-code mask assignments for floating-point comparisons only.
42 const unsigned CCMASK_CMP_UO = CCMASK_3;
4043 const unsigned CCMASK_CMP_O = CCMASK_ANY ^ CCMASK_CMP_UO;
44
45 // All condition-code values produced by comparisons.
46 const unsigned CCMASK_ICMP = CCMASK_0 | CCMASK_1 | CCMASK_2;
47 const unsigned CCMASK_FCMP = CCMASK_0 | CCMASK_1 | CCMASK_2 | CCMASK_3;
48
49 // Condition-code mask assignments for CS.
50 const unsigned CCMASK_CS_EQ = CCMASK_0;
51 const unsigned CCMASK_CS_NE = CCMASK_1;
52 const unsigned CCMASK_CS = CCMASK_0 | CCMASK_1;
4153
4254 // Return true if Val fits an LLILL operand.
4355 static inline bool isImmLL(uint64_t Val) {
10141014 return false;
10151015 }
10161016
1017 // Return a target node that compares CmpOp0 and CmpOp1. Set CCMask to the
1018 // 4-bit condition-code mask for CC.
1017 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1018 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1019 // 2-bit results and CCMask to the subset of those results that are
1020 // associated with Cond.
10191021 static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1020 ISD::CondCode CC, unsigned &CCMask) {
1022 ISD::CondCode Cond, unsigned &CCValid,
1023 unsigned &CCMask) {
10211024 bool IsUnsigned = false;
1022 CCMask = CCMaskForCondCode(CC);
1023 if (!CmpOp0.getValueType().isFloatingPoint()) {
1025 CCMask = CCMaskForCondCode(Cond);
1026 if (CmpOp0.getValueType().isFloatingPoint())
1027 CCValid = SystemZ::CCMASK_FCMP;
1028 else {
10241029 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1025 CCMask &= ~SystemZ::CCMASK_CMP_UO;
1030 CCValid = SystemZ::CCMASK_ICMP;
1031 CCMask &= CCValid;
10261032 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
10271033 if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
10281034 IsUnsigned = true;
10641070 SDValue Dest = Op.getOperand(4);
10651071 SDLoc DL(Op);
10661072
1067 unsigned CCMask;
1068 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCMask);
1073 unsigned CCValid, CCMask;
1074 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
10691075 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1070 Chain, DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1076 Chain, DAG.getConstant(CCValid, MVT::i32),
1077 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
10711078 }
10721079
10731080 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
10791086 ISD::CondCode CC = cast(Op.getOperand(4))->get();
10801087 SDLoc DL(Op);
10811088
1082 unsigned CCMask;
1083 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCMask);
1084
1085 SmallVector Ops;
1089 unsigned CCValid, CCMask;
1090 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1091
1092 SmallVector Ops;
10861093 Ops.push_back(TrueOp);
10871094 Ops.push_back(FalseOp);
1095 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
10881096 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
10891097 Ops.push_back(Flags);
10901098
17031711 unsigned DestReg = MI->getOperand(0).getReg();
17041712 unsigned TrueReg = MI->getOperand(1).getReg();
17051713 unsigned FalseReg = MI->getOperand(2).getReg();
1706 unsigned CCMask = MI->getOperand(3).getImm();
1714 unsigned CCValid = MI->getOperand(3).getImm();
1715 unsigned CCMask = MI->getOperand(4).getImm();
17071716 DebugLoc DL = MI->getDebugLoc();
17081717
17091718 MachineBasicBlock *StartMBB = MBB;
17141723 // BRC CCMask, JoinMBB
17151724 // # fallthrough to FalseMBB
17161725 MBB = StartMBB;
1717 BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(CCMask).addMBB(JoinMBB);
1726 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1727 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
17181728 MBB->addSuccessor(JoinMBB);
17191729 MBB->addSuccessor(FalseMBB);
17201730
17501760 MachineOperand Base = MI->getOperand(1);
17511761 int64_t Disp = MI->getOperand(2).getImm();
17521762 unsigned IndexReg = MI->getOperand(3).getReg();
1753 unsigned CCMask = MI->getOperand(4).getImm();
1763 unsigned CCValid = MI->getOperand(4).getImm();
1764 unsigned CCMask = MI->getOperand(5).getImm();
17541765 DebugLoc DL = MI->getDebugLoc();
17551766
17561767 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
17601771 // might be more complicated in that case.
17611772 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
17621773 if (Invert)
1763 CCMask = CCMask ^ SystemZ::CCMASK_ANY;
1774 CCMask ^= CCValid;
17641775 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
17651776 .addReg(SrcReg).addOperand(Base).addImm(Disp).addImm(CCMask);
17661777 MI->eraseFromParent();
17691780
17701781 // Get the condition needed to branch around the store.
17711782 if (!Invert)
1772 CCMask = CCMask ^ SystemZ::CCMASK_ANY;
1783 CCMask ^= CCValid;
17731784
17741785 MachineBasicBlock *StartMBB = MBB;
17751786 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
17791790 // BRC CCMask, JoinMBB
17801791 // # fallthrough to FalseMBB
17811792 MBB = StartMBB;
1782 BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(CCMask).addMBB(JoinMBB);
1793 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1794 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
17831795 MBB->addSuccessor(JoinMBB);
17841796 MBB->addSuccessor(FalseMBB);
17851797
18111823 const SystemZInstrInfo *TII = TM.getInstrInfo();
18121824 MachineFunction &MF = *MBB->getParent();
18131825 MachineRegisterInfo &MRI = MF.getRegInfo();
1814 unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
18151826 bool IsSubWord = (BitSize < 32);
18161827
18171828 // Extract the operands. Base can be a register or a frame index.
19111922 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
19121923 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
19131924 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
1914 BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
1925 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1926 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
19151927 MBB->addSuccessor(LoopMBB);
19161928 MBB->addSuccessor(DoneMBB);
19171929
19341946 const SystemZInstrInfo *TII = TM.getInstrInfo();
19351947 MachineFunction &MF = *MBB->getParent();
19361948 MachineRegisterInfo &MRI = MF.getRegInfo();
1937 unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
19381949 bool IsSubWord = (BitSize < 32);
19391950
19401951 // Extract the operands. Base can be a register or a frame index.
19992010 BuildMI(MBB, DL, TII->get(CompareOpcode))
20002011 .addReg(RotatedOldVal).addReg(Src2);
20012012 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2002 .addImm(KeepOldMask).addMBB(UpdateMBB);
2013 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
20032014 MBB->addSuccessor(UpdateMBB);
20042015 MBB->addSuccessor(UseAltMBB);
20052016
20292040 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
20302041 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
20312042 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2032 BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
2043 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2044 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
20332045 MBB->addSuccessor(LoopMBB);
20342046 MBB->addSuccessor(DoneMBB);
20352047
20452057 const SystemZInstrInfo *TII = TM.getInstrInfo();
20462058 MachineFunction &MF = *MBB->getParent();
20472059 MachineRegisterInfo &MRI = MF.getRegInfo();
2048 unsigned MaskNE = CCMaskForCondCode(ISD::SETNE);
20492060
20502061 // Extract the operands. Base can be a register or a frame index.
20512062 unsigned Dest = MI->getOperand(0).getReg();
21212132 BuildMI(MBB, DL, TII->get(SystemZ::CR))
21222133 .addReg(Dest).addReg(RetryCmpVal);
21232134 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2124 .addImm(MaskNE).addMBB(DoneMBB);
2135 .addImm(SystemZ::CCMASK_ICMP)
2136 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
21252137 MBB->addSuccessor(DoneMBB);
21262138 MBB->addSuccessor(SetMBB);
21272139
21412153 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
21422154 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
21432155 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2144 BuildMI(MBB, DL, TII->get(SystemZ::BRC)).addImm(MaskNE).addMBB(LoopMBB);
2156 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2157 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
21452158 MBB->addSuccessor(LoopMBB);
21462159 MBB->addSuccessor(DoneMBB);
21472160
683683 // is added as an implicit use.
684684 class CondUnaryRRF opcode, RegisterOperand cls1,
685685 RegisterOperand cls2>
686 : InstRRFR3),
686 : InstRRFvalid, cond4:$R3),
687687 mnemonic#"r$R3\t$R1, $R2", []>,
688688 Requires<[FeatureLoadStoreOnCond]>;
689689
12551255 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
12561256 // the value of the PSW's 2-bit condition code field.
12571257 class SelectWrapper
1258 : Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
1259 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
1258 : Pseudo<(outs cls:$dst),
1259 (ins cls:$src1, cls:$src2, uimm8zx4:$valid, uimm8zx4:$cc),
1260 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
1261 uimm8zx4:$valid, uimm8zx4:$cc))]> {
12601262 let usesCustomInserter = 1;
12611263 // Although the instructions used by these nodes do not in themselves
12621264 // change CC, the insertion requires new blocks, and CC cannot be live
12691271 multiclass CondStores
12701272 SDPatternOperator load, AddressingMode mode> {
12711273 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
1272 def "" : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
1274 def "" : Pseudo<(outs),
1275 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
12731276 [(store (z_select_ccmask cls:$new, (load mode:$addr),
1274 uimm8zx4:$cc), mode:$addr)]>;
1275 def Inv : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
1277 uimm8zx4:$valid, uimm8zx4:$cc),
1278 mode:$addr)]>;
1279 def Inv : Pseudo<(outs),
1280 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
12761281 [(store (z_select_ccmask (load mode:$addr), cls:$new,
1277 uimm8zx4:$cc), mode:$addr)]>;
1282 uimm8zx4:$valid, uimm8zx4:$cc),
1283 mode:$addr)]>;
12781284 }
12791285 }
12801286
200200 // FIXME: add X86-style branch swap
201201 FBB = TBB;
202202 TBB = Branch.Target->getMBB();
203 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
203204 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
204205 continue;
205206 }
206207
207208 // Handle subsequent conditional branches.
208 assert(Cond.size() == 1);
209 assert(TBB);
209 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
210210
211211 // Only handle the case where all conditional branches branch to the same
212212 // destination.
214214 return true;
215215
216216 // If the conditions are the same, we can leave them alone.
217 unsigned OldCond = Cond[0].getImm();
218 if (OldCond == Branch.CCMask)
217 unsigned OldCCValid = Cond[0].getImm();
218 unsigned OldCCMask = Cond[1].getImm();
219 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
219220 continue;
220221
221222 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
223 return false;
222224 }
223225
224226 return false;
246248 return Count;
247249 }
248250
251 bool SystemZInstrInfo::
252 ReverseBranchCondition(SmallVectorImpl &Cond) const {
253 assert(Cond.size() == 2 && "Invalid condition");
254 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
255 return false;
256 }
257
249258 unsigned
250259 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
251260 MachineBasicBlock *FBB,
257266
258267 // Shouldn't be a fall through.
259268 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
260 assert((Cond.size() == 1 || Cond.size() == 0) &&
269 assert((Cond.size() == 2 || Cond.size() == 0) &&
261270 "SystemZ branch conditions have one component!");
262271
263272 if (Cond.empty()) {
269278
270279 // Conditional branch.
271280 unsigned Count = 0;
272 unsigned CC = Cond[0].getImm();
273 BuildMI(&MBB, DL, get(SystemZ::BRC)).addImm(CC).addMBB(TBB);
281 unsigned CCValid = Cond[0].getImm();
282 unsigned CCMask = Cond[1].getImm();
283 BuildMI(&MBB, DL, get(SystemZ::BRC))
284 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
274285 ++Count;
275286
276287 if (FBB) {
320331 bool SystemZInstrInfo::
321332 PredicateInstruction(MachineInstr *MI,
322333 const SmallVectorImpl &Pred) const {
323 unsigned CCMask = Pred[0].getImm();
334 assert(Pred.size() == 2 && "Invalid condition");
335 unsigned CCValid = Pred[0].getImm();
336 unsigned CCMask = Pred[1].getImm();
324337 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
325338 unsigned Opcode = MI->getOpcode();
326339 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
327340 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
328341 MI->setDesc(get(CondOpcode));
329 MachineInstrBuilder(*MI->getParent()->getParent(), MI).addImm(CCMask);
342 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
343 .addImm(CCValid).addImm(CCMask);
330344 return true;
331345 }
332346 }
644658 }
645659 }
646660
647 bool SystemZInstrInfo::
648 ReverseBranchCondition(SmallVectorImpl &Cond) const {
649 assert(Cond.size() == 1 && "Invalid branch condition!");
650 Cond[0].setImm(Cond[0].getImm() ^ SystemZ::CCMASK_ANY);
651 return false;
652 }
653
654661 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
655662 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
656663 const MachineFunction *MF = MI->getParent()->getParent();
667674 case SystemZ::J:
668675 case SystemZ::JG:
669676 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
670 &MI->getOperand(0));
677 SystemZ::CCMASK_ANY, &MI->getOperand(0));
671678
672679 case SystemZ::BRC:
673680 case SystemZ::BRCL:
674681 return SystemZII::Branch(SystemZII::BranchNormal,
675 MI->getOperand(0).getImm(), &MI->getOperand(1));
682 MI->getOperand(0).getImm(),
683 MI->getOperand(1).getImm(), &MI->getOperand(2));
676684
677685 case SystemZ::CIJ:
678686 case SystemZ::CRJ:
679 return SystemZII::Branch(SystemZII::BranchC, MI->getOperand(2).getImm(),
680 &MI->getOperand(3));
687 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
688 MI->getOperand(2).getImm(), &MI->getOperand(3));
681689
682690 case SystemZ::CGIJ:
683691 case SystemZ::CGRJ:
684 return SystemZII::Branch(SystemZII::BranchCG, MI->getOperand(2).getImm(),
685 &MI->getOperand(3));
692 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
693 MI->getOperand(2).getImm(), &MI->getOperand(3));
686694
687695 default:
688696 llvm_unreachable("Unrecognized branch opcode");
6565 // The type of the branch.
6666 BranchType Type;
6767
68 // CCMASK_ is set if CC might be equal to N.
69 unsigned CCValid;
70
6871 // CCMASK_ is set if the branch should be taken when CC == N.
6972 unsigned CCMask;
7073
7174 // The target of the branch.
7275 const MachineOperand *Target;
7376
74 Branch(BranchType type, unsigned ccMask, const MachineOperand *target)
75 : Type(type), CCMask(ccMask), Target(target) {}
77 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
78 const MachineOperand *target)
79 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
7680 };
7781 }
7882
5757 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
5858 // the first operand. It seems friendlier to use mnemonic forms like
5959 // JE and JLH when writing out the assembly though.
60 multiclass CondBranches {
61 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
62 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>;
63 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>;
64 }
65 }
66 let isCodeGenOnly = 1 in
67 defm BRC : CondBranches;
68 defm AsmBRC : CondBranches;
69
70 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>;
60 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
61 let isCodeGenOnly = 1 in {
62 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
63 brtarget16:$I2), "j$R1\t$I2",
64 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
65 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
66 brtarget32:$I2), "jg$R1\t$I2", []>;
67 }
68 def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
69 "brc\t$R1, $I2", []>;
70 def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
71 "brcl\t$R1, $I2", []>;
72 }
7173
7274 // Fused compare-and-branch instructions. As for normal branches,
7375 // we handle these instructions internally in their raw CRJ-like form,
11351137
11361138 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
11371139 // for vector legalization.
1138 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm:$cc)), (i32 31)), (i32 31)),
1139 (Select32 (LHI -1), (LHI 0), imm:$cc)>;
1140 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm:$cc)))),
1140 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1141 (i32 31)),
1142 (i32 31)),
1143 (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1144 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1145 uimm8zx4:$cc)))),
11411146 (i32 63)),
11421147 (i32 63)),
1143 (Select64 (LGHI -1), (LGHI 0), imm:$cc)>;
1148 (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
296296 for (++MBBI; MBBI != MBBE; ++MBBI) {
297297 if (MBBI->getOpcode() == SystemZ::BRC && !isCCLiveAfter(MBBI, TRI)) {
298298 // Read the branch mask and target.
299 MachineOperand CCMask(MBBI->getOperand(0));
300 MachineOperand Target(MBBI->getOperand(1));
299 MachineOperand CCMask(MBBI->getOperand(1));
300 MachineOperand Target(MBBI->getOperand(2));
301 assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
302 "Invalid condition-code mask for integer comparison");
301303
302304 // Clear out all current operands.
303305 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
304306 assert(CCUse >= 0 && "BRC must use CC");
305307 MBBI->RemoveOperand(CCUse);
308 MBBI->RemoveOperand(2);
306309 MBBI->RemoveOperand(1);
307310 MBBI->RemoveOperand(0);
308311
440443 .addOperand(MI->getOperand(0))
441444 .addOperand(MI->getOperand(1));
442445 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
446 .addImm(SystemZ::CCMASK_ICMP)
443447 .addOperand(MI->getOperand(2))
444448 .addOperand(MI->getOperand(3));
445449 // The implicit use of CC is a killing use.
446 BRCL->getOperand(2).setIsKill();
450 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo());
447451 MI->eraseFromParent();
448452 }
449453
1414 SDTCisVT<1, i64>]>;
1515 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
1616 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
17 def SDT_ZBRCCMask : SDTypeProfile<0, 2,
17 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
1818 [SDTCisVT<0, i8>,
19 SDTCisVT<1, OtherVT>]>;
20 def SDT_ZSelectCCMask : SDTypeProfile<1, 3,
19 SDTCisVT<1, i8>,
20 SDTCisVT<2, OtherVT>]>;
21 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
2122 [SDTCisSameAs<0, 1>,
2223 SDTCisSameAs<1, 2>,
23 SDTCisVT<3, i8>]>;
24 SDTCisVT<3, i8>,
25 SDTCisVT<4, i8>]>;
2426 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
2527 [SDTCisSameAs<0, 1>,
2628 SDTCisPtrTy<0>]>;
5757 // register of class CLS. The load may trap even if the condition is false.
5858 multiclass CondLoad
5959 SDPatternOperator load> {
60 def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc),
60 def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4,
61 uimm8zx4:$cc),
6162 (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
6263 Requires<[FeatureLoadStoreOnCond]>;
63 def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc),
64 def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4,
65 uimm8zx4:$cc),
6466 (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
6567 Requires<[FeatureLoadStoreOnCond]>;
6668 }
88 ; CHECK: l %r0, 0(%r3)
99 ; CHECK: [[LABEL:\.[^:]*]]:
1010 ; CHECK: cs %r0, %r2, 0(%r3)
11 ; CHECK: jlh [[LABEL]]
11 ; CHECK: jl [[LABEL]]
1212 ; CHECK: br %r14
1313 store atomic i32 %val, i32 *%src seq_cst, align 4
1414 ret void
88 ; CHECK: lg %r0, 0(%r3)
99 ; CHECK: [[LABEL:\.[^:]*]]:
1010 ; CHECK: csg %r0, %r2, 0(%r3)
11 ; CHECK: jlh [[LABEL]]
11 ; CHECK: jl [[LABEL]]
1212 ; CHECK: br %r14
1313 store atomic i64 %val, i64 *%src seq_cst, align 8
1414 ret void
2121 ; CHECK: ar [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
2121 ; CHECK: ar [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
99 ; CHECK: lr %r0, %r2
1010 ; CHECK: ar %r0, %r4
1111 ; CHECK: cs %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw add i32 *%src, i32 %b seq_cst
1515 ret i32 %res
2323 ; CHECK: lr %r0, %r2
2424 ; CHECK: ahi %r0, 1
2525 ; CHECK: cs %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw add i32 *%src, i32 1 seq_cst
2929 ret i32 %res
99 ; CHECK: lgr %r0, %r2
1010 ; CHECK: agr %r0, %r4
1111 ; CHECK: csg %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw add i64 *%src, i64 %b seq_cst
1515 ret i64 %res
2323 ; CHECK: lgr %r0, %r2
2424 ; CHECK: aghi %r0, 1
2525 ; CHECK: csg %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw add i64 *%src, i64 1 seq_cst
2929 ret i64 %res
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5656 ; CHECK: nilh [[ROT]], 33023
5757 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5858 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
59 ; CHECK: jlh [[LABEL]]
59 ; CHECK: jl [[LABEL]]
6060 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6161 ; CHECK: br %r14
6262 ;
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5656 ; CHECK: nilh [[ROT]], 32768
5757 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5858 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
59 ; CHECK: jlh [[LABEL]]
59 ; CHECK: jl [[LABEL]]
6060 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6161 ; CHECK: br %r14
6262 ;
99 ; CHECK: lr %r0, %r2
1010 ; CHECK: nr %r0, %r4
1111 ; CHECK: cs %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw and i32 *%src, i32 %b seq_cst
1515 ret i32 %res
2323 ; CHECK: lr %r0, %r2
2424 ; CHECK: nilf %r0, 1
2525 ; CHECK: cs %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw and i32 *%src, i32 1 seq_cst
2929 ret i32 %res
99 ; CHECK: lgr %r0, %r2
1010 ; CHECK: ngr %r0, %r4
1111 ; CHECK: csg %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw and i64 *%src, i64 %b seq_cst
1515 ret i64 %res
3232 ; CHECK: [[LABEL:\.[^:]*]]:
3333 ; CHECK: risbg %r0, %r2, 31, 191, 0
3434 ; CHECK: csg %r2, %r0, 0(%r3)
35 ; CHECK: jlh [[LABEL]]
35 ; CHECK: jl [[LABEL]]
3636 ; CHECK: br %r14
3737 %res = atomicrmw and i64 *%src, i64 8589934591 seq_cst
3838 ret i64 %res
4646 ; CHECK: lgr %r0, %r2
4747 ; CHECK: nihf %r0, 2
4848 ; CHECK: csg %r2, %r0, 0(%r3)
49 ; CHECK: jlh [[LABEL]]
49 ; CHECK: jl [[LABEL]]
5050 ; CHECK: br %r14
5151 %res = atomicrmw and i64 *%src, i64 12884901887 seq_cst
5252 ret i64 %res
2323 ; CHECK: [[KEEP]]:
2424 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2525 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
26 ; CHECK: jlh [[LOOP]]
26 ; CHECK: jl [[LOOP]]
2727 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2828 ; CHECK: br %r14
2929 ;
5959 ; CHECK: [[KEEP]]:
6060 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
6161 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
62 ; CHECK: jlh [[LOOP]]
62 ; CHECK: jl [[LOOP]]
6363 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6464 ; CHECK: br %r14
6565 ;
9696 ; CHECK: [[KEEP]]:
9797 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
9898 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
99 ; CHECK: jlh [[LOOP]]
99 ; CHECK: jl [[LOOP]]
100100 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
101101 ; CHECK: br %r14
102102 ;
133133 ; CHECK: [[KEEP]]:
134134 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
135135 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
136 ; CHECK: jlh [[LOOP]]
136 ; CHECK: jl [[LOOP]]
137137 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
138138 ; CHECK: br %r14
139139 ;
2323 ; CHECK: [[KEEP]]:
2424 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2525 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
26 ; CHECK: jlh [[LOOP]]
26 ; CHECK: jl [[LOOP]]
2727 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2828 ; CHECK: br %r14
2929 ;
5959 ; CHECK: [[KEEP]]:
6060 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
6161 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
62 ; CHECK: jlh [[LOOP]]
62 ; CHECK: jl [[LOOP]]
6363 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6464 ; CHECK: br %r14
6565 ;
9696 ; CHECK: [[KEEP]]:
9797 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
9898 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
99 ; CHECK: jlh [[LOOP]]
99 ; CHECK: jl [[LOOP]]
100100 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
101101 ; CHECK: br %r14
102102 ;
133133 ; CHECK: [[KEEP]]:
134134 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
135135 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
136 ; CHECK: jlh [[LOOP]]
136 ; CHECK: jl [[LOOP]]
137137 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
138138 ; CHECK: br %r14
139139 ;
1010 ; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
1111 ; CHECK: lr [[NEW]], %r4
1212 ; CHECK: cs %r2, [[NEW]], 0(%r3)
13 ; CHECK: jlh [[LOOP]]
13 ; CHECK: jl [[LOOP]]
1414 ; CHECK: br %r14
1515 %res = atomicrmw min i32 *%src, i32 %b seq_cst
1616 ret i32 %res
2525 ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
2626 ; CHECK: lr [[NEW]], %r4
2727 ; CHECK: cs %r2, [[NEW]], 0(%r3)
28 ; CHECK: jlh [[LOOP]]
28 ; CHECK: jl [[LOOP]]
2929 ; CHECK: br %r14
3030 %res = atomicrmw max i32 *%src, i32 %b seq_cst
3131 ret i32 %res
4141 ; CHECK: jle [[KEEP:\..*]]
4242 ; CHECK: lr [[NEW]], %r4
4343 ; CHECK: cs %r2, [[NEW]], 0(%r3)
44 ; CHECK: jlh [[LOOP]]
44 ; CHECK: jl [[LOOP]]
4545 ; CHECK: br %r14
4646 %res = atomicrmw umin i32 *%src, i32 %b seq_cst
4747 ret i32 %res
5757 ; CHECK: jhe [[KEEP:\..*]]
5858 ; CHECK: lr [[NEW]], %r4
5959 ; CHECK: cs %r2, [[NEW]], 0(%r3)
60 ; CHECK: jlh [[LOOP]]
60 ; CHECK: jl [[LOOP]]
6161 ; CHECK: br %r14
6262 %res = atomicrmw umax i32 *%src, i32 %b seq_cst
6363 ret i32 %res
165165 ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
166166 ; CHECK: lhi [[NEW]], 42
167167 ; CHECK: cs %r2, [[NEW]], 0(%r3)
168 ; CHECK: jlh [[LOOP]]
168 ; CHECK: jl [[LOOP]]
169169 ; CHECK: br %r14
170170 %res = atomicrmw min i32 *%ptr, i32 42 seq_cst
171171 ret i32 %res
1010 ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]]
1111 ; CHECK: lgr [[NEW]], %r4
1212 ; CHECK: csg %r2, [[NEW]], 0(%r3)
13 ; CHECK: jlh [[LOOP]]
13 ; CHECK: jl [[LOOP]]
1414 ; CHECK: br %r14
1515 %res = atomicrmw min i64 *%src, i64 %b seq_cst
1616 ret i64 %res
2525 ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]]
2626 ; CHECK: lgr [[NEW]], %r4
2727 ; CHECK: csg %r2, [[NEW]], 0(%r3)
28 ; CHECK: jlh [[LOOP]]
28 ; CHECK: jl [[LOOP]]
2929 ; CHECK: br %r14
3030 %res = atomicrmw max i64 *%src, i64 %b seq_cst
3131 ret i64 %res
4141 ; CHECK: jle [[KEEP:\..*]]
4242 ; CHECK: lgr [[NEW]], %r4
4343 ; CHECK: csg %r2, [[NEW]], 0(%r3)
44 ; CHECK: jlh [[LOOP]]
44 ; CHECK: jl [[LOOP]]
4545 ; CHECK: br %r14
4646 %res = atomicrmw umin i64 *%src, i64 %b seq_cst
4747 ret i64 %res
5757 ; CHECK: jhe [[KEEP:\..*]]
5858 ; CHECK: lgr [[NEW]], %r4
5959 ; CHECK: csg %r2, [[NEW]], 0(%r3)
60 ; CHECK: jlh [[LOOP]]
60 ; CHECK: jl [[LOOP]]
6161 ; CHECK: br %r14
6262 %res = atomicrmw umax i64 *%src, i64 %b seq_cst
6363 ret i64 %res
132132 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
133133 ; CHECK: lghi [[NEW]], 42
134134 ; CHECK: csg %r2, [[NEW]], 0(%r3)
135 ; CHECK: jlh [[LOOP]]
135 ; CHECK: jl [[LOOP]]
136136 ; CHECK: br %r14
137137 %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
138138 ret i64 %res
2222 ; CHECK: xilf [[ROT]], 4278190080
2323 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2424 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
25 ; CHECK: jlh [[LABEL]]
25 ; CHECK: jl [[LABEL]]
2626 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2727 ; CHECK: br %r14
2828 ;
5858 ; CHECK: xilf [[ROT]], 4278190080
5959 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
6060 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
61 ; CHECK: jlh [[LABEL]]
61 ; CHECK: jl [[LABEL]]
6262 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6363 ; CHECK: br %r14
6464 ;
2222 ; CHECK: xilf [[ROT]], 4294901760
2323 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2424 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
25 ; CHECK: jlh [[LABEL]]
25 ; CHECK: jl [[LABEL]]
2626 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2727 ; CHECK: br %r14
2828 ;
5858 ; CHECK: xilf [[ROT]], 4294901760
5959 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
6060 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
61 ; CHECK: jlh [[LABEL]]
61 ; CHECK: jl [[LABEL]]
6262 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6363 ; CHECK: br %r14
6464 ;
1010 ; CHECK: nr %r0, %r4
1111 ; CHECK: xilf %r0, 4294967295
1212 ; CHECK: cs %r2, %r0, 0(%r3)
13 ; CHECK: jlh [[LABEL]]
13 ; CHECK: jl [[LABEL]]
1414 ; CHECK: br %r14
1515 %res = atomicrmw nand i32 *%src, i32 %b seq_cst
1616 ret i32 %res
2525 ; CHECK: nilf %r0, 1
2626 ; CHECK: xilf %r0, 4294967295
2727 ; CHECK: cs %r2, %r0, 0(%r3)
28 ; CHECK: jlh [[LABEL]]
28 ; CHECK: jl [[LABEL]]
2929 ; CHECK: br %r14
3030 %res = atomicrmw nand i32 *%src, i32 1 seq_cst
3131 ret i32 %res
1111 ; CHECK: lcgr %r0, %r0
1212 ; CHECK: aghi %r0, -1
1313 ; CHECK: csg %r2, %r0, 0(%r3)
14 ; CHECK: jlh [[LABEL]]
14 ; CHECK: jl [[LABEL]]
1515 ; CHECK: br %r14
1616 %res = atomicrmw nand i64 *%src, i64 %b seq_cst
1717 ret i64 %res
3636 ; CHECK: lcgr %r0, %r0
3737 ; CHECK: aghi %r0, -1
3838 ; CHECK: csg %r2, %r0, 0(%r3)
39 ; CHECK: jlh [[LABEL]]
39 ; CHECK: jl [[LABEL]]
4040 ; CHECK: br %r14
4141 %res = atomicrmw nand i64 *%src, i64 8589934591 seq_cst
4242 ret i64 %res
5252 ; CHECK: lcgr %r0, %r0
5353 ; CHECK: aghi %r0, -1
5454 ; CHECK: csg %r2, %r0, 0(%r3)
55 ; CHECK: jlh [[LABEL]]
55 ; CHECK: jl [[LABEL]]
5656 ; CHECK: br %r14
5757 %res = atomicrmw nand i64 *%src, i64 12884901887 seq_cst
5858 ret i64 %res
2121 ; CHECK: or [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: oilh [[ROT]], 32768
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
2121 ; CHECK: or [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: oilh [[ROT]], 32768
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
99 ; CHECK: lr %r0, %r2
1010 ; CHECK: or %r0, %r4
1111 ; CHECK: cs %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw or i32 *%src, i32 %b seq_cst
1515 ret i32 %res
2323 ; CHECK: lr %r0, %r2
2424 ; CHECK: oill %r0, 1
2525 ; CHECK: cs %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw or i32 *%src, i32 1 seq_cst
2929 ret i32 %res
99 ; CHECK: lgr %r0, %r2
1010 ; CHECK: ogr %r0, %r4
1111 ; CHECK: csg %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw or i64 *%src, i64 %b seq_cst
1515 ret i64 %res
2323 ; CHECK: lgr %r0, %r2
2424 ; CHECK: oill %r0, 1
2525 ; CHECK: csg %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw or i64 *%src, i64 1 seq_cst
2929 ret i64 %res
2121 ; CHECK: sr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
2121 ; CHECK: sr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
99 ; CHECK: lr %r0, %r2
1010 ; CHECK: sr %r0, %r4
1111 ; CHECK: cs %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw sub i32 *%src, i32 %b seq_cst
1515 ret i32 %res
2323 ; CHECK: lr %r0, %r2
2424 ; CHECK: ahi %r0, -1
2525 ; CHECK: cs %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw sub i32 *%src, i32 1 seq_cst
2929 ret i32 %res
99 ; CHECK: lgr %r0, %r2
1010 ; CHECK: sgr %r0, %r4
1111 ; CHECK: csg %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw sub i64 *%src, i64 %b seq_cst
1515 ret i64 %res
2323 ; CHECK: lgr %r0, %r2
2424 ; CHECK: aghi %r0, -1
2525 ; CHECK: csg %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw sub i64 *%src, i64 1 seq_cst
2929 ret i64 %res
1919 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
2020 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2121 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
22 ; CHECK: jlh [[LABEL]]
22 ; CHECK: jl [[LABEL]]
2323 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2424 ; CHECK: br %r14
2525 ;
1919 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
2020 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2121 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
22 ; CHECK: jlh [[LABEL]]
22 ; CHECK: jl [[LABEL]]
2323 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2424 ; CHECK: br %r14
2525 ;
77 ; CHECK: l %r2, 0(%r3)
88 ; CHECK: [[LABEL:\.[^:]*]]:
99 ; CHECK: cs %r2, %r4, 0(%r3)
10 ; CHECK: jlh [[LABEL]]
10 ; CHECK: jl [[LABEL]]
1111 ; CHECK: br %r14
1212 %res = atomicrmw xchg i32 *%src, i32 %b seq_cst
1313 ret i32 %res
113113 ; CHECK: l %r2, 0(%r3)
114114 ; CHECK: [[LABEL:\.[^:]*]]:
115115 ; CHECK: cs %r2, [[VALUE]], 0(%r3)
116 ; CHECK: jlh [[LABEL]]
116 ; CHECK: jl [[LABEL]]
117117 ; CHECK: br %r14
118118 %res = atomicrmw xchg i32 *%src, i32 40000 seq_cst
119119 ret i32 %res
77 ; CHECK: lg %r2, 0(%r3)
88 ; CHECK: [[LABEL:\.[^:]*]]:
99 ; CHECK: csg %r2, %r4, 0(%r3)
10 ; CHECK: jlh [[LABEL]]
10 ; CHECK: jl [[LABEL]]
1111 ; CHECK: br %r14
1212 %res = atomicrmw xchg i64 *%src, i64 %b seq_cst
1313 ret i64 %res
8080 ; CHECK: lg %r2, 0(%r3)
8181 ; CHECK: [[LABEL:\.[^:]*]]:
8282 ; CHECK: csg %r2, [[VALUE]], 0(%r3)
83 ; CHECK: jlh [[LABEL]]
83 ; CHECK: jl [[LABEL]]
8484 ; CHECK: br %r14
8585 %res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst
8686 ret i64 %res
2121 ; CHECK: xr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: xilf [[ROT]], 2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
2121 ; CHECK: xr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
2323 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: jlh [[LABEL]]
24 ; CHECK: jl [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
2727 ;
5555 ; CHECK: xilf [[ROT]], 2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
5757 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: jlh [[LABEL]]
58 ; CHECK: jl [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
6161 ;
99 ; CHECK: lr %r0, %r2
1010 ; CHECK: xr %r0, %r4
1111 ; CHECK: cs %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw xor i32 *%src, i32 %b seq_cst
1515 ret i32 %res
2323 ; CHECK: lr %r0, %r2
2424 ; CHECK: xilf %r0, 1
2525 ; CHECK: cs %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw xor i32 *%src, i32 1 seq_cst
2929 ret i32 %res
99 ; CHECK: lgr %r0, %r2
1010 ; CHECK: xgr %r0, %r4
1111 ; CHECK: csg %r2, %r0, 0(%r3)
12 ; CHECK: jlh [[LABEL]]
12 ; CHECK: jl [[LABEL]]
1313 ; CHECK: br %r14
1414 %res = atomicrmw xor i64 *%src, i64 %b seq_cst
1515 ret i64 %res
2323 ; CHECK: lgr %r0, %r2
2424 ; CHECK: xilf %r0, 1
2525 ; CHECK: csg %r2, %r0, 0(%r3)
26 ; CHECK: jlh [[LABEL]]
26 ; CHECK: jl [[LABEL]]
2727 ; CHECK: br %r14
2828 %res = atomicrmw xor i64 *%src, i64 1 seq_cst
2929 ret i64 %res
88 define i32 @f1(i32 %a, i32 %b) {
99 ; CHECK-LABEL: f1:
1010 ; CHECK: clr %r2, %r3
11 ; CHECK: jnhe .L[[LABEL:.*]]
11 ; CHECK: jl .L[[LABEL:.*]]
1212 ; CHECK: br %r14
1313 ; CHECK: .L[[LABEL]]:
1414 ; CHECK: brasl %r14, foo@PLT
2727 ; Same again with a fused compare and branch.
2828 define i32 @f2(i32 %a) {
2929 ; CHECK-LABEL: f2:
30 ; CHECK: cijnlh %r2, 0, .L[[LABEL:.*]]
30 ; CHECK: cije %r2, 0, .L[[LABEL:.*]]
3131 ; CHECK: br %r14
3232 ; CHECK: .L[[LABEL]]:
3333 ; CHECK: brasl %r14, foo@PLT
2121 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
2222 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
2323 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
24 ; CHECK-MAIN: jlh [[LOOP]]
24 ; CHECK-MAIN: jl [[LOOP]]
2525 ; CHECK-MAIN: [[EXIT]]:
2626 ; CHECK-MAIN-NOT: %r2
2727 ; CHECK-MAIN: br %r14
2121 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
2222 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
2323 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
24 ; CHECK-MAIN: jlh [[LOOP]]
24 ; CHECK-MAIN: jl [[LOOP]]
2525 ; CHECK-MAIN: [[EXIT]]:
2626 ; CHECK-MAIN-NOT: %r2
2727 ; CHECK-MAIN: br %r14
55 define i32 @f1(i32 %a, i32 %b, i32 %limit) {
66 ; CHECK-LABEL: f1:
77 ; CHECK: clfi %r4, 42
8 ; CHECK: locrnl %r2, %r3
8 ; CHECK: locrhe %r2, %r3
99 ; CHECK: br %r14
1010 %cond = icmp ult i32 %limit, 42
1111 %res = select i1 %cond, i32 %a, i32 %b
1616 define i64 @f2(i64 %a, i64 %b, i64 %limit) {
1717 ; CHECK-LABEL: f2:
1818 ; CHECK: clgfi %r4, 42
19 ; CHECK: locgrnl %r2, %r3
19 ; CHECK: locgrhe %r2, %r3
2020 ; CHECK: br %r14
2121 %cond = icmp ult i64 %limit, 42
2222 %res = select i1 %cond, i64 %a, i64 %b
2323 ret i64 %res
2424 }
25
26 ; Test LOCR in a case that could use COMPARE AND BRANCH. We prefer using
27 ; LOCR if possible.
28 define i32 @f3(i32 %a, i32 %b, i32 %limit) {
29 ; CHECK-LABEL: f3:
30 ; CHECK: chi %r4, 42
31 ; CHECK: locrlh %r2, %r3
32 ; CHECK: br %r14
33 %cond = icmp eq i32 %limit, 42
34 %res = select i1 %cond, i32 %a, i32 %b
35 ret i32 %res
36 }
37
38 ; ...and again for LOCGR.
39 define i64 @f4(i64 %a, i64 %b, i64 %limit) {
40 ; CHECK-LABEL: f4:
41 ; CHECK: cghi %r4, 42
42 ; CHECK: locgrlh %r2, %r3
43 ; CHECK: br %r14
44 %cond = icmp eq i64 %limit, 42
45 %res = select i1 %cond, i64 %a, i64 %b
46 ret i64 %res
47 }
2323 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: stc %r3, 0(%r2)
2929 ; CHECK: [[LABEL]]:
5858 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
5959 ; CHECK-LABEL: f4:
6060 ; CHECK-NOT: %r2
61 ; CHECK: jnl [[LABEL:[^ ]*]]
61 ; CHECK: jhe [[LABEL:[^ ]*]]
6262 ; CHECK-NOT: %r2
6363 ; CHECK: stc %r3, 0(%r2)
6464 ; CHECK: [[LABEL]]:
9595 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
9696 ; CHECK-LABEL: f6:
9797 ; CHECK-NOT: %r2
98 ; CHECK: jnl [[LABEL:[^ ]*]]
98 ; CHECK: jhe [[LABEL:[^ ]*]]
9999 ; CHECK-NOT: %r2
100100 ; CHECK: stc %r3, 0(%r2)
101101 ; CHECK: [[LABEL]]:
132132 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
133133 ; CHECK-LABEL: f8:
134134 ; CHECK-NOT: %r2
135 ; CHECK: jnl [[LABEL:[^ ]*]]
135 ; CHECK: jhe [[LABEL:[^ ]*]]
136136 ; CHECK-NOT: %r2
137137 ; CHECK: stc %r3, 0(%r2)
138138 ; CHECK: [[LABEL]]:
169169 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
170170 ; CHECK-LABEL: f10:
171171 ; CHECK-NOT: %r2
172 ; CHECK: jnl [[LABEL:[^ ]*]]
172 ; CHECK: jhe [[LABEL:[^ ]*]]
173173 ; CHECK-NOT: %r2
174174 ; CHECK: stc %r3, 0(%r2)
175175 ; CHECK: [[LABEL]]:
326326 ; ...likewise stores. In this case we should have a conditional load into %r3.
327327 define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
328328 ; CHECK-LABEL: f19:
329 ; CHECK: jnl [[LABEL:[^ ]*]]
329 ; CHECK: jhe [[LABEL:[^ ]*]]
330330 ; CHECK: lb %r3, 0(%r2)
331331 ; CHECK: [[LABEL]]:
332332 ; CHECK: stc %r3, 0(%r2)
346346 ; FIXME: should use a normal load instead of CS.
347347 ; CHECK-LABEL: f20:
348348 ; CHECK: cs {{%r[0-9]+}},
349 ; CHECK: jl
349350 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
350351 ; CHECK: [[LABEL]]:
351352 ; CHECK: stc {{%r[0-9]+}},
361362 define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
362363 ; FIXME: should use a normal store instead of CS.
363364 ; CHECK-LABEL: f21:
364 ; CHECK: jnl [[LABEL:[^ ]*]]
365 ; CHECK: jhe [[LABEL:[^ ]*]]
365366 ; CHECK: lb %r3, 0(%r2)
366367 ; CHECK: [[LABEL]]:
367368 ; CHECK: cs {{%r[0-9]+}},
2323 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: sth %r3, 0(%r2)
2929 ; CHECK: [[LABEL]]:
5858 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
5959 ; CHECK-LABEL: f4:
6060 ; CHECK-NOT: %r2
61 ; CHECK: jnl [[LABEL:[^ ]*]]
61 ; CHECK: jhe [[LABEL:[^ ]*]]
6262 ; CHECK-NOT: %r2
6363 ; CHECK: sth %r3, 0(%r2)
6464 ; CHECK: [[LABEL]]:
9595 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
9696 ; CHECK-LABEL: f6:
9797 ; CHECK-NOT: %r2
98 ; CHECK: jnl [[LABEL:[^ ]*]]
98 ; CHECK: jhe [[LABEL:[^ ]*]]
9999 ; CHECK-NOT: %r2
100100 ; CHECK: sth %r3, 0(%r2)
101101 ; CHECK: [[LABEL]]:
132132 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
133133 ; CHECK-LABEL: f8:
134134 ; CHECK-NOT: %r2
135 ; CHECK: jnl [[LABEL:[^ ]*]]
135 ; CHECK: jhe [[LABEL:[^ ]*]]
136136 ; CHECK-NOT: %r2
137137 ; CHECK: sth %r3, 0(%r2)
138138 ; CHECK: [[LABEL]]:
169169 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
170170 ; CHECK-LABEL: f10:
171171 ; CHECK-NOT: %r2
172 ; CHECK: jnl [[LABEL:[^ ]*]]
172 ; CHECK: jhe [[LABEL:[^ ]*]]
173173 ; CHECK-NOT: %r2
174174 ; CHECK: sth %r3, 0(%r2)
175175 ; CHECK: [[LABEL]]:
326326 ; ...likewise stores. In this case we should have a conditional load into %r3.
327327 define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
328328 ; CHECK-LABEL: f19:
329 ; CHECK: jnl [[LABEL:[^ ]*]]
329 ; CHECK: jhe [[LABEL:[^ ]*]]
330330 ; CHECK: lh %r3, 0(%r2)
331331 ; CHECK: [[LABEL]]:
332332 ; CHECK: sth %r3, 0(%r2)
346346 ; FIXME: should use a normal load instead of CS.
347347 ; CHECK-LABEL: f20:
348348 ; CHECK: cs {{%r[0-9]+}},
349 ; CHECK: jl
349350 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
350351 ; CHECK: [[LABEL]]:
351352 ; CHECK: sth {{%r[0-9]+}},
361362 define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
362363 ; FIXME: should use a normal store instead of CS.
363364 ; CHECK-LABEL: f21:
364 ; CHECK: jnl [[LABEL:[^ ]*]]
365 ; CHECK: jhe [[LABEL:[^ ]*]]
365366 ; CHECK: lh %r3, 0(%r2)
366367 ; CHECK: [[LABEL]]:
367368 ; CHECK: cs {{%r[0-9]+}},
2323 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: st %r3, 0(%r2)
2929 ; CHECK: [[LABEL]]:
5858 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
5959 ; CHECK-LABEL: f4:
6060 ; CHECK-NOT: %r2
61 ; CHECK: jnl [[LABEL:[^ ]*]]
61 ; CHECK: jhe [[LABEL:[^ ]*]]
6262 ; CHECK-NOT: %r2
6363 ; CHECK: st %r3, 0(%r2)
6464 ; CHECK: [[LABEL]]:
9595 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
9696 ; CHECK-LABEL: f6:
9797 ; CHECK-NOT: %r2
98 ; CHECK: jnl [[LABEL:[^ ]*]]
98 ; CHECK: jhe [[LABEL:[^ ]*]]
9999 ; CHECK-NOT: %r2
100100 ; CHECK: st %r3, 0(%r2)
101101 ; CHECK: [[LABEL]]:
252252 ; ...likewise stores. In this case we should have a conditional load into %r3.
253253 define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
254254 ; CHECK-LABEL: f15:
255 ; CHECK: jnl [[LABEL:[^ ]*]]
255 ; CHECK: jhe [[LABEL:[^ ]*]]
256256 ; CHECK: l %r3, 0(%r2)
257257 ; CHECK: [[LABEL]]:
258258 ; CHECK: st %r3, 0(%r2)
287287 define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
288288 ; FIXME: should use a normal store instead of CS.
289289 ; CHECK-LABEL: f17:
290 ; CHECK: jnl [[LABEL:[^ ]*]]
290 ; CHECK: jhe [[LABEL:[^ ]*]]
291291 ; CHECK: l %r3, 0(%r2)
292292 ; CHECK: [[LABEL]]:
293293 ; CHECK: cs {{%r[0-5]}}, %r3, 0(%r2)
2323 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: stg %r3, 0(%r2)
2929 ; CHECK: [[LABEL]]:
144144 ; ...likewise stores. In this case we should have a conditional load into %r3.
145145 define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
146146 ; CHECK-LABEL: f9:
147 ; CHECK: jnl [[LABEL:[^ ]*]]
147 ; CHECK: jhe [[LABEL:[^ ]*]]
148148 ; CHECK: lg %r3, 0(%r2)
149149 ; CHECK: [[LABEL]]:
150150 ; CHECK: stg %r3, 0(%r2)
179179 define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
180180 ; FIXME: should use a normal store instead of CSG.
181181 ; CHECK-LABEL: f11:
182 ; CHECK: jnl [[LABEL:[^ ]*]]
182 ; CHECK: jhe [[LABEL:[^ ]*]]
183183 ; CHECK: lg %r3, 0(%r2)
184184 ; CHECK: [[LABEL]]:
185185 ; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
2323 define void @f2(float *%ptr, float %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: ste %f0, 0(%r2)
2929 ; CHECK: [[LABEL]]:
178178 ; ...likewise stores. In this case we should have a conditional load into %f0.
179179 define void @f11(float *%ptr, float %alt, i32 %limit) {
180180 ; CHECK-LABEL: f11:
181 ; CHECK: jnl [[LABEL:[^ ]*]]
181 ; CHECK: jhe [[LABEL:[^ ]*]]
182182 ; CHECK: le %f0, 0(%r2)
183183 ; CHECK: [[LABEL]]:
184184 ; CHECK: ste %f0, 0(%r2)
2323 define void @f2(double *%ptr, double %alt, i32 %limit) {
2424 ; CHECK-LABEL: f2:
2525 ; CHECK-NOT: %r2
26 ; CHECK: jnl [[LABEL:[^ ]*]]
26 ; CHECK: jhe [[LABEL:[^ ]*]]
2727 ; CHECK-NOT: %r2
2828 ; CHECK: std %f0, 0(%r2)
2929 ; CHECK: [[LABEL]]:
178178 ; ...likewise stores. In this case we should have a conditional load into %f0.
179179 define void @f11(double *%ptr, double %alt, i32 %limit) {
180180 ; CHECK-LABEL: f11:
181 ; CHECK: jnl [[LABEL:[^ ]*]]
181 ; CHECK: jhe [[LABEL:[^ ]*]]
182182 ; CHECK: ld %f0, 0(%r2)
183183 ; CHECK: [[LABEL]]:
184184 ; CHECK: std %f0, 0(%r2)
77 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK: clfi %r4, 42
10 ; CHECK: stocnl %r3, 0(%r2)
10 ; CHECK: stoche %r3, 0(%r2)
1111 ; CHECK: br %r14
1212 %cond = icmp ult i32 %limit, 42
1313 %orig = load i32 *%ptr
3434 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
3535 ; CHECK-LABEL: f3:
3636 ; CHECK: clfi %r4, 42
37 ; CHECK: stocnl %r3, 0(%r2)
37 ; CHECK: stoche %r3, 0(%r2)
3838 ; CHECK: br %r14
3939 %cond = icmp ult i32 %limit, 42
4040 %orig = load i32 *%ptr
6565 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
6666 ; CHECK-LABEL: f5:
6767 ; CHECK: clfi %r4, 42
68 ; CHECK: stocnl %r3, 0(%r2)
68 ; CHECK: stoche %r3, 0(%r2)
6969 ; CHECK: br %r14
7070 %cond = icmp ult i32 %limit, 42
7171 %orig = load i32 *%ptr
9595 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
9696 ; CHECK-LABEL: f7:
9797 ; CHECK: clfi %r4, 42
98 ; CHECK: stocnl %r3, 524284(%r2)
98 ; CHECK: stoche %r3, 524284(%r2)
9999 ; CHECK: br %r14
100100 %ptr = getelementptr i32 *%base, i64 131071
101101 %cond = icmp ult i32 %limit, 42
110110 ; CHECK-LABEL: f8:
111111 ; CHECK: agfi %r2, 524288
112112 ; CHECK: clfi %r4, 42
113 ; CHECK: stocnl %r3, 0(%r2)
113 ; CHECK: stoche %r3, 0(%r2)
114114 ; CHECK: br %r14
115115 %ptr = getelementptr i32 *%base, i64 131072
116116 %cond = icmp ult i32 %limit, 42
124124 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
125125 ; CHECK-LABEL: f9:
126126 ; CHECK: clfi %r4, 42
127 ; CHECK: stocnl %r3, -524288(%r2)
127 ; CHECK: stoche %r3, -524288(%r2)
128128 ; CHECK: br %r14
129129 %ptr = getelementptr i32 *%base, i64 -131072
130130 %cond = icmp ult i32 %limit, 42
139139 ; CHECK-LABEL: f10:
140140 ; CHECK: agfi %r2, -524292
141141 ; CHECK: clfi %r4, 42
142 ; CHECK: stocnl %r3, 0(%r2)
142 ; CHECK: stoche %r3, 0(%r2)
143143 ; CHECK: br %r14
144144 %ptr = getelementptr i32 *%base, i64 -131073
145145 %cond = icmp ult i32 %limit, 42
153153 define void @f11(i32 %alt, i32 %limit) {
154154 ; CHECK-LABEL: f11:
155155 ; CHECK: brasl %r14, foo@PLT
156 ; CHECK: stocnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
156 ; CHECK: stoche {{%r[0-9]+}}, {{[0-9]+}}(%r15)
157157 ; CHECK: brasl %r14, foo@PLT
158158 ; CHECK: br %r14
159159 %ptr = alloca i32
77 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
88 ; CHECK-LABEL: f1:
99 ; CHECK: clfi %r4, 42
10 ; CHECK: stocgnl %r3, 0(%r2)
10 ; CHECK: stocghe %r3, 0(%r2)
1111 ; CHECK: br %r14
1212 %cond = icmp ult i32 %limit, 42
1313 %orig = load i64 *%ptr
3333 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
3434 ; CHECK-LABEL: f3:
3535 ; CHECK: clfi %r4, 42
36 ; CHECK: stocgnl %r3, 524280(%r2)
36 ; CHECK: stocghe %r3, 524280(%r2)
3737 ; CHECK: br %r14
3838 %ptr = getelementptr i64 *%base, i64 65535
3939 %cond = icmp ult i32 %limit, 42
4848 ; CHECK-LABEL: f4:
4949 ; CHECK: agfi %r2, 524288
5050 ; CHECK: clfi %r4, 42
51 ; CHECK: stocgnl %r3, 0(%r2)
51 ; CHECK: stocghe %r3, 0(%r2)
5252 ; CHECK: br %r14
5353 %ptr = getelementptr i64 *%base, i64 65536
5454 %cond = icmp ult i32 %limit, 42
6262 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
6363 ; CHECK-LABEL: f5:
6464 ; CHECK: clfi %r4, 42
65 ; CHECK: stocgnl %r3, -524288(%r2)
65 ; CHECK: stocghe %r3, -524288(%r2)
6666 ; CHECK: br %r14
6767 %ptr = getelementptr i64 *%base, i64 -65536
6868 %cond = icmp ult i32 %limit, 42
7777 ; CHECK-LABEL: f6:
7878 ; CHECK: agfi %r2, -524296
7979 ; CHECK: clfi %r4, 42
80 ; CHECK: stocgnl %r3, 0(%r2)
80 ; CHECK: stocghe %r3, 0(%r2)
8181 ; CHECK: br %r14
8282 %ptr = getelementptr i64 *%base, i64 -65537
8383 %cond = icmp ult i32 %limit, 42
9191 define void @f7(i64 %alt, i32 %limit) {
9292 ; CHECK-LABEL: f7:
9393 ; CHECK: brasl %r14, foo@PLT
94 ; CHECK: stocgnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
94 ; CHECK: stocghe {{%r[0-9]+}}, {{[0-9]+}}(%r15)
9595 ; CHECK: brasl %r14, foo@PLT
9696 ; CHECK: br %r14
9797 %ptr = alloca i64
165165 ; critical edge %entry->%while.body, which lost the kills information for CC.
166166 define void @f12(i32 %a, i32 %b) {
167167 ; CHECK-LABEL: f12:
168 ; CHECK: crje %r2,
168 ; CHECK: cije %r2, 0
169169 ; CHECK: crjlh %r2,
170170 ; CHECK: br %r14
171171 entry:
172 %cmp11 = icmp eq i32 %a, %b
172 %cmp11 = icmp eq i32 %a, 0
173173 br i1 %cmp11, label %while.end, label %while.body
174174
175175 while.body: