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Merging r203581: ------------------------------------------------------------------------ r203581 | hans | 2014-03-11 11:49:24 -0400 (Tue, 11 Mar 2014) | 7 lines X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059) This fixes the bug where we would bitcast the 64-bit floating point result of cmpneqsd to a 64-bit integer even on 32-bit targets. Differential Revision: http://llvm-reviews.chandlerc.com/D3009 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206071 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 48 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
1758217582 // FIXME: need symbolic constants for these magic numbers.
1758317583 // See X86ATTInstPrinter.cpp:printSSECC().
1758417584 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17585 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17585 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, CMP00.getValueType(),
17586 CMP00, CMP01,
1758617587 DAG.getConstant(x86cc, MVT::i8));
17587 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17588 OnesOrZeroesF);
17589 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17590 DAG.getConstant(1, MVT::i32));
17588
17589 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
17590
17591 if (is64BitFP && !Subtarget->is64Bit()) {
17592 // On a 32-bit target, we cannot bitcast the 64-bit float to a
17593 // 64-bit integer, since that's not a legal type. Since
17594 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
17595 // bits, but can do this little dance to extract the lowest 32 bits
17596 // and work with those going forward.
17597 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
17598 OnesOrZeroesF);
17599 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
17600 Vector64);
17601 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
17602 Vector32, DAG.getIntPtrConstant(0));
17603 IntVT = MVT::i32;
17604 }
17605
17606 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
17607 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17608 DAG.getConstant(1, IntVT));
1759117609 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
1759217610 return OneBitOfTruth;
1759317611 }
None ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
1 ; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s
2
3 ; PR19059
4 ; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck -check-prefix=CHECK32 %s
15
26 define i32 @isint_return(double %d) nounwind {
7 ; CHECK-LABEL: isint_return:
38 ; CHECK-NOT: xor
49 ; CHECK: cvt
510 %i = fptosi double %d to i32
712 %e = sitofp i32 %i to double
813 ; CHECK: cmpeqsd
914 %c = fcmp oeq double %d, %e
15 ; CHECK32-NOT: movd {{.*}}, %r{{.*}}
16 ; CHECK32-NOT: andq
17 ; CHECK-NEXT: movd
18 ; CHECK-NEXT: andl
19 %z = zext i1 %c to i32
20 ret i32 %z
21 }
22
23 define i32 @isint_float_return(float %f) nounwind {
24 ; CHECK-LABEL: isint_float_return:
25 ; CHECK-NOT: xor
26 ; CHECK: cvt
27 %i = fptosi float %f to i32
28 ; CHECK-NEXT: cvt
29 %g = sitofp i32 %i to float
30 ; CHECK: cmpeqss
31 %c = fcmp oeq float %f, %g
32 ; CHECK-NOT: movd {{.*}}, %r{{.*}}
1033 ; CHECK-NEXT: movd
1134 ; CHECK-NEXT: andl
1235 %z = zext i1 %c to i32
1639 declare void @foo()
1740
1841 define void @isint_branch(double %d) nounwind {
42 ; CHECK-LABEL: isint_branch:
1943 ; CHECK: cvt
2044 %i = fptosi double %d to i32
2145 ; CHECK-NEXT: cvt