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Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63505 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
2 changed file(s) with 44 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
53655365 Op.getOperand(1).hasOneUse());
53665366 }
53675367
5368 static bool isXor1OfSetCC(SDValue Op) {
5369 if (Op.getOpcode() != ISD::XOR)
5370 return false;
5371 ConstantSDNode *N1C = dyn_cast(Op.getOperand(1));
5372 if (N1C && N1C->getAPIntValue() == 1) {
5373 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5374 Op.getOperand(0).hasOneUse();
5375 }
5376 return false;
5377 }
5378
53685379 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
53695380 bool addTest = true;
53705381 SDValue Chain = Op.getOperand(0);
54595470 }
54605471 }
54615472 }
5473 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5474 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5475 // It should be transformed during dag combiner except when the condition
5476 // is set by a arithmetics with overflow node.
5477 X86::CondCode CCode =
5478 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5479 CCode = X86::GetOppositeBranchCondition(CCode);
5480 CC = DAG.getConstant(CCode, MVT::i8);
5481 Cond = Cond.getOperand(0).getOperand(1);
5482 addTest = false;
54625483 }
54635484 }
54645485
0 ; RUN: llvm-as < %s | llc -march=x86 | grep {jno} | count 1
1
2 @ok = internal constant [4 x i8] c"%d\0A\00"
3 @no = internal constant [4 x i8] c"no\0A\00"
4
5 define i1 @func1(i32 %v1, i32 %v2) nounwind {
6 entry:
7 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
8 %sum = extractvalue {i32, i1} %t, 0
9 %obit = extractvalue {i32, i1} %t, 1
10 br i1 %obit, label %overflow, label %normal
11
12 overflow:
13 %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
14 ret i1 false
15
16 normal:
17 %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
18 ret i1 true
19 }
20
21 declare i32 @printf(i8*, ...) nounwind
22 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)