llvm.org GIT mirror llvm / 67a6103
Convert more NEON tests to use FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
8 changed file(s) with 140 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vneg\\.s8} %t | count 2
2 ; RUN: grep {vneg\\.s16} %t | count 2
3 ; RUN: grep {vneg\\.s32} %t | count 2
4 ; RUN: grep {vneg\\.f32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
51
62 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
3 ;CHECK: vnegs8:
4 ;CHECK: vneg.s8
75 %tmp1 = load <8 x i8>* %A
86 %tmp2 = sub <8 x i8> zeroinitializer, %tmp1
97 ret <8 x i8> %tmp2
108 }
119
1210 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
11 ;CHECK: vnegs16:
12 ;CHECK: vneg.s16
1313 %tmp1 = load <4 x i16>* %A
1414 %tmp2 = sub <4 x i16> zeroinitializer, %tmp1
1515 ret <4 x i16> %tmp2
1616 }
1717
1818 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
19 ;CHECK: vnegs32:
20 ;CHECK: vneg.s32
1921 %tmp1 = load <2 x i32>* %A
2022 %tmp2 = sub <2 x i32> zeroinitializer, %tmp1
2123 ret <2 x i32> %tmp2
2224 }
2325
2426 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
27 ;CHECK: vnegf32:
28 ;CHECK: vneg.f32
2529 %tmp1 = load <2 x float>* %A
2630 %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
2731 ret <2 x float> %tmp2
2832 }
2933
3034 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
35 ;CHECK: vnegQs8:
36 ;CHECK: vneg.s8
3137 %tmp1 = load <16 x i8>* %A
3238 %tmp2 = sub <16 x i8> zeroinitializer, %tmp1
3339 ret <16 x i8> %tmp2
3440 }
3541
3642 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
43 ;CHECK: vnegQs16:
44 ;CHECK: vneg.s16
3745 %tmp1 = load <8 x i16>* %A
3846 %tmp2 = sub <8 x i16> zeroinitializer, %tmp1
3947 ret <8 x i16> %tmp2
4048 }
4149
4250 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
51 ;CHECK: vnegQs32:
52 ;CHECK: vneg.s32
4353 %tmp1 = load <4 x i32>* %A
4454 %tmp2 = sub <4 x i32> zeroinitializer, %tmp1
4555 ret <4 x i32> %tmp2
4656 }
4757
4858 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
59 ;CHECK: vnegQf32:
60 ;CHECK: vneg.f32
4961 %tmp1 = load <4 x float>* %A
5062 %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
5163 ret <4 x float> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep vorn %t | count 8
2 ; Note: function names do not include "vorn" to allow simple grep for opcodes
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
31
42 define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: v_orni8:
4 ;CHECK: vorn
55 %tmp1 = load <8 x i8>* %A
66 %tmp2 = load <8 x i8>* %B
77 %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
1010 }
1111
1212 define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13 ;CHECK: v_orni16:
14 ;CHECK: vorn
1315 %tmp1 = load <4 x i16>* %A
1416 %tmp2 = load <4 x i16>* %B
1517 %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
1820 }
1921
2022 define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
23 ;CHECK: v_orni32:
24 ;CHECK: vorn
2125 %tmp1 = load <2 x i32>* %A
2226 %tmp2 = load <2 x i32>* %B
2327 %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
2630 }
2731
2832 define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
33 ;CHECK: v_orni64:
34 ;CHECK: vorn
2935 %tmp1 = load <1 x i64>* %A
3036 %tmp2 = load <1 x i64>* %B
3137 %tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
3440 }
3541
3642 define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
43 ;CHECK: v_ornQi8:
44 ;CHECK: vorn
3745 %tmp1 = load <16 x i8>* %A
3846 %tmp2 = load <16 x i8>* %B
3947 %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
4250 }
4351
4452 define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
53 ;CHECK: v_ornQi16:
54 ;CHECK: vorn
4555 %tmp1 = load <8 x i16>* %A
4656 %tmp2 = load <8 x i16>* %B
4757 %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
5060 }
5161
5262 define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
63 ;CHECK: v_ornQi32:
64 ;CHECK: vorn
5365 %tmp1 = load <4 x i32>* %A
5466 %tmp2 = load <4 x i32>* %B
5567 %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
5870 }
5971
6072 define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
73 ;CHECK: v_ornQi64:
74 ;CHECK: vorn
6175 %tmp1 = load <2 x i64>* %A
6276 %tmp2 = load <2 x i64>* %B
6377 %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep vorr %t | count 8
2 ; Note: function names do not include "vorr" to allow simple grep for opcodes
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
31
42 define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: v_orri8:
4 ;CHECK: vorr
55 %tmp1 = load <8 x i8>* %A
66 %tmp2 = load <8 x i8>* %B
77 %tmp3 = or <8 x i8> %tmp1, %tmp2
99 }
1010
1111 define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: v_orri16:
13 ;CHECK: vorr
1214 %tmp1 = load <4 x i16>* %A
1315 %tmp2 = load <4 x i16>* %B
1416 %tmp3 = or <4 x i16> %tmp1, %tmp2
1618 }
1719
1820 define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: v_orri32:
22 ;CHECK: vorr
1923 %tmp1 = load <2 x i32>* %A
2024 %tmp2 = load <2 x i32>* %B
2125 %tmp3 = or <2 x i32> %tmp1, %tmp2
2327 }
2428
2529 define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
30 ;CHECK: v_orri64:
31 ;CHECK: vorr
2632 %tmp1 = load <1 x i64>* %A
2733 %tmp2 = load <1 x i64>* %B
2834 %tmp3 = or <1 x i64> %tmp1, %tmp2
3036 }
3137
3238 define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
39 ;CHECK: v_orrQi8:
40 ;CHECK: vorr
3341 %tmp1 = load <16 x i8>* %A
3442 %tmp2 = load <16 x i8>* %B
3543 %tmp3 = or <16 x i8> %tmp1, %tmp2
3745 }
3846
3947 define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
48 ;CHECK: v_orrQi16:
49 ;CHECK: vorr
4050 %tmp1 = load <8 x i16>* %A
4151 %tmp2 = load <8 x i16>* %B
4252 %tmp3 = or <8 x i16> %tmp1, %tmp2
4454 }
4555
4656 define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
57 ;CHECK: v_orrQi32:
58 ;CHECK: vorr
4759 %tmp1 = load <4 x i32>* %A
4860 %tmp2 = load <4 x i32>* %B
4961 %tmp3 = or <4 x i32> %tmp1, %tmp2
5163 }
5264
5365 define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
66 ;CHECK: v_orrQi64:
67 ;CHECK: vorr
5468 %tmp1 = load <2 x i64>* %A
5569 %tmp2 = load <2 x i64>* %B
5670 %tmp3 = or <2 x i64> %tmp1, %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vpadal\\.s8} %t | count 2
2 ; RUN: grep {vpadal\\.s16} %t | count 2
3 ; RUN: grep {vpadal\\.s32} %t | count 2
4 ; RUN: grep {vpadal\\.u8} %t | count 2
5 ; RUN: grep {vpadal\\.u16} %t | count 2
6 ; RUN: grep {vpadal\\.u32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
71
82 define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vpadals8:
4 ;CHECK: vpadal.s8
95 %tmp1 = load <4 x i16>* %A
106 %tmp2 = load <8 x i8>* %B
117 %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
139 }
1410
1511 define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vpadals16:
13 ;CHECK: vpadal.s16
1614 %tmp1 = load <2 x i32>* %A
1715 %tmp2 = load <4 x i16>* %B
1816 %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
2018 }
2119
2220 define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vpadals32:
22 ;CHECK: vpadal.s32
2323 %tmp1 = load <1 x i64>* %A
2424 %tmp2 = load <2 x i32>* %B
2525 %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
2727 }
2828
2929 define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
30 ;CHECK: vpadalu8:
31 ;CHECK: vpadal.u8
3032 %tmp1 = load <4 x i16>* %A
3133 %tmp2 = load <8 x i8>* %B
3234 %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
3436 }
3537
3638 define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
39 ;CHECK: vpadalu16:
40 ;CHECK: vpadal.u16
3741 %tmp1 = load <2 x i32>* %A
3842 %tmp2 = load <4 x i16>* %B
3943 %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
4145 }
4246
4347 define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
48 ;CHECK: vpadalu32:
49 ;CHECK: vpadal.u32
4450 %tmp1 = load <1 x i64>* %A
4551 %tmp2 = load <2 x i32>* %B
4652 %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
4854 }
4955
5056 define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
57 ;CHECK: vpadalQs8:
58 ;CHECK: vpadal.s8
5159 %tmp1 = load <8 x i16>* %A
5260 %tmp2 = load <16 x i8>* %B
5361 %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
5563 }
5664
5765 define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
66 ;CHECK: vpadalQs16:
67 ;CHECK: vpadal.s16
5868 %tmp1 = load <4 x i32>* %A
5969 %tmp2 = load <8 x i16>* %B
6070 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
6272 }
6373
6474 define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
75 ;CHECK: vpadalQs32:
76 ;CHECK: vpadal.s32
6577 %tmp1 = load <2 x i64>* %A
6678 %tmp2 = load <4 x i32>* %B
6779 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
6981 }
7082
7183 define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
84 ;CHECK: vpadalQu8:
85 ;CHECK: vpadal.u8
7286 %tmp1 = load <8 x i16>* %A
7387 %tmp2 = load <16 x i8>* %B
7488 %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
7690 }
7791
7892 define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
93 ;CHECK: vpadalQu16:
94 ;CHECK: vpadal.u16
7995 %tmp1 = load <4 x i32>* %A
8096 %tmp2 = load <8 x i16>* %B
8197 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
8399 }
84100
85101 define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
102 ;CHECK: vpadalQu32:
103 ;CHECK: vpadal.u32
86104 %tmp1 = load <2 x i64>* %A
87105 %tmp2 = load <4 x i32>* %B
88106 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vpadd\\.i8} %t | count 1
2 ; RUN: grep {vpadd\\.i16} %t | count 1
3 ; RUN: grep {vpadd\\.i32} %t | count 1
4 ; RUN: grep {vpadd\\.f32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
51
62 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vpaddi8:
4 ;CHECK: vpadd.i8
75 %tmp1 = load <8 x i8>* %A
86 %tmp2 = load <8 x i8>* %B
97 %tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
119 }
1210
1311 define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vpaddi16:
13 ;CHECK: vpadd.i16
1414 %tmp1 = load <4 x i16>* %A
1515 %tmp2 = load <4 x i16>* %B
1616 %tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
1818 }
1919
2020 define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vpaddi32:
22 ;CHECK: vpadd.i32
2123 %tmp1 = load <2 x i32>* %A
2224 %tmp2 = load <2 x i32>* %B
2325 %tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2527 }
2628
2729 define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
30 ;CHECK: vpaddf32:
31 ;CHECK: vpadd.f32
2832 %tmp1 = load <2 x float>* %A
2933 %tmp2 = load <2 x float>* %B
3034 %tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vpaddl\\.s8} %t | count 2
2 ; RUN: grep {vpaddl\\.s16} %t | count 2
3 ; RUN: grep {vpaddl\\.s32} %t | count 2
4 ; RUN: grep {vpaddl\\.u8} %t | count 2
5 ; RUN: grep {vpaddl\\.u16} %t | count 2
6 ; RUN: grep {vpaddl\\.u32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
71
82 define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
3 ;CHECK: vpaddls8:
4 ;CHECK: vpaddl.s8
95 %tmp1 = load <8 x i8>* %A
106 %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
117 ret <4 x i16> %tmp2
128 }
139
1410 define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
11 ;CHECK: vpaddls16:
12 ;CHECK: vpaddl.s16
1513 %tmp1 = load <4 x i16>* %A
1614 %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
1715 ret <2 x i32> %tmp2
1816 }
1917
2018 define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
19 ;CHECK: vpaddls32:
20 ;CHECK: vpaddl.s32
2121 %tmp1 = load <2 x i32>* %A
2222 %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
2323 ret <1 x i64> %tmp2
2424 }
2525
2626 define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
27 ;CHECK: vpaddlu8:
28 ;CHECK: vpaddl.u8
2729 %tmp1 = load <8 x i8>* %A
2830 %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
2931 ret <4 x i16> %tmp2
3032 }
3133
3234 define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
35 ;CHECK: vpaddlu16:
36 ;CHECK: vpaddl.u16
3337 %tmp1 = load <4 x i16>* %A
3438 %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
3539 ret <2 x i32> %tmp2
3640 }
3741
3842 define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
43 ;CHECK: vpaddlu32:
44 ;CHECK: vpaddl.u32
3945 %tmp1 = load <2 x i32>* %A
4046 %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
4147 ret <1 x i64> %tmp2
4248 }
4349
4450 define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
51 ;CHECK: vpaddlQs8:
52 ;CHECK: vpaddl.s8
4553 %tmp1 = load <16 x i8>* %A
4654 %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
4755 ret <8 x i16> %tmp2
4856 }
4957
5058 define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
59 ;CHECK: vpaddlQs16:
60 ;CHECK: vpaddl.s16
5161 %tmp1 = load <8 x i16>* %A
5262 %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
5363 ret <4 x i32> %tmp2
5464 }
5565
5666 define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
67 ;CHECK: vpaddlQs32:
68 ;CHECK: vpaddl.s32
5769 %tmp1 = load <4 x i32>* %A
5870 %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
5971 ret <2 x i64> %tmp2
6072 }
6173
6274 define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
75 ;CHECK: vpaddlQu8:
76 ;CHECK: vpaddl.u8
6377 %tmp1 = load <16 x i8>* %A
6478 %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
6579 ret <8 x i16> %tmp2
6680 }
6781
6882 define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
83 ;CHECK: vpaddlQu16:
84 ;CHECK: vpaddl.u16
6985 %tmp1 = load <8 x i16>* %A
7086 %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
7187 ret <4 x i32> %tmp2
7288 }
7389
7490 define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
91 ;CHECK: vpaddlQu32:
92 ;CHECK: vpaddl.u32
7593 %tmp1 = load <4 x i32>* %A
7694 %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
7795 ret <2 x i64> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vpmax\\.s8} %t | count 1
2 ; RUN: grep {vpmax\\.s16} %t | count 1
3 ; RUN: grep {vpmax\\.s32} %t | count 1
4 ; RUN: grep {vpmax\\.u8} %t | count 1
5 ; RUN: grep {vpmax\\.u16} %t | count 1
6 ; RUN: grep {vpmax\\.u32} %t | count 1
7 ; RUN: grep {vpmax\\.f32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
81
92 define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vpmaxs8:
4 ;CHECK: vpmax.s8
105 %tmp1 = load <8 x i8>* %A
116 %tmp2 = load <8 x i8>* %B
127 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
149 }
1510
1611 define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vpmaxs16:
13 ;CHECK: vpmax.s16
1714 %tmp1 = load <4 x i16>* %A
1815 %tmp2 = load <4 x i16>* %B
1916 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2118 }
2219
2320 define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vpmaxs32:
22 ;CHECK: vpmax.s32
2423 %tmp1 = load <2 x i32>* %A
2524 %tmp2 = load <2 x i32>* %B
2625 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2827 }
2928
3029 define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
30 ;CHECK: vpmaxu8:
31 ;CHECK: vpmax.u8
3132 %tmp1 = load <8 x i8>* %A
3233 %tmp2 = load <8 x i8>* %B
3334 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
3536 }
3637
3738 define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
39 ;CHECK: vpmaxu16:
40 ;CHECK: vpmax.u16
3841 %tmp1 = load <4 x i16>* %A
3942 %tmp2 = load <4 x i16>* %B
4043 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
4245 }
4346
4447 define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
48 ;CHECK: vpmaxu32:
49 ;CHECK: vpmax.u32
4550 %tmp1 = load <2 x i32>* %A
4651 %tmp2 = load <2 x i32>* %B
4752 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
4954 }
5055
5156 define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
57 ;CHECK: vpmaxf32:
58 ;CHECK: vpmax.f32
5259 %tmp1 = load <2 x float>* %A
5360 %tmp2 = load <2 x float>* %B
5461 %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vpmin\\.s8} %t | count 1
2 ; RUN: grep {vpmin\\.s16} %t | count 1
3 ; RUN: grep {vpmin\\.s32} %t | count 1
4 ; RUN: grep {vpmin\\.u8} %t | count 1
5 ; RUN: grep {vpmin\\.u16} %t | count 1
6 ; RUN: grep {vpmin\\.u32} %t | count 1
7 ; RUN: grep {vpmin\\.f32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
81
92 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vpmins8:
4 ;CHECK: vpmin.s8
105 %tmp1 = load <8 x i8>* %A
116 %tmp2 = load <8 x i8>* %B
127 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
149 }
1510
1611 define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vpmins16:
13 ;CHECK: vpmin.s16
1714 %tmp1 = load <4 x i16>* %A
1815 %tmp2 = load <4 x i16>* %B
1916 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2118 }
2219
2320 define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vpmins32:
22 ;CHECK: vpmin.s32
2423 %tmp1 = load <2 x i32>* %A
2524 %tmp2 = load <2 x i32>* %B
2625 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2827 }
2928
3029 define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
30 ;CHECK: vpminu8:
31 ;CHECK: vpmin.u8
3132 %tmp1 = load <8 x i8>* %A
3233 %tmp2 = load <8 x i8>* %B
3334 %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
3536 }
3637
3738 define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
39 ;CHECK: vpminu16:
40 ;CHECK: vpmin.u16
3841 %tmp1 = load <4 x i16>* %A
3942 %tmp2 = load <4 x i16>* %B
4043 %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
4245 }
4346
4447 define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
48 ;CHECK: vpminu32:
49 ;CHECK: vpmin.u32
4550 %tmp1 = load <2 x i32>* %A
4651 %tmp2 = load <2 x i32>* %B
4752 %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
4954 }
5055
5156 define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
57 ;CHECK: vpminf32:
58 ;CHECK: vpmin.f32
5259 %tmp1 = load <2 x float>* %A
5360 %tmp2 = load <2 x float>* %B
5461 %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)