llvm.org GIT mirror llvm / 676dd7c
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
10 changed file(s) with 228 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
281281 addIntervalsForSpills(const LiveInterval& i,
282282 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
283283
284 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
285 /// around all defs and uses of the specified interval.
286 void spillPhysRegAroundRegDefsUses(const LiveInterval &li,
287 unsigned PhysReg, VirtRegMap &vrm);
288
284289 /// isReMaterializable - Returns true if every definition of MI of every
285290 /// val# of the specified interval is re-materializable. Also returns true
286291 /// by reference if all of the defs are load instructions.
287292 bool isReMaterializable(const LiveInterval &li, bool &isLoad);
293
294 /// getRepresentativeReg - Find the largest super register of the specified
295 /// physical register.
296 unsigned getRepresentativeReg(unsigned Reg) const;
297
298 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
299 /// specified interval that conflicts with the specified physical register.
300 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
301 unsigned PhysReg) const;
288302
289303 private:
290304 /// computeIntervals - Compute live intervals.
358372 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
359373 /// within a single basic block.
360374 bool intervalIsInOneMBB(const LiveInterval &li) const;
375
376 /// hasAllocatableSuperReg - Return true if the specified physical register
377 /// has any super register that's allocatable.
378 bool hasAllocatableSuperReg(unsigned Reg) const;
361379
362380 /// SRInfo - Spill / restore info.
363381 struct SRInfo {
320320 }
321321
322322 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
323 /// register of the given type.
324 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
325 unsigned Reg) const;
323 /// register of the given type. If type is MVT::Other, then just return any
324 /// register class the register belongs to.
325 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
326 MVT::ValueType VT = MVT::Other) const;
326327
327328 /// getAllocatableSet - Returns a bitset indexed by register number
328329 /// indicating if a register is allocatable or not. If a register class is
16191619
16201620 return RetNewLIs;
16211621 }
1622
1623 /// hasAllocatableSuperReg - Return true if the specified physical register has
1624 /// any super register that's allocatable.
1625 bool LiveIntervals::hasAllocatableSuperReg(unsigned Reg) const {
1626 for (const unsigned* AS = tri_->getSuperRegisters(Reg); *AS; ++AS)
1627 if (allocatableRegs_[*AS] && hasInterval(*AS))
1628 return true;
1629 return false;
1630 }
1631
1632 /// getRepresentativeReg - Find the largest super register of the specified
1633 /// physical register.
1634 unsigned LiveIntervals::getRepresentativeReg(unsigned Reg) const {
1635 // Find the largest super-register that is allocatable.
1636 unsigned BestReg = Reg;
1637 for (const unsigned* AS = tri_->getSuperRegisters(Reg); *AS; ++AS) {
1638 unsigned SuperReg = *AS;
1639 if (!hasAllocatableSuperReg(SuperReg) && hasInterval(SuperReg)) {
1640 BestReg = SuperReg;
1641 break;
1642 }
1643 }
1644 return BestReg;
1645 }
1646
1647 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
1648 /// specified interval that conflicts with the specified physical register.
1649 unsigned LiveIntervals::getNumConflictsWithPhysReg(const LiveInterval &li,
1650 unsigned PhysReg) const {
1651 unsigned NumConflicts = 0;
1652 const LiveInterval &pli = getInterval(getRepresentativeReg(PhysReg));
1653 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
1654 E = mri_->reg_end(); I != E; ++I) {
1655 MachineOperand &O = I.getOperand();
1656 MachineInstr *MI = O.getParent();
1657 unsigned Index = getInstructionIndex(MI);
1658 if (pli.liveAt(Index))
1659 ++NumConflicts;
1660 }
1661 return NumConflicts;
1662 }
1663
1664 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
1665 /// around all defs and uses of the specified interval.
1666 void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
1667 unsigned PhysReg, VirtRegMap &vrm) {
1668 unsigned SpillReg = getRepresentativeReg(PhysReg);
1669
1670 for (const unsigned *AS = tri_->getAliasSet(PhysReg); *AS; ++AS)
1671 // If there are registers which alias PhysReg, but which are not a
1672 // sub-register of the chosen representative super register. Assert
1673 // since we can't handle it yet.
1674 assert(*AS == SpillReg || !allocatableRegs_[*AS] ||
1675 tri_->isSuperRegister(*AS, SpillReg));
1676
1677 LiveInterval &pli = getInterval(SpillReg);
1678 SmallPtrSet SeenMIs;
1679 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
1680 E = mri_->reg_end(); I != E; ++I) {
1681 MachineOperand &O = I.getOperand();
1682 MachineInstr *MI = O.getParent();
1683 if (SeenMIs.count(MI))
1684 continue;
1685 SeenMIs.insert(MI);
1686 unsigned Index = getInstructionIndex(MI);
1687 if (pli.liveAt(Index)) {
1688 vrm.addEmergencySpill(SpillReg, MI);
1689 pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
1690 for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
1691 if (!hasInterval(*AS))
1692 continue;
1693 LiveInterval &spli = getInterval(*AS);
1694 if (spli.liveAt(Index))
1695 spli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
1696 }
1697 }
1698 }
1699 }
560560 // is very bad (it contains all callee clobbered registers for any functions
561561 // with a call), so we want to avoid doing that if possible.
562562 unsigned physReg = getFreePhysReg(cur);
563 unsigned BestPhysReg = physReg;
563564 if (physReg) {
564565 // We got a register. However, if it's in the fixed_ list, we might
565566 // conflict with it. Check to see if we conflict with it or any of its
684685 }
685686
686687 // All registers must have inf weight. Just grab one!
687 if (!minReg)
688 minReg = *RC->allocation_order_begin(*mf_);
688 if (!minReg) {
689 if (BestPhysReg)
690 minReg = BestPhysReg;
691 else {
692 // Get the physical register with the fewest conflicts.
693 unsigned MinConflicts = ~0U;
694 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
695 e = RC->allocation_order_end(*mf_); i != e; ++i) {
696 unsigned reg = *i;
697 unsigned NumConflicts = li_->getNumConflictsWithPhysReg(*cur, reg);
698 if (NumConflicts <= MinConflicts) {
699 MinConflicts = NumConflicts;
700 minReg = reg;
701 }
702 }
703 }
704
705 if (cur->weight == HUGE_VALF || cur->getSize() == 1)
706 // Spill a physical register around defs and uses.
707 li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
708 }
689709 }
690710
691711 DOUT << "\t\tregister with min weight: "
6060 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
6161 PhysReg = Reg;
6262 const TargetRegisterClass *RC =
63 TRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
63 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
6464 Cost = RC->getCopyCost();
6565 }
6666 }
432432 }
433433
434434 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
435 SrcRC = TRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
435 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, Node->getValueType(ResNo));
436436
437437 // Figure out the register class to create for the destreg.
438438 if (VRBase) {
861861 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
862862 SrcTRC = RegInfo.getRegClass(SrcReg);
863863 else
864 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcVal.getValueType(),SrcReg);
864 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
865865
866866 if (TargetRegisterInfo::isVirtualRegister(DestReg))
867867 DstTRC = RegInfo.getRegClass(DestReg);
868868 else
869 DstTRC = TRI->getPhysicalRegisterRegClass(
870 Node->getOperand(1).getValueType(),
871 DestReg);
869 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
870 Node->getOperand(1).getValueType());
872871 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
873872 break;
874873 }
767767 // Issue expensive cross register class copies.
768768 MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
769769 const TargetRegisterClass *RC =
770 TRI->getPhysicalRegisterRegClass(VT, Reg);
770 TRI->getPhysicalRegisterRegClass(Reg, VT);
771771 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
772772 if (!DestRC) {
773773 assert(false && "Don't know how to copy this physical register!");
124124 Virt2ReMatIdMap[virtReg] = id;
125125 }
126126
127 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
128 std::map::iterator I =
129 EmergencySpillSlots.find(RC);
130 if (I != EmergencySpillSlots.end())
131 return I->second;
132 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
133 RC->getAlignment());
134 if (LowSpillSlot == NO_STACK_SLOT)
135 LowSpillSlot = SS;
136 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
137 HighSpillSlot = SS;
138 I->second = SS;
139 return SS;
140 }
141
127142 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
128143 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) {
129144 assert(FI >= 0 && "Spill slot index should not be negative!");
163178 MI2VirtMap.erase(MI);
164179 SpillPt2VirtMap.erase(MI);
165180 RestorePt2VirtMap.erase(MI);
181 EmergencySpillMap.erase(MI);
166182 }
167183
168184 void VirtRegMap::print(std::ostream &OS) const {
10421058 MachineInstr &MI = *MII;
10431059 const TargetInstrDesc &TID = MI.getDesc();
10441060
1061 if (VRM.hasEmergencySpills(&MI)) {
1062 // Spill physical register(s) in the rare case the allocator has run out
1063 // of registers to allocate.
1064 SmallSet UsedSS;
1065 std::vector &EmSpills = VRM.getEmergencySpills(&MI);
1066 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1067 unsigned PhysReg = EmSpills[i];
1068 const TargetRegisterClass *RC =
1069 TRI->getPhysicalRegisterRegClass(PhysReg);
1070 assert(RC && "Unable to determine register class!");
1071 int SS = VRM.getEmergencySpillSlot(RC);
1072 if (UsedSS.count(SS))
1073 assert(0 && "Need to spill more than one physical registers!");
1074 UsedSS.insert(SS);
1075 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1076 MachineInstr *StoreMI = prior(MII);
1077 VRM.addSpillSlotUse(SS, StoreMI);
1078 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
1079 MachineInstr *LoadMI = next(MII);
1080 VRM.addSpillSlotUse(SS, LoadMI);
1081 ++NumSpills;
1082 }
1083 }
1084
10451085 // Insert restores here if asked to.
10461086 if (VRM.isRestorePt(&MI)) {
10471087 std::vector &RestoreRegs = VRM.getRestorePtRestores(&MI);
9292 /// splitting.
9393 std::map > RestorePt2VirtMap;
9494
95 /// EmergencySpillMap - This records the physical registers that should
96 /// be spilled / restored around the MachineInstr since the register
97 /// allocator has run out of registers.
98 std::map > EmergencySpillMap;
99
100 /// EmergencySpillSlots - This records emergency spill slots used to
101 /// spill physical registers when the register allocator runs out of
102 /// registers. Ideally only one stack slot is used per function per
103 /// register class.
104 std::map EmergencySpillSlots;
105
95106 /// ReMatId - Instead of assigning a stack slot to a to be rematerialized
96107 /// virtual register, an unique id is being assigned. This keeps track of
97108 /// the highest id used so far. Note, this starts at (1<<18) to avoid
292303 }
293304 }
294305
306 /// @brief - transfer restore point information from one instruction to
307 /// another.
295308 void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
296309 std::map >::iterator I =
297310 RestorePt2VirtMap.find(Old);
305318 RestorePt2VirtMap.erase(I);
306319 }
307320
321 /// @brief records that the specified physical register must be spilled
322 /// around the specified machine instr.
323 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
324 if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
325 EmergencySpillMap[MI].push_back(PhysReg);
326 else {
327 std::vector PhysRegs;
328 PhysRegs.push_back(PhysReg);
329 EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
330 }
331 }
332
333 /// @brief returns true if one or more physical registers must be spilled
334 /// around the specified instruction.
335 bool hasEmergencySpills(MachineInstr *MI) const {
336 return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
337 }
338
339 /// @brief returns the physical registers to be spilled and restored around
340 /// the instruction.
341 std::vector &getEmergencySpills(MachineInstr *MI) {
342 return EmergencySpillMap[MI];
343 }
344
345 /// @brief return or get a emergency spill slot for the register class.
346 int getEmergencySpillSlot(const TargetRegisterClass *RC);
347
308348 /// @brief Return lowest spill slot index.
309349 int getLowSpillSlot() const {
310350 return LowSpillSlot;
3333 TargetRegisterInfo::~TargetRegisterInfo() {}
3434
3535 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
36 /// register.
36 /// register of the given type. If type is MVT::Other, then just return any
37 /// register class the register belongs to.
3738 const TargetRegisterClass *
38 TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
39 unsigned reg) const {
39 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg,
40 MVT::ValueType VT) const {
4041 assert(isPhysicalRegister(reg) && "reg must be a physical register");
4142 // Pick the register class of the right type that contains this physreg.
4243 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
43 if ((*I)->hasType(VT) && (*I)->contains(reg))
44 if ((VT == MVT::Other || (*I)->hasType(VT))
45 && (*I)->contains(reg))
4446 return *I;
4547 assert(false && "Couldn't find the register class");
4648 return 0;
4749 }
48
4950
5051 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
5152 /// registers for the specific register class.
0 ; RUN: llvm-as < %s | llc -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim
1 ; PR2134
2
3 declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind
4
5 define x86_stdcallcc i32 @parse_backslash(i8** inreg %word, i32* inreg %word_length, i32* inreg %max_length) nounwind {
6 entry:
7 %tmp6 = load i8* null, align 1 ; [#uses=1]
8 br label %bb13
9 bb13: ; preds = %entry
10 %tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext %tmp6 ) nounwind ; [#uses=1]
11 store i8* %tmp26, i8** %word, align 4
12 ret i32 0
13 }