llvm.org GIT mirror llvm / 675eb3b
Add PREFETCHW codegen support - Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 7 years ago
6 changed file(s) with 24 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
121121 "Support RTM instructions">;
122122 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
123123 "Support ADX instructions">;
124 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
125 "Support PRFCHW instructions">;
124126 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
125127 "Use LEA for adjusting the stack pointer">;
126128 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
8383 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw">;
8484
8585
86 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
86 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
87 [(int_x86_mmx_femms)]>;
8788
88 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
89 "prefetch\t$addr", []>;
89 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
90 "prefetch\t$addr",
91 [(prefetch addr:$addr, (i32 0), imm, (i32 1))]>;
9092
91 def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
92 "prefetchw\t$addr", []>;
93 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
94 [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
95 Requires<[HasPrefetchW]>;
9396
9497 // "3DNowA" instructions
9598 defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
603603 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
604604 def HasRTM : Predicate<"Subtarget->hasRTM()">;
605605 def HasADX : Predicate<"Subtarget->hasADX()">;
606 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
607 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
606608 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
607609 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
608610 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
281281 if ((ECX >> 5) & 0x1) {
282282 HasLZCNT = true;
283283 ToggleFeature(X86::FeatureLZCNT);
284 }
285 if (IsIntel && ((ECX >> 8) & 0x1)) {
286 HasPRFCHW = true;
287 ToggleFeature(X86::FeaturePRFCHW);
284288 }
285289 if (IsAMD) {
286290 if ((ECX >> 6) & 0x1) {
439443 HasBMI2 = false;
440444 HasRTM = false;
441445 HasADX = false;
446 HasPRFCHW = false;
442447 IsBTMemSlow = false;
443448 IsUAMemFast = false;
444449 HasVectorUAMem = false;
122122
123123 /// HasADX - Processor has ADX instructions.
124124 bool HasADX;
125
126 /// HasPRFCHW - Processor has PRFCHW instructions.
127 bool HasPRFCHW;
125128
126129 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
127130 bool IsBTMemSlow;
253256 bool hasBMI2() const { return HasBMI2; }
254257 bool hasRTM() const { return HasRTM; }
255258 bool hasADX() const { return HasADX; }
259 bool hasPRFCHW() const { return HasPRFCHW; }
256260 bool isBTMemSlow() const { return IsBTMemSlow; }
257261 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
258262 bool hasVectorUAMem() const { return HasVectorUAMem; }
0 ; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s
11 ; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
2 ; RUN: llc < %s -march=x86 -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
23
34 ; rdar://10538297
45
89 ; CHECK: prefetcht1
910 ; CHECK: prefetcht0
1011 ; CHECK: prefetchnta
12 ; PRFCHW: prefetchw
1113 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
1214 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
1315 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
1416 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
17 tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
1518 ret void
1619 }
1720