llvm.org GIT mirror llvm / 666020a
AMDGPU: Move trap lowering to DAG Fixes traps in any block besides the entry block, and fixes depending on a live-in physical register by using a virtual register copy. Also happens to stop emitting a nop in the case debug trap is not supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301206 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
7 changed file(s) with 89 addition(s) and 62 deletion(s). Raw diff Collapse all Expand all
8181 =============== ============= ===============================================
8282 Usage Code Sequence Description
8383 =============== ============= ===============================================
84 llvm.trap s_endpgm Causes wavefront to be terminated.
85 llvm.debugtrap s_nop No operation. Compiler warning generated that
86 there is no trap handler installed.
84 llvm.trap s_endpgm Causes wavefront to be terminated.
85 llvm.debugtrap Nothing. Compiler warning generated that there is no trap handler installed.
8786 =============== ============= ===============================================
8887
8988 Assembler
34363436 NODE_NAME_CASE(ELSE)
34373437 NODE_NAME_CASE(LOOP)
34383438 NODE_NAME_CASE(CALL)
3439 NODE_NAME_CASE(TRAP)
34393440 NODE_NAME_CASE(RET_FLAG)
34403441 NODE_NAME_CASE(RETURN_TO_EPILOG)
34413442 NODE_NAME_CASE(ENDPGM)
243243
244244 // Function call.
245245 CALL,
246 TRAP,
246247
247248 // Masked control flow nodes.
248249 IF,
7676 def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
7777 def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
7878 def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
79
80 def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
81 SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
82 [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
83 >;
7984
8085 def AMDGPUconstdata_ptr : SDNode<
8186 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
286286
287287 // On SI this is s_memtime and s_memrealtime on VI.
288288 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
289 setOperationAction(ISD::TRAP, MVT::Other, Legal);
290 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
289 setOperationAction(ISD::TRAP, MVT::Other, Custom);
290 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
291291
292292 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
293293 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
19471947 }
19481948
19491949 switch (MI.getOpcode()) {
1950 case AMDGPU::S_TRAP_PSEUDO: {
1951 const DebugLoc &DL = MI.getDebugLoc();
1952 const int TrapType = MI.getOperand(0).getImm();
1953
1954 if (Subtarget->getTrapHandlerAbi() == SISubtarget::TrapHandlerAbiHsa &&
1955 Subtarget->isTrapHandlerEnabled()) {
1956
1957 MachineFunction *MF = BB->getParent();
1958 SIMachineFunctionInfo *Info = MF->getInfo();
1959 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
1960 assert(UserSGPR != AMDGPU::NoRegister);
1961
1962 if (!BB->isLiveIn(UserSGPR))
1963 BB->addLiveIn(UserSGPR);
1964
1965 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::SGPR0_SGPR1)
1966 .addReg(UserSGPR);
1967 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_TRAP))
1968 .addImm(TrapType)
1969 .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
1970 } else {
1971 switch (TrapType) {
1972 case SISubtarget::TrapIDLLVMTrap:
1973 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM));
1974 break;
1975 case SISubtarget::TrapIDLLVMDebugTrap: {
1976 DiagnosticInfoUnsupported NoTrap(*MF->getFunction(),
1977 "debugtrap handler not supported",
1978 DL,
1979 DS_Warning);
1980 LLVMContext &C = MF->getFunction()->getContext();
1981 C.diagnose(NoTrap);
1982 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_NOP))
1983 .addImm(0);
1984 break;
1985 }
1986 default:
1987 llvm_unreachable("unsupported trap handler type!");
1988 }
1989 }
1990
1991 MI.eraseFromParent();
1992 return BB;
1993 }
19941950 case AMDGPU::SI_INIT_M0:
19951951 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
19961952 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
21622118 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
21632119 case ISD::FP_ROUND:
21642120 return lowerFP_ROUND(Op, DAG);
2121
2122 case ISD::TRAP:
2123 case ISD::DEBUGTRAP:
2124 return lowerTRAP(Op, DAG);
21652125 }
21662126 return SDValue();
21672127 }
24282388 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
24292389 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
24302390 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);;
2391 }
2392
2393 SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
2394 SDLoc SL(Op);
2395 MachineFunction &MF = DAG.getMachineFunction();
2396 SDValue Chain = Op.getOperand(0);
2397
2398 unsigned TrapID = Op.getOpcode() == ISD::DEBUGTRAP ?
2399 SISubtarget::TrapIDLLVMDebugTrap : SISubtarget::TrapIDLLVMTrap;
2400
2401 if (Subtarget->getTrapHandlerAbi() == SISubtarget::TrapHandlerAbiHsa &&
2402 Subtarget->isTrapHandlerEnabled()) {
2403 SIMachineFunctionInfo *Info = MF.getInfo();
2404 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
2405 assert(UserSGPR != AMDGPU::NoRegister);
2406
2407 SDValue QueuePtr = CreateLiveInRegister(
2408 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
2409
2410 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
2411
2412 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
2413 QueuePtr, SDValue());
2414
2415 SDValue Ops[] = {
2416 ToReg,
2417 DAG.getTargetConstant(TrapID, SL, MVT::i16),
2418 SGPR01,
2419 ToReg.getValue(1)
2420 };
2421
2422 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
2423 }
2424
2425 switch (TrapID) {
2426 case SISubtarget::TrapIDLLVMTrap:
2427 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
2428 case SISubtarget::TrapIDLLVMDebugTrap: {
2429 DiagnosticInfoUnsupported NoTrap(*MF.getFunction(),
2430 "debugtrap handler not supported",
2431 Op.getDebugLoc(),
2432 DS_Warning);
2433 LLVMContext &Ctx = MF.getFunction()->getContext();
2434 Ctx.diagnose(NoTrap);
2435 return Chain;
2436 }
2437 default:
2438 llvm_unreachable("unsupported trap handler type!");
2439 }
2440
2441 return Chain;
24312442 }
24322443
24332444 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
109109 def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
110110 (ins VSrc_b64:$src0)>;
111111 } // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC]
112
113 def S_TRAP_PSEUDO : SPseudoInstSI <(outs), (ins i16imm:$simm16)> {
114 let hasSideEffects = 1;
115 let SALU = 1;
116 let usesCustomInserter = 1;
117 }
118112
119113 let usesCustomInserter = 1, SALU = 1 in {
120114 def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
399393
400394 let Predicates = [isGCN] in {
401395 def : Pat<
402 (trap),
403 (S_TRAP_PSEUDO TRAPID.LLVM_TRAP)
404 >;
405
406 def : Pat<
407 (debugtrap),
408 (S_TRAP_PSEUDO TRAPID.LLVM_DEBUG_TRAP)
396 (AMDGPUtrap timm:$trapid),
397 (S_TRAP $trapid)
409398 >;
410399
411400 def : Pat<
7979 ret void
8080 }
8181
82 ; GCN-LABEL: {{^}}non_entry_trap:
83 ; TRAP-BIT: enable_trap_handler = 1
84 ; NO-TRAP-BIT: enable_trap_handler = 0
85
86 ; HSA: BB{{[0-9]_[0-9]+]]: ; %trap
87 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
88 ; HSA-TRAP-NEXT: s_trap 2
89 define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr #1 {
90 entry:
91 %tmp29 = load volatile i32, i32 addrspace(1)* %arg0
92 %cmp = icmp eq i32 %tmp29, -1
93 br i1 %cmp, label %ret, label %trap
94
95 trap:
96 call void @llvm.trap()
97 unreachable
98
99 ret:
100 ret void
101 }
102
82103 attributes #0 = { nounwind noreturn }