llvm.org GIT mirror llvm / 663e339
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 10 years ago
3 changed file(s) with 12 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
451451 /// binop that produces a value.
452452 multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode,
453453 bit Commutable = 0> {
454 // The register-immediate version is re-materializable. This is useful
455 // in particular for taking the address of a local.
456 let isReMaterializable = 1 in {
454457 def ri : AsI1
455458 IIC_iALUi, opc, "\t$dst, $a, $b",
456459 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
457460 let Inst{25} = 1;
461 }
458462 }
459463 def rr : AsI1
460464 IIC_iALUr, opc, "\t$dst, $a, $b",
220220 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
221221
222222 // ADD rd, sp, #imm8
223 // This is rematerializable, which is particularly useful for taking the
224 // address of locals.
225 let isReMaterializable = 1 in {
223226 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
224227 "add\t$dst, $sp, $rhs", []>,
225228 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
229 }
226230
227231 // ADD sp, sp, #imm7
228232 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
381381 multiclass T2I_bin_ii12rs op23_21, string opc, PatFrag opnode,
382382 bit Commutable = 0> {
383383 // shifted imm
384 // The register-immediate version is re-materializable. This is useful
385 // in particular for taking the address of a local.
386 let isReMaterializable = 1 in {
384387 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
385388 opc, ".w\t$dst, $lhs, $rhs",
386389 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
390393 let Inst{23-21} = op23_21;
391394 let Inst{20} = 0; // The S bit.
392395 let Inst{15} = 0;
396 }
393397 }
394398 // 12-bit imm
395399 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,