llvm.org GIT mirror llvm / 663aebf
remove some old autoupgrade logic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145167 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
4 changed file(s) with 4 addition(s) and 282 deletion(s). Raw diff Collapse all Expand all
106106 }
107107
108108 break;
109 case 'x': {
110 const char *NewFnName = NULL;
111 // This fixes the poorly named crc32 intrinsics.
112 if (Name == "x86.sse42.crc32.8")
113 NewFnName = "llvm.x86.sse42.crc32.32.8";
114 else if (Name == "x86.sse42.crc32.16")
115 NewFnName = "llvm.x86.sse42.crc32.32.16";
116 else if (Name == "x86.sse42.crc32.32")
117 NewFnName = "llvm.x86.sse42.crc32.32.32";
118 else if (Name == "x86.sse42.crc64.8")
119 NewFnName = "llvm.x86.sse42.crc32.64.8";
120 else if (Name == "x86.sse42.crc64.64")
121 NewFnName = "llvm.x86.sse42.crc32.64.64";
122
123 if (NewFnName) {
124 F->setName(NewFnName);
125 NewFn = F;
126 return true;
127 }
128
129 // Calls to these instructions are transformed into unaligned loads.
130 if (Name == "x86.sse.loadu.ps" || Name == "x86.sse2.loadu.dq" ||
131 Name == "x86.sse2.loadu.pd")
132 return true;
133
134 // Calls to these instructions are transformed into nontemporal stores.
135 if (Name == "x86.sse.movnt.ps" || Name == "x86.sse2.movnt.dq" ||
136 Name == "x86.sse2.movnt.pd" || Name == "x86.sse2.movnt.i")
137 return true;
138
139 break;
140 }
141109 }
142110
143111 // This may not belong here. This function is effectively being overloaded
175143 assert(F && "CallInst has no function associated with it.");
176144
177145 if (!NewFn) {
178 if (F->getName() == "llvm.x86.sse.loadu.ps" ||
179 F->getName() == "llvm.x86.sse2.loadu.dq" ||
180 F->getName() == "llvm.x86.sse2.loadu.pd") {
181 // Convert to a native, unaligned load.
182 Type *VecTy = CI->getType();
183 Type *IntTy = IntegerType::get(C, 128);
184 IRBuilder<> Builder(C);
185 Builder.SetInsertPoint(CI->getParent(), CI);
186
187 Value *BC = Builder.CreateBitCast(CI->getArgOperand(0),
188 PointerType::getUnqual(IntTy),
189 "cast");
190 LoadInst *LI = Builder.CreateLoad(BC, CI->getName());
191 LI->setAlignment(1); // Unaligned load.
192 BC = Builder.CreateBitCast(LI, VecTy, "new.cast");
193
194 // Fix up all the uses with our new load.
195 if (!CI->use_empty())
196 CI->replaceAllUsesWith(BC);
197
198 // Remove intrinsic.
199 CI->eraseFromParent();
200 } else if (F->getName() == "llvm.x86.sse.movnt.ps" ||
201 F->getName() == "llvm.x86.sse2.movnt.dq" ||
202 F->getName() == "llvm.x86.sse2.movnt.pd" ||
203 F->getName() == "llvm.x86.sse2.movnt.i") {
204 IRBuilder<> Builder(C);
205 Builder.SetInsertPoint(CI->getParent(), CI);
206
207 Module *M = F->getParent();
208 SmallVector Elts;
209 Elts.push_back(ConstantInt::get(Type::getInt32Ty(C), 1));
210 MDNode *Node = MDNode::get(C, Elts);
211
212 Value *Arg0 = CI->getArgOperand(0);
213 Value *Arg1 = CI->getArgOperand(1);
214
215 // Convert the type of the pointer to a pointer to the stored type.
216 Value *BC = Builder.CreateBitCast(Arg0,
217 PointerType::getUnqual(Arg1->getType()),
218 "cast");
219 StoreInst *SI = Builder.CreateStore(Arg1, BC);
220 SI->setMetadata(M->getMDKindID("nontemporal"), Node);
221 SI->setAlignment(16);
222
223 // Remove intrinsic.
224 CI->eraseFromParent();
225 } else if (F->getName().startswith("llvm.atomic.cmp.swap")) {
146 if (F->getName().startswith("llvm.atomic.cmp.swap")) {
226147 IRBuilder<> Builder(C);
227148 Builder.SetInsertPoint(CI->getParent(), CI);
228149 Value *Val = Builder.CreateAtomicCmpXchg(CI->getArgOperand(0),
0 ; Tests to make sure intrinsics are automatically upgraded.
11 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
22
3
4 declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readnone
5 declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone
6 declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone
7 define void @test_loadu(i8* %a, double* %b) {
8 %v0 = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a)
9 %v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a)
10 %v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b)
11
12 ; CHECK: load i128* {{.*}}, align 1
13 ; CHECK: load i128* {{.*}}, align 1
14 ; CHECK: load i128* {{.*}}, align 1
15 ret void
16 }
17
18 declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind readnone
19 declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x double>) nounwind readnone
20 declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind readnone
21 declare void @llvm.x86.sse2.movnt.i(i8*, i32) nounwind readnone
22
23 define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D) {
24 ; CHECK: store{{.*}}nontemporal
25 call void @llvm.x86.sse.movnt.ps(i8* %B, <4 x float> %A)
26 ; CHECK: store{{.*}}nontemporal
27 call void @llvm.x86.sse2.movnt.dq(i8* %B, <2 x double> %C)
28 ; CHECK: store{{.*}}nontemporal
29 call void @llvm.x86.sse2.movnt.pd(i8* %B, <2 x double> %C)
30 ; CHECK: store{{.*}}nontemporal
31 call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D)
32 ret void
33 }
343
354 declare void @llvm.prefetch(i8*, i32, i32) nounwind
365
+0
-44
test/Bitcode/sse42_crc32.ll less more
None ; Check to make sure old CRC32 intrinsics are auto-upgraded correctly.
1 ; Auto-upgrade happens when parsing a .bc or a .ll file. Thus, leave the test
2 ; case as a .ll file so we can see what's going on.
3 ;
4 ; Rdar: 9472944
5 ;
6 ; RUN: opt < %s -S | FileCheck %s
7
8 ; crc32.8 should upgrade to crc32.32.8
9 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
10 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.8(
11
12 ; crc32.16 should upgrade to crc32.32.16
13 ; CHECK: i32 @llvm.x86.sse42.crc32.32.16(
14 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.16(
15
16 ; crc32.32 should upgrade to crc32.32.32
17 ; CHECK: i32 @llvm.x86.sse42.crc32.32.32(
18 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.32(
19
20 ; crc64.8 should upgrade to crc32.64.8
21 ; CHECK: i64 @llvm.x86.sse42.crc32.64.8(
22 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.8(
23
24 ; crc64.64 should upgrade to crc32.64.64
25 ; CHECK: i64 @llvm.x86.sse42.crc32.64.64(
26 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
27
28
29 define void @foo() nounwind readnone ssp {
30 entry:
31 %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
32 %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
33 %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
34 %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
35 %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
36 ret void
37 }
38
39 declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
40 declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
41 declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
42 declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
43 declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
244244 declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone
245245
246246
247 define <16 x i8> @test_x86_sse2_loadu_dq(i8* %a0) {
248 ; CHECK: movl
249 ; CHECK: vmovups
250 %res = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a0) ; <<16 x i8>> [#uses=1]
251 ret <16 x i8> %res
252 }
253 declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readonly
254
255
256 define <2 x double> @test_x86_sse2_loadu_pd(i8* %a0) {
257 ; CHECK: movl
258 ; CHECK: vmovups
259 %res = call <2 x double> @llvm.x86.sse2.loadu.pd(i8* %a0) ; <<2 x double>> [#uses=1]
260 ret <2 x double> %res
261 }
262 declare <2 x double> @llvm.x86.sse2.loadu.pd(i8*) nounwind readonly
263
264
265 define void @test_x86_sse2_maskmov_dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) {
266 ; CHECK: pushl
267 ; CHECK: movl
268 ; CHECK: vmaskmovdqu
269 ; CHECK: popl
270 call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2)
271 ret void
272 }
273 declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
274
275247
276248 define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) {
277249 ; CHECK: vmaxpd
313285 declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
314286
315287
316 define void @test_x86_sse2_movnt_dq(i8* %a0, <2 x i64> %a1) {
317 ; CHECK: test_x86_sse2_movnt_dq
318 ; CHECK: movl
319 ; CHECK: vmovntdq
320 ; add operation forces the execution domain.
321 %a2 = add <2 x i64> %a1,
322 call void @llvm.x86.sse2.movnt.dq(i8* %a0, <2 x i64> %a2)
323 ret void
324 }
325 declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x i64>) nounwind
326
327
328 define void @test_x86_sse2_movnt_pd(i8* %a0, <2 x double> %a1) {
329 ; CHECK test_x86_sse2_movnt_pd
330 ; CHECK: movl
331 ; CHECK: vmovntpd
332 ; fadd operation forces the execution domain.
333 %a2 = fadd <2 x double> %a1,
334 call void @llvm.x86.sse2.movnt.pd(i8* %a0, <2 x double> %a2)
335 ret void
336 }
337 declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind
338288
339289
340290 define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) {
966916 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
967917
968918
969 define <2 x i64> @test_x86_sse41_movntdqa(i8* %a0) {
970 ; CHECK: movl
971 ; CHECK: vmovntdqa
972 %res = call <2 x i64> @llvm.x86.sse41.movntdqa(i8* %a0) ; <<2 x i64>> [#uses=1]
973 ret <2 x i64> %res
974 }
975 declare <2 x i64> @llvm.x86.sse41.movntdqa(i8*) nounwind readonly
976
977919
978920 define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
979921 ; CHECK: vmpsadbw
15231465 declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind
15241466
15251467
1526 define <4 x float> @test_x86_sse_loadu_ps(i8* %a0) {
1527 ; CHECK: movl
1528 ; CHECK: vmovups
1529 %res = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a0) ; <<4 x float>> [#uses=1]
1530 ret <4 x float> %res
1531 }
1532 declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readonly
1533
15341468
15351469 define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) {
15361470 ; CHECK: vmaxps
15711505 }
15721506 declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
15731507
1574
1575 define void @test_x86_sse_movnt_ps(i8* %a0, <4 x float> %a1) {
1576 ; CHECK: movl
1577 ; CHECK: vmovntps
1578 call void @llvm.x86.sse.movnt.ps(i8* %a0, <4 x float> %a1)
1579 ret void
1580 }
1581 declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind
15821508
15831509
15841510 define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
20181944 declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
20191945
20201946
2021 define <32 x i8> @test_x86_avx_loadu_dq_256(i8* %a0) {
2022 ; CHECK: vmovdqu
2023 %a1 = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
2024 ; add operation forces the execution domain.
2025 %res = add <32 x i8> %a1,
2026 ret <32 x i8> %res
2027 }
2028 declare <32 x i8> @llvm.x86.avx.loadu.dq.256(i8*) nounwind readonly
2029
2030
2031 define <4 x double> @test_x86_avx_loadu_pd_256(i8* %a0) {
2032 ; CHECK: vmovupd
2033 %a1 = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
2034 ; add operation forces the execution domain.
2035 %res = fadd <4 x double> %a1,
2036 ret <4 x double> %res
2037 }
2038 declare <4 x double> @llvm.x86.avx.loadu.pd.256(i8*) nounwind readonly
2039
2040
2041 define <8 x float> @test_x86_avx_loadu_ps_256(i8* %a0) {
2042 ; CHECK: vmovups
2043 %res = call <8 x float> @llvm.x86.avx.loadu.ps.256(i8* %a0) ; <<8 x float>> [#uses=1]
2044 ret <8 x float> %res
2045 }
2046 declare <8 x float> @llvm.x86.avx.loadu.ps.256(i8*) nounwind readonly
2047
2048
20491947 define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) {
20501948 ; CHECK: vmaskmovpd
20511949 %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
21582056 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
21592057
21602058
2161 define void @test_x86_avx_movnt_dq_256(i8* %a0, <4 x i64> %a1) {
2162 ; CHECK: vmovntdq
2163 ; add operation forces the execution domain.
2164 %a2 = add <4 x i64> %a1,
2165 call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a2)
2166 ret void
2167 }
2168 declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
2169
2170
2171 define void @test_x86_avx_movnt_pd_256(i8* %a0, <4 x double> %a1) {
2172 ; CHECK: vmovntpd
2173 %a2 = fadd <4 x double> %a1,
2174 call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a2)
2175 ret void
2176 }
2177 declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
2178
2179
2180 define void @test_x86_avx_movnt_ps_256(i8* %a0, <8 x float> %a1) {
2181 ; CHECK: vmovntps
2182 call void @llvm.x86.avx.movnt.ps.256(i8* %a0, <8 x float> %a1)
2183 ret void
2184 }
2185 declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
2059
2060
2061
21862062
21872063
21882064 define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {