llvm.org GIT mirror llvm / 65fb103
[X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. The %eiz/%riz are dummy registers that force the encoder to emit a SIB byte when it normally wouldn't. By emitting them in the disassembly output we ensure that assembling the disassembler output would also produce a SIB byte. This should match the behavior of objdump from binutils. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335768 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
3 changed file(s) with 59 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
757757 #undef ENTRY
758758 }
759759 } else {
760 baseReg = MCOperand::createReg(0);
760 baseReg = MCOperand::createReg(X86::NoRegister);
761761 }
762762
763763 if (insn.sibIndex != SIB_INDEX_NONE) {
776776 #undef ENTRY
777777 }
778778 } else {
779 indexReg = MCOperand::createReg(0);
779 // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
780 // but no index is used and modrm alone should have been enough.
781 // -No base register in 32-bit mode. In 64-bit mode this is used to
782 // avoid rip-relative addressing.
783 // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
784 // base always requires a SIB byte.
785 // -A scale other than 1 is used.
786 if (insn.sibScale != 1 ||
787 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
788 ((insn.sibBase != SIB_BASE_NONE &&
789 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
790 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12)) {
791 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
792 X86::RIZ);
793 } else
794 indexReg = MCOperand::createReg(X86::NoRegister);
780795 }
781796
782797 scaleAmount = MCOperand::createImm(insn.sibScale);
798813 X86::RIP);
799814 }
800815 else
801 baseReg = MCOperand::createReg(0);
802
803 indexReg = MCOperand::createReg(0);
816 baseReg = MCOperand::createReg(X86::NoRegister);
817
818 indexReg = MCOperand::createReg(X86::NoRegister);
804819 break;
805820 case EA_BASE_BX_SI:
806821 baseReg = MCOperand::createReg(X86::BX);
819834 indexReg = MCOperand::createReg(X86::DI);
820835 break;
821836 default:
822 indexReg = MCOperand::createReg(0);
837 indexReg = MCOperand::createReg(X86::NoRegister);
823838 switch (insn.eaBase) {
824839 default:
825840 debug("Unexpected eaBase");
888888
889889 #CHECK: vgatherdps (%esi,%zmm0,4), %zmm1 {%k2}
890890 0x62 0xf2 0x7d 0x42 0x92 0x0c 0x86
891
892 # CHECK: addb $0, 305419896(%ebp,%eiz)
893 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
894
895 # CHECK: addb $0, 305419896(%ebp,%eiz,2)
896 0x80 0x84 0x65 0x78 0x56 0x34 0x12 0x00
897
898 # CHECK: addb $0, 305419896(%esp,%eiz,2)
899 0x80 0x84 0x64 0x78 0x56 0x34 0x12 0x00
900
901 # CHECK: addb $0, 305419896(,%eiz)
902 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
271271 # CHECK: pextrw $3, %xmm3, (%rax)
272272 0x66 0x0f 0x3a 0x15 0x18 0x03
273273
274 # CHECK: $0, 305419896(,%r8)
274 # CHECK: addb $0, 305419896(,%r8)
275275 0x43 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
276276
277 # CHECK: $0, 305419896(%r13,%r8)
277 # CHECK: addb $0, 305419896(%r13,%r8)
278278 0x43 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
279279
280 # CHECK: $0, 305419896(,%r8)
280 # CHECK: addb $0, 305419896(,%r8)
281281 0x42 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
282282
283 # CHECK: $0, 305419896(%rbp,%r8)
283 # CHECK: addb $0, 305419896(%rbp,%r8)
284284 0x42 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
285285
286 # CHECK: $0, 305419896(,%r12)
286 # CHECK: addb $0, 305419896(,%r12)
287287 0x42 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
288288
289 # CHECK: $0, 305419896(%rbp,%r12)
289 # CHECK: addb $0, 305419896(%rbp,%r12)
290290 0x42 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
291291
292 # CHECK: $0, 305419896
292 # CHECK: addb $0, 305419896
293293 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
294294
295 # CHECK: $0, 305419896(%rbp)
295 # CHECK: addb $0, 305419896(%rbp)
296 0x80 0x85 0x78 0x56 0x34 0x12 0x00
297
298 # CHECK: addb $0, 305419896(%rbp,%riz)
296299 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
300
301 # CHECK: addb $0, 305419896(%rbp,%riz,2)
302 0x80 0x84 0x65 0x78 0x56 0x34 0x12 0x00
303
304 # CHECK: addb $0, 305419896(%rsp,%riz,2)
305 0x80 0x84 0x64 0x78 0x56 0x34 0x12 0x00
306
307 # CHECK: addb $0, 305419896(%r12,%riz,2)
308 0x41 0x80 0x84 0x64 0x78 0x56 0x34 0x12 0x00
309
310 # CHECK: addb $0, 305419896(%esp,%eiz,2)
311 0x67 0x80 0x84 0x64 0x78 0x56 0x34 0x12 0x00
312
313 # CHECK: addb $0, 305419896(%r12d,%eiz,2)
314 0x67 0x41 0x80 0x84 0x64 0x78 0x56 0x34 0x12 0x00
297315
298316 # CHECK: movabsq 6510615555426900570, %rax
299317 0x48 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a