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PowerPC: Simplify handling of fixups. MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 6 years ago
5 changed file(s) with 23 addition(s) and 74 deletion(s). Raw diff Collapse all Expand all
479479 R_PPC64_TOC16_LO = 48,
480480 R_PPC64_TOC16_HA = 50,
481481 R_PPC64_TOC = 51,
482 R_PPC64_ADDR16_DS = 56,
483 R_PPC64_ADDR16_LO_DS = 57,
482484 R_PPC64_TOC16_DS = 63,
483485 R_PPC64_TOC16_LO_DS = 64,
484486 R_PPC64_TLS = 67,
2929 case FK_Data_2:
3030 case FK_Data_4:
3131 case FK_Data_8:
32 case PPC::fixup_ppc_toc:
3332 case PPC::fixup_ppc_tlsreg:
3433 case PPC::fixup_ppc_nofixup:
3534 return Value;
36 case PPC::fixup_ppc_lo14:
37 case PPC::fixup_ppc_toc16_ds:
38 return (Value & 0xffff) << 2;
3935 case PPC::fixup_ppc_brcond14:
4036 return Value & 0xfffc;
4137 case PPC::fixup_ppc_br24:
4743 case PPC::fixup_ppc_ha16:
4844 return ((Value >> 16) + ((Value & 0x8000) ? 1 : 0)) & 0xffff;
4945 case PPC::fixup_ppc_lo16:
50 case PPC::fixup_ppc_toc16:
5146 return Value & 0xffff;
47 case PPC::fixup_ppc_lo16_ds:
48 return Value & 0xfffc;
5249 }
5350 }
5451
8178 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
8279 { "fixup_ppc_lo16", 16, 16, 0 },
8380 { "fixup_ppc_ha16", 16, 16, 0 },
84 { "fixup_ppc_lo14", 16, 14, 0 },
85 { "fixup_ppc_toc", 0, 64, 0 },
86 { "fixup_ppc_toc16", 16, 16, 0 },
87 { "fixup_ppc_toc16_ds", 16, 14, 0 },
81 { "fixup_ppc_lo16_ds", 16, 14, 0 },
8882 { "fixup_ppc_tlsreg", 0, 0, 0 },
8983 { "fixup_ppc_nofixup", 0, 0, 0 }
9084 };
132132 case MCSymbolRefExpr::VK_None:
133133 Type = ELF::R_PPC_ADDR16_LO;
134134 break;
135 case MCSymbolRefExpr::VK_PPC_TOC_ENTRY:
136 Type = ELF::R_PPC64_TOC16;
137 break;
135138 case MCSymbolRefExpr::VK_PPC_TOC16_LO:
136139 Type = ELF::R_PPC64_TOC16_LO;
137140 break;
143146 break;
144147 }
145148 break;
146 case PPC::fixup_ppc_lo14:
147 Type = ELF::R_PPC_ADDR14;
148 break;
149 case PPC::fixup_ppc_toc:
150 Type = ELF::R_PPC64_TOC;
151 break;
152 case PPC::fixup_ppc_toc16:
153 switch (Modifier) {
154 default: llvm_unreachable("Unsupported Modifier");
155 case MCSymbolRefExpr::VK_PPC_TPREL16_LO:
156 Type = ELF::R_PPC64_TPREL16_LO;
157 break;
158 case MCSymbolRefExpr::VK_PPC_DTPREL16_LO:
159 Type = ELF::R_PPC64_DTPREL16_LO;
160 break;
161 case MCSymbolRefExpr::VK_None:
162 Type = ELF::R_PPC64_TOC16;
163 break;
164 case MCSymbolRefExpr::VK_PPC_TOC16_LO:
165 Type = ELF::R_PPC64_TOC16_LO;
166 break;
167 case MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_LO:
168 Type = ELF::R_PPC64_GOT_TLSLD16_LO;
169 break;
170 }
171 break;
172 case PPC::fixup_ppc_toc16_ds:
173 switch (Modifier) {
174 default: llvm_unreachable("Unsupported Modifier");
149 case PPC::fixup_ppc_lo16_ds:
150 switch (Modifier) {
151 default: llvm_unreachable("Unsupported Modifier");
152 case MCSymbolRefExpr::VK_None:
153 Type = ELF::R_PPC64_ADDR16_DS;
154 break;
175155 case MCSymbolRefExpr::VK_PPC_TOC_ENTRY:
176156 Type = ELF::R_PPC64_TOC16_DS;
177157 break;
252232 switch ((unsigned)Fixup.getKind()) {
253233 case PPC::fixup_ppc_ha16:
254234 case PPC::fixup_ppc_lo16:
255 case PPC::fixup_ppc_toc16:
256 case PPC::fixup_ppc_toc16_ds:
235 case PPC::fixup_ppc_lo16_ds:
257236 RelocOffset += 2;
258237 break;
259238 default:
3232 /// like 'lis'.
3333 fixup_ppc_ha16,
3434
35 /// fixup_ppc_lo14 - A 14-bit fixup corresponding to lo16(_foo) for instrs
36 /// like 'std'.
37 fixup_ppc_lo14,
38
39 /// fixup_ppc_toc - Insert value of TOC base (.TOC.).
40 fixup_ppc_toc,
41
42 /// fixup_ppc_toc16 - A 16-bit signed fixup relative to the TOC base.
43 fixup_ppc_toc16,
44
45 /// fixup_ppc_toc16_ds - A 14-bit signed fixup relative to the TOC base with
46 /// implied 2 zero bits
47 fixup_ppc_toc16_ds,
35 /// fixup_ppc_lo16_ds - A 14-bit fixup corresponding to lo16(_foo) with
36 /// implied 2 zero bits for instrs like 'std'.
37 fixup_ppc_lo16_ds,
4838
4939 /// fixup_ppc_tlsreg - Insert thread-pointer register number.
5040 fixup_ppc_tlsreg,
4141 }
4242
4343 ~PPCMCCodeEmitter() {}
44
45 bool is64BitMode() const {
46 return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
47 }
48
49 bool isSVR4ABI() const {
50 return TT.isMacOSX() == 0;
51 }
5244
5345 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
5446 SmallVectorImpl &Fixups) const;
176168 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
177169
178170 // Add a fixup for the displacement field.
179 if (isSVR4ABI() && is64BitMode())
180 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
181 (MCFixupKind)PPC::fixup_ppc_toc16));
182 else
183 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
184 (MCFixupKind)PPC::fixup_ppc_lo16));
171 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
172 (MCFixupKind)PPC::fixup_ppc_lo16));
185173 return RegBits;
186174 }
187175
197185 if (MO.isImm())
198186 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
199187
200 // Add a fixup for the branch target.
201 if (isSVR4ABI() && is64BitMode())
202 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
203 (MCFixupKind)PPC::fixup_ppc_toc16_ds));
204 else
205 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
206 (MCFixupKind)PPC::fixup_ppc_lo14));
188 // Add a fixup for the displacement field.
189 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
190 (MCFixupKind)PPC::fixup_ppc_lo16_ds));
207191 return RegBits;
208192 }
209193