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[ARM] Tidy up banked registers encoding Moves encoding (SYSm) information of banked registers to ARMSystemRegister.td, where it rightly belongs and forms a single point of reference in the code. Reviewed by: @fhahn, @rovka, @olista01 Differential Revision: https://reviews.llvm.org/D36219 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309910 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
5 changed file(s) with 74 addition(s) and 77 deletion(s). Raw diff Collapse all Expand all
37643764 // which mode it is to be used, e.g. usr. Returns -1 to signify that the string
37653765 // was invalid.
37663766 static inline int getBankedRegisterMask(StringRef RegString) {
3767 return StringSwitch(RegString.lower())
3768 .Case("r8_usr", 0x00)
3769 .Case("r9_usr", 0x01)
3770 .Case("r10_usr", 0x02)
3771 .Case("r11_usr", 0x03)
3772 .Case("r12_usr", 0x04)
3773 .Case("sp_usr", 0x05)
3774 .Case("lr_usr", 0x06)
3775 .Case("r8_fiq", 0x08)
3776 .Case("r9_fiq", 0x09)
3777 .Case("r10_fiq", 0x0a)
3778 .Case("r11_fiq", 0x0b)
3779 .Case("r12_fiq", 0x0c)
3780 .Case("sp_fiq", 0x0d)
3781 .Case("lr_fiq", 0x0e)
3782 .Case("lr_irq", 0x10)
3783 .Case("sp_irq", 0x11)
3784 .Case("lr_svc", 0x12)
3785 .Case("sp_svc", 0x13)
3786 .Case("lr_abt", 0x14)
3787 .Case("sp_abt", 0x15)
3788 .Case("lr_und", 0x16)
3789 .Case("sp_und", 0x17)
3790 .Case("lr_mon", 0x1c)
3791 .Case("sp_mon", 0x1d)
3792 .Case("elr_hyp", 0x1e)
3793 .Case("sp_hyp", 0x1f)
3794 .Case("spsr_fiq", 0x2e)
3795 .Case("spsr_irq", 0x30)
3796 .Case("spsr_svc", 0x32)
3797 .Case("spsr_abt", 0x34)
3798 .Case("spsr_und", 0x36)
3799 .Case("spsr_mon", 0x3c)
3800 .Case("spsr_hyp", 0x3e)
3801 .Default(-1);
3767 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegString.lower());
3768 if (!TheReg)
3769 return -1;
3770 return TheReg->Encoding;
38023771 }
38033772
38043773 // The flags here are common to those allowed for apsr in the A class cores and
105105 def : MClassSysReg<0, 0, 1, 0x894, "control_ns">;
106106 def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">;
107107 }
108
109
110 // Banked Registers
111 //
112 class BankedReg enc>
113 : SearchableTable {
114 string Name;
115 bits<8> Encoding;
116 let Name = name;
117 let Encoding = enc;
118 let SearchableFields = ["Name", "Encoding"];
119 }
120
121 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
122 // and bit 5 is R.
123 def : BankedReg<"r8_usr", 0x00>;
124 def : BankedReg<"r9_usr", 0x01>;
125 def : BankedReg<"r10_usr", 0x02>;
126 def : BankedReg<"r11_usr", 0x03>;
127 def : BankedReg<"r12_usr", 0x04>;
128 def : BankedReg<"sp_usr", 0x05>;
129 def : BankedReg<"lr_usr", 0x06>;
130 def : BankedReg<"r8_fiq", 0x08>;
131 def : BankedReg<"r9_fiq", 0x09>;
132 def : BankedReg<"r10_fiq", 0x0a>;
133 def : BankedReg<"r11_fiq", 0x0b>;
134 def : BankedReg<"r12_fiq", 0x0c>;
135 def : BankedReg<"sp_fiq", 0x0d>;
136 def : BankedReg<"lr_fiq", 0x0e>;
137 def : BankedReg<"lr_irq", 0x10>;
138 def : BankedReg<"sp_irq", 0x11>;
139 def : BankedReg<"lr_svc", 0x12>;
140 def : BankedReg<"sp_svc", 0x13>;
141 def : BankedReg<"lr_abt", 0x14>;
142 def : BankedReg<"sp_abt", 0x15>;
143 def : BankedReg<"lr_und", 0x16>;
144 def : BankedReg<"sp_und", 0x17>;
145 def : BankedReg<"lr_mon", 0x1c>;
146 def : BankedReg<"sp_mon", 0x1d>;
147 def : BankedReg<"elr_hyp", 0x1e>;
148 def : BankedReg<"sp_hyp", 0x1f>;
149 def : BankedReg<"spsr_fiq", 0x2e>;
150 def : BankedReg<"spsr_irq", 0x30>;
151 def : BankedReg<"spsr_svc", 0x32>;
152 def : BankedReg<"spsr_abt", 0x34>;
153 def : BankedReg<"spsr_und", 0x36>;
154 def : BankedReg<"spsr_mon", 0x3c>;
155 def : BankedReg<"spsr_hyp", 0x3e>;
41744174 return MatchOperand_NoMatch;
41754175 StringRef RegName = Tok.getString();
41764176
4177 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4178 // and bit 5 is R.
4179 unsigned Encoding = StringSwitch(RegName.lower())
4180 .Case("r8_usr", 0x00)
4181 .Case("r9_usr", 0x01)
4182 .Case("r10_usr", 0x02)
4183 .Case("r11_usr", 0x03)
4184 .Case("r12_usr", 0x04)
4185 .Case("sp_usr", 0x05)
4186 .Case("lr_usr", 0x06)
4187 .Case("r8_fiq", 0x08)
4188 .Case("r9_fiq", 0x09)
4189 .Case("r10_fiq", 0x0a)
4190 .Case("r11_fiq", 0x0b)
4191 .Case("r12_fiq", 0x0c)
4192 .Case("sp_fiq", 0x0d)
4193 .Case("lr_fiq", 0x0e)
4194 .Case("lr_irq", 0x10)
4195 .Case("sp_irq", 0x11)
4196 .Case("lr_svc", 0x12)
4197 .Case("sp_svc", 0x13)
4198 .Case("lr_abt", 0x14)
4199 .Case("sp_abt", 0x15)
4200 .Case("lr_und", 0x16)
4201 .Case("sp_und", 0x17)
4202 .Case("lr_mon", 0x1c)
4203 .Case("sp_mon", 0x1d)
4204 .Case("elr_hyp", 0x1e)
4205 .Case("sp_hyp", 0x1f)
4206 .Case("spsr_fiq", 0x2e)
4207 .Case("spsr_irq", 0x30)
4208 .Case("spsr_svc", 0x32)
4209 .Case("spsr_abt", 0x34)
4210 .Case("spsr_und", 0x36)
4211 .Case("spsr_mon", 0x3c)
4212 .Case("spsr_hyp", 0x3e)
4213 .Default(~0U);
4214
4215 if (Encoding == ~0U)
4177 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
4178 if (!TheReg)
42164179 return MatchOperand_NoMatch;
4180 unsigned Encoding = TheReg->Encoding;
42174181
42184182 Parser.Lex(); // Eat identifier token.
42194183 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
1717
1818 using namespace llvm;
1919 namespace llvm {
20 namespace ARMSysReg {
20 namespace ARMSysReg {
2121
2222 // lookup system register using 12-bit SYSm value.
2323 // Note: the search is uniqued using M1 mask
3939 #define GET_MCLASSSYSREG_IMPL
4040 #include "ARMGenSystemRegister.inc"
4141
42 }
43 }
42 } // end namespace ARMSysReg
43
44 namespace ARMBankedReg {
45 #define GET_BANKEDREG_IMPL
46 #include "ARMGenSystemRegister.inc"
47 } // end namespce ARMSysReg
48 } // end namespace llvm
2323
2424 namespace llvm {
2525
26 // System Registers
2627 namespace ARMSysReg {
2728 struct MClassSysReg {
2829 const char *Name;
5859
5960 } // end namespace ARMSysReg
6061
62 // Banked Registers
63 namespace ARMBankedReg {
64 struct BankedReg {
65 const char *Name;
66 uint16_t Encoding;
67 };
68 #define GET_BANKEDREG_DECL
69 #include "ARMGenSystemRegister.inc"
70 } // end namespace ARMBankedReg
71
6172 } // end namespace llvm
6273
6374 #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H