llvm.org GIT mirror llvm / 65c488a
[lanai] Manually match 0/-1 with R0/R1. Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel. Reviewers: eliben, majnemer Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27171 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288215 91177308-0d34-0410-b5e6-96231b3b80d8 Jacques Pienaar 2 years ago
3 changed file(s) with 26 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
281281 return;
282282 }
283283
284 // Instruction Selection not handled by the auto-generated
285 // tablegen selection should be handled here.
284 // Instruction Selection not handled by the auto-generated tablegen selection
285 // should be handled here.
286 EVT VT = Node->getValueType(0);
286287 switch (Opcode) {
288 case ISD::Constant:
289 if (VT == MVT::i32) {
290 ConstantSDNode *ConstNode = cast(Node);
291 // Materialize zero constants as copies from R0. This allows the coalescer
292 // to propagate these into other instructions.
293 if (ConstNode->isNullValue()) {
294 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
295 SDLoc(Node), Lanai::R0, MVT::i32);
296 return ReplaceNode(Node, New.getNode());
297 }
298 // Materialize all ones constants as copies from R1. This allows the
299 // coalescer to propagate these into other instructions.
300 if (ConstNode->isAllOnesValue()) {
301 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
302 SDLoc(Node), Lanai::R1, MVT::i32);
303 return ReplaceNode(Node, New.getNode());
304 }
305 }
306 break;
287307 case ISD::FrameIndex:
288308 selectFrameIndex(Node);
289309 return;
830830 // Non-Instruction Patterns
831831 //===----------------------------------------------------------------------===//
832832
833 // i32 0 and R0 can be used interchangeably.
834 def : Pat<(i32 0), (i32 R0)>;
835 // i32 -1 and R1 can be used interchangeably.
836 def : Pat<(i32 -1), (i32 R1)>;
837
838833 // unsigned 16-bit immediate
839834 def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>;
840835
8080 }
8181
8282 ; CHECK-LABEL: fm9:
83 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
84 ; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}}
85 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
83 ; CHECK: sub %r0, %r6, %r{{[0-9]+}}
84 ; CHECK: sh %r6, 0x3, %r9
85 ; CHECK: sub %r{{[0-9]+}}, %r9, %rv
8686 define i32 @fm9(i32 inreg %a) #0 {
8787 %1 = mul nsw i32 %a, -9
8888 ret i32 %1
8989 }
9090
9191 ; CHECK-LABEL: fm10:
92 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
9392 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
9493 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
94 ; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
9595 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
9696 define i32 @fm10(i32 inreg %a) #0 {
9797 %1 = mul nsw i32 %a, -10