llvm.org GIT mirror llvm / 655739d
Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133897 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 9 years ago
3 changed file(s) with 1523 addition(s) and 1541 deletion(s). Raw diff Collapse all Expand all
7878 ScoreboardHazardRecognizer.cpp
7979 ShadowStackGC.cpp
8080 ShrinkWrapping.cpp
81 SimpleRegisterCoalescing.cpp
8281 SjLjEHPrepare.cpp
8382 SlotIndexes.cpp
8483 Spiller.cpp
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #define DEBUG_TYPE "regcoalescing"
1516 #include "RegisterCoalescer.h"
17 #include "VirtRegMap.h"
18 #include "LiveDebugVariables.h"
19
20 #include "llvm/Pass.h"
21 #include "llvm/Value.h"
1622 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
1723 #include "llvm/CodeGen/MachineInstr.h"
1824 #include "llvm/CodeGen/MachineRegisterInfo.h"
1925 #include "llvm/Target/TargetInstrInfo.h"
2026 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Pass.h"
22
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/ADT/OwningPtr.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/STLExtras.h"
45 #include
46 #include
2347 using namespace llvm;
48
49 STATISTIC(numJoins , "Number of interval joins performed");
50 STATISTIC(numCrossRCs , "Number of cross class joins performed");
51 STATISTIC(numCommutes , "Number of instruction commuting performed");
52 STATISTIC(numExtends , "Number of copies extended");
53 STATISTIC(NumReMats , "Number of instructions re-materialized");
54 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
55 STATISTIC(numAborts , "Number of times interval joining aborted");
56
57 char SimpleRegisterCoalescing::ID = 0;
58 static cl::opt
59 EnableJoining("join-liveintervals",
60 cl::desc("Coalesce copies (default=true)"),
61 cl::init(true));
62
63 static cl::opt
64 DisableCrossClassJoin("disable-cross-class-join",
65 cl::desc("Avoid coalescing cross register class copies"),
66 cl::init(false), cl::Hidden);
67
68 static cl::opt
69 EnablePhysicalJoin("join-physregs",
70 cl::desc("Join physical register copies"),
71 cl::init(false), cl::Hidden);
72
73 static cl::opt
74 VerifyCoalescing("verify-coalescing",
75 cl::desc("Verify machine instrs before and after register coalescing"),
76 cl::Hidden);
77
78 INITIALIZE_AG_PASS_BEGIN(SimpleRegisterCoalescing, RegisterCoalescer,
79 "simple-register-coalescing", "Simple Register Coalescing",
80 false, false, true)
81 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
82 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
83 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
84 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
85 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
86 INITIALIZE_PASS_DEPENDENCY(PHIElimination)
87 INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
88 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
89 INITIALIZE_AG_PASS_END(SimpleRegisterCoalescing, RegisterCoalescer,
90 "simple-register-coalescing", "Simple Register Coalescing",
91 false, false, true)
92
93 char &llvm::SimpleRegisterCoalescingID = SimpleRegisterCoalescing::ID;
2494
2595 // Register the RegisterCoalescer interface, providing a nice name to refer to.
2696 INITIALIZE_ANALYSIS_GROUP(RegisterCoalescer, "Register Coalescer",
194264 // used, but the default implementation not being linked into the tool
195265 // that uses it.
196266 DEFINING_FILE_FOR(RegisterCoalescer)
267
268 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
269 AU.setPreservesCFG();
270 AU.addRequired();
271 AU.addRequired();
272 AU.addPreserved();
273 AU.addRequired();
274 AU.addPreserved();
275 AU.addPreserved();
276 AU.addRequired();
277 AU.addPreserved();
278 AU.addPreservedID(MachineDominatorsID);
279 AU.addPreservedID(StrongPHIEliminationID);
280 AU.addPreservedID(PHIEliminationID);
281 AU.addPreservedID(TwoAddressInstructionPassID);
282 MachineFunctionPass::getAnalysisUsage(AU);
283 }
284
285 void SimpleRegisterCoalescing::markAsJoined(MachineInstr *CopyMI) {
286 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
287 JoinedCopies.insert(CopyMI);
288
289 /// Mark all register operands of CopyMI as so they won't affect dead
290 /// code elimination.
291 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
292 E = CopyMI->operands_end(); I != E; ++I)
293 if (I->isReg())
294 I->setIsUndef(true);
295 }
296
297 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
298 /// being the source and IntB being the dest, thus this defines a value number
299 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
300 /// see if we can merge these two pieces of B into a single value number,
301 /// eliminating a copy. For example:
302 ///
303 /// A3 = B0
304 /// ...
305 /// B1 = A3 <- this copy
306 ///
307 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
308 /// value number to be replaced with B0 (which simplifies the B liveinterval).
309 ///
310 /// This returns true if an interval was modified.
311 ///
312 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
313 MachineInstr *CopyMI) {
314 // Bail if there is no dst interval - can happen when merging physical subreg
315 // operations.
316 if (!li_->hasInterval(CP.getDstReg()))
317 return false;
318
319 LiveInterval &IntA =
320 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
321 LiveInterval &IntB =
322 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
323 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
324
325 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
326 // the example above.
327 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
328 if (BLR == IntB.end()) return false;
329 VNInfo *BValNo = BLR->valno;
330
331 // Get the location that B is defined at. Two options: either this value has
332 // an unknown definition point or it is defined at CopyIdx. If unknown, we
333 // can't process it.
334 if (!BValNo->isDefByCopy()) return false;
335 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
336
337 // AValNo is the value number in A that defines the copy, A3 in the example.
338 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
339 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
340 // The live range might not exist after fun with physreg coalescing.
341 if (ALR == IntA.end()) return false;
342 VNInfo *AValNo = ALR->valno;
343 // If it's re-defined by an early clobber somewhere in the live range, then
344 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
345 // See PR3149:
346 // 172 %ECX = MOV32rr %reg1039
347 // 180 INLINEASM
348 // sbbl $3,$0>, 10, %EAX, 14, %ECX, 9,
349 // %EAX,
350 // 36, , 1, %reg0, 0, 9, %ECX, 36, , 1, %reg0, 0
351 // 188 %EAX = MOV32rr %EAX
352 // 196 %ECX = MOV32rr %ECX
353 // 204 %ECX = MOV32rr %ECX
354 // 212 %EAX = MOV32rr %EAX
355 // 220 %EAX = MOV32rr %EAX
356 // 228 %reg1039 = MOV32rr %ECX
357 // The early clobber operand ties ECX input to the ECX def.
358 //
359 // The live interval of ECX is represented as this:
360 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
361 // The coalescer has no idea there was a def in the middle of [174,230].
362 if (AValNo->hasRedefByEC())
363 return false;
364
365 // If AValNo is defined as a copy from IntB, we can potentially process this.
366 // Get the instruction that defines this value number.
367 if (!CP.isCoalescable(AValNo->getCopy()))
368 return false;
369
370 // Get the LiveRange in IntB that this value number starts with.
371 LiveInterval::iterator ValLR =
372 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
373 if (ValLR == IntB.end())
374 return false;
375
376 // Make sure that the end of the live range is inside the same block as
377 // CopyMI.
378 MachineInstr *ValLREndInst =
379 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
380 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
381 return false;
382
383 // Okay, we now know that ValLR ends in the same block that the CopyMI
384 // live-range starts. If there are no intervening live ranges between them in
385 // IntB, we can merge them.
386 if (ValLR+1 != BLR) return false;
387
388 // If a live interval is a physical register, conservatively check if any
389 // of its aliases is overlapping the live interval of the virtual register.
390 // If so, do not coalesce.
391 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
392 for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS)
393 if (li_->hasInterval(*AS) && IntA.overlaps(li_->getInterval(*AS))) {
394 DEBUG({
395 dbgs() << "\t\tInterfere with alias ";
396 li_->getInterval(*AS).print(dbgs(), tri_);
397 });
398 return false;
399 }
400 }
401
402 DEBUG({
403 dbgs() << "Extending: ";
404 IntB.print(dbgs(), tri_);
405 });
406
407 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
408 // We are about to delete CopyMI, so need to remove it as the 'instruction
409 // that defines this value #'. Update the valnum with the new defining
410 // instruction #.
411 BValNo->def = FillerStart;
412 BValNo->setCopy(0);
413
414 // Okay, we can merge them. We need to insert a new liverange:
415 // [ValLR.end, BLR.begin) of either value number, then we merge the
416 // two value numbers.
417 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
418
419 // If the IntB live range is assigned to a physical register, and if that
420 // physreg has sub-registers, update their live intervals as well.
421 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
422 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
423 if (!li_->hasInterval(*SR))
424 continue;
425 LiveInterval &SRLI = li_->getInterval(*SR);
426 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
427 SRLI.getNextValue(FillerStart, 0,
428 li_->getVNInfoAllocator())));
429 }
430 }
431
432 // Okay, merge "B1" into the same value number as "B0".
433 if (BValNo != ValLR->valno) {
434 // If B1 is killed by a PHI, then the merged live range must also be killed
435 // by the same PHI, as B0 and B1 can not overlap.
436 bool HasPHIKill = BValNo->hasPHIKill();
437 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
438 if (HasPHIKill)
439 ValLR->valno->setHasPHIKill(true);
440 }
441 DEBUG({
442 dbgs() << " result = ";
443 IntB.print(dbgs(), tri_);
444 dbgs() << "\n";
445 });
446
447 // If the source instruction was killing the source register before the
448 // merge, unset the isKill marker given the live range has been extended.
449 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
450 if (UIdx != -1) {
451 ValLREndInst->getOperand(UIdx).setIsKill(false);
452 }
453
454 // If the copy instruction was killing the destination register before the
455 // merge, find the last use and trim the live range. That will also add the
456 // isKill marker.
457 if (ALR->end == CopyIdx)
458 li_->shrinkToUses(&IntA);
459
460 ++numExtends;
461 return true;
462 }
463
464 /// HasOtherReachingDefs - Return true if there are definitions of IntB
465 /// other than BValNo val# that can reach uses of AValno val# of IntA.
466 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
467 LiveInterval &IntB,
468 VNInfo *AValNo,
469 VNInfo *BValNo) {
470 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
471 AI != AE; ++AI) {
472 if (AI->valno != AValNo) continue;
473 LiveInterval::Ranges::iterator BI =
474 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
475 if (BI != IntB.ranges.begin())
476 --BI;
477 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
478 if (BI->valno == BValNo)
479 continue;
480 if (BI->start <= AI->start && BI->end > AI->start)
481 return true;
482 if (BI->start > AI->start && BI->start < AI->end)
483 return true;
484 }
485 }
486 return false;
487 }
488
489 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
490 /// IntA being the source and IntB being the dest, thus this defines a value
491 /// number in IntB. If the source value number (in IntA) is defined by a
492 /// commutable instruction and its other operand is coalesced to the copy dest
493 /// register, see if we can transform the copy into a noop by commuting the
494 /// definition. For example,
495 ///
496 /// A3 = op A2 B0
497 /// ...
498 /// B1 = A3 <- this copy
499 /// ...
500 /// = op A3 <- more uses
501 ///
502 /// ==>
503 ///
504 /// B2 = op B0 A2
505 /// ...
506 /// B1 = B2 <- now an identify copy
507 /// ...
508 /// = op B2 <- more uses
509 ///
510 /// This returns true if an interval was modified.
511 ///
512 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
513 MachineInstr *CopyMI) {
514 // FIXME: For now, only eliminate the copy by commuting its def when the
515 // source register is a virtual register. We want to guard against cases
516 // where the copy is a back edge copy and commuting the def lengthen the
517 // live interval of the source register to the entire loop.
518 if (CP.isPhys() && CP.isFlipped())
519 return false;
520
521 // Bail if there is no dst interval.
522 if (!li_->hasInterval(CP.getDstReg()))
523 return false;
524
525 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
526
527 LiveInterval &IntA =
528 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
529 LiveInterval &IntB =
530 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
531
532 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
533 // the example above.
534 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
535 if (!BValNo || !BValNo->isDefByCopy())
536 return false;
537
538 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
539
540 // AValNo is the value number in A that defines the copy, A3 in the example.
541 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getUseIndex());
542 assert(AValNo && "COPY source not live");
543
544 // If other defs can reach uses of this def, then it's not safe to perform
545 // the optimization.
546 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
547 return false;
548 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
549 if (!DefMI)
550 return false;
551 const TargetInstrDesc &TID = DefMI->getDesc();
552 if (!TID.isCommutable())
553 return false;
554 // If DefMI is a two-address instruction then commuting it will change the
555 // destination register.
556 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
557 assert(DefIdx != -1);
558 unsigned UseOpIdx;
559 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
560 return false;
561 unsigned Op1, Op2, NewDstIdx;
562 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
563 return false;
564 if (Op1 == UseOpIdx)
565 NewDstIdx = Op2;
566 else if (Op2 == UseOpIdx)
567 NewDstIdx = Op1;
568 else
569 return false;
570
571 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
572 unsigned NewReg = NewDstMO.getReg();
573 if (NewReg != IntB.reg || !NewDstMO.isKill())
574 return false;
575
576 // Make sure there are no other definitions of IntB that would reach the
577 // uses which the new definition can reach.
578 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
579 return false;
580
581 // Abort if the aliases of IntB.reg have values that are not simply the
582 // clobbers from the superreg.
583 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
584 for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS)
585 if (li_->hasInterval(*AS) &&
586 HasOtherReachingDefs(IntA, li_->getInterval(*AS), AValNo, 0))
587 return false;
588
589 // If some of the uses of IntA.reg is already coalesced away, return false.
590 // It's not possible to determine whether it's safe to perform the coalescing.
591 for (MachineRegisterInfo::use_nodbg_iterator UI =
592 mri_->use_nodbg_begin(IntA.reg),
593 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
594 MachineInstr *UseMI = &*UI;
595 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
596 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
597 if (ULR == IntA.end())
598 continue;
599 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
600 return false;
601 }
602
603 DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t'
604 << *DefMI);
605
606 // At this point we have decided that it is legal to do this
607 // transformation. Start by commuting the instruction.
608 MachineBasicBlock *MBB = DefMI->getParent();
609 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
610 if (!NewMI)
611 return false;
612 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
613 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
614 !mri_->constrainRegClass(IntB.reg, mri_->getRegClass(IntA.reg)))
615 return false;
616 if (NewMI != DefMI) {
617 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
618 MBB->insert(DefMI, NewMI);
619 MBB->erase(DefMI);
620 }
621 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
622 NewMI->getOperand(OpIdx).setIsKill();
623
624 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
625 // A = or A, B
626 // ...
627 // B = A
628 // ...
629 // C = A
630 // ...
631 // = B
632
633 // Update uses of IntA of the specific Val# with IntB.
634 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
635 UE = mri_->use_end(); UI != UE;) {
636 MachineOperand &UseMO = UI.getOperand();
637 MachineInstr *UseMI = &*UI;
638 ++UI;
639 if (JoinedCopies.count(UseMI))
640 continue;
641 if (UseMI->isDebugValue()) {
642 // FIXME These don't have an instruction index. Not clear we have enough
643 // info to decide whether to do this replacement or not. For now do it.
644 UseMO.setReg(NewReg);
645 continue;
646 }
647 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
648 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
649 if (ULR == IntA.end() || ULR->valno != AValNo)
650 continue;
651 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
652 UseMO.substPhysReg(NewReg, *tri_);
653 else
654 UseMO.setReg(NewReg);
655 if (UseMI == CopyMI)
656 continue;
657 if (!UseMI->isCopy())
658 continue;
659 if (UseMI->getOperand(0).getReg() != IntB.reg ||
660 UseMI->getOperand(0).getSubReg())
661 continue;
662
663 // This copy will become a noop. If it's defining a new val#, merge it into
664 // BValNo.
665 SlotIndex DefIdx = UseIdx.getDefIndex();
666 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
667 if (!DVNI)
668 continue;
669 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
670 assert(DVNI->def == DefIdx);
671 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
672 markAsJoined(UseMI);
673 }
674
675 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
676 // is updated.
677 VNInfo *ValNo = BValNo;
678 ValNo->def = AValNo->def;
679 ValNo->setCopy(0);
680 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
681 AI != AE; ++AI) {
682 if (AI->valno != AValNo) continue;
683 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
684 }
685 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
686
687 IntA.removeValNo(AValNo);
688 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
689 ++numCommutes;
690 return true;
691 }
692
693 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
694 /// computation, replace the copy by rematerialize the definition.
695 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
696 bool preserveSrcInt,
697 unsigned DstReg,
698 unsigned DstSubIdx,
699 MachineInstr *CopyMI) {
700 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
701 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
702 assert(SrcLR != SrcInt.end() && "Live range not found!");
703 VNInfo *ValNo = SrcLR->valno;
704 // If other defs can reach uses of this def, then it's not safe to perform
705 // the optimization.
706 if (ValNo->isPHIDef() || ValNo->isUnused() || ValNo->hasPHIKill())
707 return false;
708 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
709 if (!DefMI)
710 return false;
711 assert(DefMI && "Defining instruction disappeared");
712 const TargetInstrDesc &TID = DefMI->getDesc();
713 if (!TID.isAsCheapAsAMove())
714 return false;
715 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
716 return false;
717 bool SawStore = false;
718 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
719 return false;
720 if (TID.getNumDefs() != 1)
721 return false;
722 if (!DefMI->isImplicitDef()) {
723 // Make sure the copy destination register class fits the instruction
724 // definition register class. The mismatch can happen as a result of earlier
725 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
726 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
727 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
728 if (mri_->getRegClass(DstReg) != RC)
729 return false;
730 } else if (!RC->contains(DstReg))
731 return false;
732 }
733
734 // If destination register has a sub-register index on it, make sure it
735 // matches the instruction register class.
736 if (DstSubIdx) {
737 const TargetInstrDesc &TID = DefMI->getDesc();
738 if (TID.getNumDefs() != 1)
739 return false;
740 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
741 const TargetRegisterClass *DstSubRC =
742 DstRC->getSubRegisterRegClass(DstSubIdx);
743 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
744 if (DefRC == DstRC)
745 DstSubIdx = 0;
746 else if (DefRC != DstSubRC)
747 return false;
748 }
749
750 RemoveCopyFlag(DstReg, CopyMI);
751
752 MachineBasicBlock *MBB = CopyMI->getParent();
753 MachineBasicBlock::iterator MII =
754 llvm::next(MachineBasicBlock::iterator(CopyMI));
755 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
756 MachineInstr *NewMI = prior(MII);
757
758 // CopyMI may have implicit operands, transfer them over to the newly
759 // rematerialized instruction. And update implicit def interval valnos.
760 for (unsigned i = CopyMI->getDesc().getNumOperands(),
761 e = CopyMI->getNumOperands(); i != e; ++i) {
762 MachineOperand &MO = CopyMI->getOperand(i);
763 if (MO.isReg() && MO.isImplicit())
764 NewMI->addOperand(MO);
765 if (MO.isDef())
766 RemoveCopyFlag(MO.getReg(), CopyMI);
767 }
768
769 NewMI->copyImplicitOps(CopyMI);
770 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
771 CopyMI->eraseFromParent();
772 ReMatCopies.insert(CopyMI);
773 ReMatDefs.insert(DefMI);
774 DEBUG(dbgs() << "Remat: " << *NewMI);
775 ++NumReMats;
776
777 // The source interval can become smaller because we removed a use.
778 if (preserveSrcInt)
779 li_->shrinkToUses(&SrcInt);
780
781 return true;
782 }
783
784 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
785 /// update the subregister number if it is not zero. If DstReg is a
786 /// physical register and the existing subregister number of the def / use
787 /// being updated is not zero, make sure to set it to the correct physical
788 /// subregister.
789 void
790 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
791 bool DstIsPhys = CP.isPhys();
792 unsigned SrcReg = CP.getSrcReg();
793 unsigned DstReg = CP.getDstReg();
794 unsigned SubIdx = CP.getSubIdx();
795
796 // Update LiveDebugVariables.
797 ldv_->renameRegister(SrcReg, DstReg, SubIdx);
798
799 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
800 MachineInstr *UseMI = I.skipInstruction();) {
801 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
802 // instead.
803 if (DstIsPhys) {
804 if (UseMI->isCopy() &&
805 !UseMI->getOperand(1).getSubReg() &&
806 !UseMI->getOperand(0).getSubReg() &&
807 UseMI->getOperand(1).getReg() == SrcReg &&
808 UseMI->getOperand(0).getReg() != SrcReg &&
809 UseMI->getOperand(0).getReg() != DstReg &&
810 !JoinedCopies.count(UseMI) &&
811 ReMaterializeTrivialDef(li_->getInterval(SrcReg), false,
812 UseMI->getOperand(0).getReg(), 0, UseMI))
813 continue;
814 }
815
816 SmallVector Ops;
817 bool Reads, Writes;
818 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
819 bool Kills = false, Deads = false;
820
821 // Replace SrcReg with DstReg in all UseMI operands.
822 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
823 MachineOperand &MO = UseMI->getOperand(Ops[i]);
824 Kills |= MO.isKill();
825 Deads |= MO.isDead();
826
827 if (DstIsPhys)
828 MO.substPhysReg(DstReg, *tri_);
829 else
830 MO.substVirtReg(DstReg, SubIdx, *tri_);
831 }
832
833 // This instruction is a copy that will be removed.
834 if (JoinedCopies.count(UseMI))
835 continue;
836
837 if (SubIdx) {
838 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
839 // read-modify-write of DstReg.
840 if (Deads)
841 UseMI->addRegisterDead(DstReg, tri_);
842 else if (!Reads && Writes)
843 UseMI->addRegisterDefined(DstReg, tri_);
844
845 // Kill flags apply to the whole physical register.
846 if (DstIsPhys && Kills)
847 UseMI->addRegisterKilled(DstReg, tri_);
848 }
849
850 DEBUG({
851 dbgs() << "\t\tupdated: ";
852 if (!UseMI->isDebugValue())
853 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
854 dbgs() << *UseMI;
855 });
856 }
857 }
858
859 /// removeIntervalIfEmpty - Check if the live interval of a physical register
860 /// is empty, if so remove it and also remove the empty intervals of its
861 /// sub-registers. Return true if live interval is removed.
862 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
863 const TargetRegisterInfo *tri_) {
864 if (li.empty()) {
865 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
866 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
867 if (!li_->hasInterval(*SR))
868 continue;
869 LiveInterval &sli = li_->getInterval(*SR);
870 if (sli.empty())
871 li_->removeInterval(*SR);
872 }
873 li_->removeInterval(li.reg);
874 return true;
875 }
876 return false;
877 }
878
879 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
880 /// the val# it defines. If the live interval becomes empty, remove it as well.
881 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
882 MachineInstr *DefMI) {
883 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
884 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
885 if (DefIdx != MLR->valno->def)
886 return false;
887 li.removeValNo(MLR->valno);
888 return removeIntervalIfEmpty(li, li_, tri_);
889 }
890
891 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
892 const MachineInstr *CopyMI) {
893 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
894 if (li_->hasInterval(DstReg)) {
895 LiveInterval &LI = li_->getInterval(DstReg);
896 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
897 if (LR->valno->def == DefIdx)
898 LR->valno->setCopy(0);
899 }
900 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
901 return;
902 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
903 if (!li_->hasInterval(*AS))
904 continue;
905 LiveInterval &LI = li_->getInterval(*AS);
906 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
907 if (LR->valno->def == DefIdx)
908 LR->valno->setCopy(0);
909 }
910 }
911
912 /// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
913 /// We need to be careful about coalescing a source physical register with a
914 /// virtual register. Once the coalescing is done, it cannot be broken and these
915 /// are not spillable! If the destination interval uses are far away, think
916 /// twice about coalescing them!
917 bool SimpleRegisterCoalescing::shouldJoinPhys(CoalescerPair &CP) {
918 bool Allocatable = li_->isAllocatable(CP.getDstReg());
919 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
920
921 /// Always join simple intervals that are defined by a single copy from a
922 /// reserved register. This doesn't increase register pressure, so it is
923 /// always beneficial.
924 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
925 return true;
926
927 if (!EnablePhysicalJoin) {
928 DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
929 return false;
930 }
931
932 // Only coalesce to allocatable physreg, we don't want to risk modifying
933 // reserved registers.
934 if (!Allocatable) {
935 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
936 return false; // Not coalescable.
937 }
938
939 // Don't join with physregs that have a ridiculous number of live
940 // ranges. The data structure performance is really bad when that
941 // happens.
942 if (li_->hasInterval(CP.getDstReg()) &&
943 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
944 ++numAborts;
945 DEBUG(dbgs()
946 << "\tPhysical register live interval too complicated, abort!\n");
947 return false;
948 }
949
950 // FIXME: Why are we skipping this test for partial copies?
951 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
952 if (!CP.isPartial()) {
953 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
954 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
955 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
956 if (Length > Threshold) {
957 ++numAborts;
958 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
959 return false;
960 }
961 }
962 return true;
963 }
964
965 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
966 /// two virtual registers from different register classes.
967 bool
968 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
969 unsigned DstReg,
970 const TargetRegisterClass *SrcRC,
971 const TargetRegisterClass *DstRC,
972 const TargetRegisterClass *NewRC) {
973 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
974 // This heuristics is good enough in practice, but it's obviously not *right*.
975 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
976 // out all but the most restrictive register classes.
977 if (NewRCCount > 4 ||
978 // Early exit if the function is fairly small, coalesce aggressively if
979 // that's the case. For really special register classes with 3 or
980 // fewer registers, be a bit more careful.
981 (li_->getFuncInstructionCount() / NewRCCount) < 8)
982 return true;
983 LiveInterval &SrcInt = li_->getInterval(SrcReg);
984 LiveInterval &DstInt = li_->getInterval(DstReg);
985 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
986 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
987
988 // Coalesce aggressively if the intervals are small compared to the number of
989 // registers in the new class. The number 4 is fairly arbitrary, chosen to be
990 // less aggressive than the 8 used for the whole function size.
991 const unsigned ThresSize = 4 * NewRCCount;
992 if (SrcSize <= ThresSize && DstSize <= ThresSize)
993 return true;
994
995 // Estimate *register use density*. If it doubles or more, abort.
996 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
997 mri_->use_nodbg_end());
998 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
999 mri_->use_nodbg_end());
1000 unsigned NewUses = SrcUses + DstUses;
1001 unsigned NewSize = SrcSize + DstSize;
1002 if (SrcRC != NewRC && SrcSize > ThresSize) {
1003 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
1004 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1005 return false;
1006 }
1007 if (DstRC != NewRC && DstSize > ThresSize) {
1008 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1009 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1010 return false;
1011 }
1012 return true;
1013 }
1014
1015
1016 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1017 /// which are the src/dst of the copy instruction CopyMI. This returns true
1018 /// if the copy was successfully coalesced away. If it is not currently
1019 /// possible to coalesce this interval, but it may be possible if other
1020 /// things get coalesced, then it returns true by reference in 'Again'.
1021 bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI, bool &Again) {
1022
1023 Again = false;
1024 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1025 return false; // Already done.
1026
1027 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1028
1029 CoalescerPair CP(*tii_, *tri_);
1030 if (!CP.setRegisters(CopyMI)) {
1031 DEBUG(dbgs() << "\tNot coalescable.\n");
1032 return false;
1033 }
1034
1035 // If they are already joined we continue.
1036 if (CP.getSrcReg() == CP.getDstReg()) {
1037 markAsJoined(CopyMI);
1038 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1039 return false; // Not coalescable.
1040 }
1041
1042 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_)
1043 << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx())
1044 << "\n");
1045
1046 // Enforce policies.
1047 if (CP.isPhys()) {
1048 if (!shouldJoinPhys(CP)) {
1049 // Before giving up coalescing, if definition of source is defined by
1050 // trivial computation, try rematerializing it.
1051 if (!CP.isFlipped() &&
1052 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), true,
1053 CP.getDstReg(), 0, CopyMI))
1054 return true;
1055 return false;
1056 }
1057 } else {
1058 // Avoid constraining virtual register regclass too much.
1059 if (CP.isCrossClass()) {
1060 DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
1061 if (DisableCrossClassJoin) {
1062 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1063 return false;
1064 }
1065 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1066 mri_->getRegClass(CP.getSrcReg()),
1067 mri_->getRegClass(CP.getDstReg()),
1068 CP.getNewRC())) {
1069 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
1070 Again = true; // May be possible to coalesce later.
1071 return false;
1072 }
1073 }
1074
1075 // When possible, let DstReg be the larger interval.
1076 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
1077 li_->getInterval(CP.getDstReg()).ranges.size())
1078 CP.flip();
1079 }
1080
1081 // Okay, attempt to join these two intervals. On failure, this returns false.
1082 // Otherwise, if one of the intervals being joined is a physreg, this method
1083 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1084 // been modified, so we can use this information below to update aliases.
1085 if (!JoinIntervals(CP)) {
1086 // Coalescing failed.
1087
1088 // If definition of source is defined by trivial computation, try
1089 // rematerializing it.
1090 if (!CP.isFlipped() &&
1091 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), true,
1092 CP.getDstReg(), 0, CopyMI))
1093 return true;
1094
1095 // If we can eliminate the copy without merging the live ranges, do so now.
1096 if (!CP.isPartial()) {
1097 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1098 RemoveCopyByCommutingDef(CP, CopyMI)) {
1099 markAsJoined(CopyMI);
1100 DEBUG(dbgs() << "\tTrivial!\n");
1101 return true;
1102 }
1103 }
1104
1105 // Otherwise, we are unable to join the intervals.
1106 DEBUG(dbgs() << "\tInterference!\n");
1107 Again = true; // May be possible to coalesce later.
1108 return false;
1109 }
1110
1111 // Coalescing to a virtual register that is of a sub-register class of the
1112 // other. Make sure the resulting register is set to the right register class.
1113 if (CP.isCrossClass()) {
1114 ++numCrossRCs;
1115 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
1116 }
1117
1118 // Remember to delete the copy instruction.
1119 markAsJoined(CopyMI);
1120
1121 UpdateRegDefsUses(CP);
1122
1123 // If we have extended the live range of a physical register, make sure we
1124 // update live-in lists as well.
1125 if (CP.isPhys()) {
1126 SmallVector BlockSeq;
1127 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1128 // ranges for this, and they are preserved.
1129 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
1130 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1131 I != E; ++I ) {
1132 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1133 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1134 MachineBasicBlock &block = *BlockSeq[idx];
1135 if (!block.isLiveIn(CP.getDstReg()))
1136 block.addLiveIn(CP.getDstReg());
1137 }
1138 BlockSeq.clear();
1139 }
1140 }
1141
1142 // SrcReg is guarateed to be the register whose live interval that is
1143 // being merged.
1144 li_->removeInterval(CP.getSrcReg());
1145
1146 // Update regalloc hint.
1147 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
1148
1149 DEBUG({
1150 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
1151 dbgs() << "\tJoined. Result = ";
1152 DstInt.print(dbgs(), tri_);
1153 dbgs() << "\n";
1154 });
1155
1156 ++numJoins;
1157 return true;
1158 }
1159
1160 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1161 /// compute what the resultant value numbers for each value in the input two
1162 /// ranges will be. This is complicated by copies between the two which can
1163 /// and will commonly cause multiple value numbers to be merged into one.
1164 ///
1165 /// VN is the value number that we're trying to resolve. InstDefiningValue
1166 /// keeps track of the new InstDefiningValue assignment for the result
1167 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1168 /// whether a value in this or other is a copy from the opposite set.
1169 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1170 /// already been assigned.
1171 ///
1172 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1173 /// contains the value number the copy is from.
1174 ///
1175 static unsigned ComputeUltimateVN(VNInfo *VNI,
1176 SmallVector &NewVNInfo,
1177 DenseMap &ThisFromOther,
1178 DenseMap &OtherFromThis,
1179 SmallVector &ThisValNoAssignments,
1180 SmallVector &OtherValNoAssignments) {
1181 unsigned VN = VNI->id;
1182
1183 // If the VN has already been computed, just return it.
1184 if (ThisValNoAssignments[VN] >= 0)
1185 return ThisValNoAssignments[VN];
1186 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1187
1188 // If this val is not a copy from the other val, then it must be a new value
1189 // number in the destination.
1190 DenseMap::iterator I = ThisFromOther.find(VNI);
1191 if (I == ThisFromOther.end()) {
1192 NewVNInfo.push_back(VNI);
1193 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1194 }
1195 VNInfo *OtherValNo = I->second;
1196
1197 // Otherwise, this *is* a copy from the RHS. If the other side has already
1198 // been computed, return it.
1199 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1200 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1201
1202 // Mark this value number as currently being computed, then ask what the
1203 // ultimate value # of the other value is.
1204 ThisValNoAssignments[VN] = -2;
1205 unsigned UltimateVN =
1206 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1207 OtherValNoAssignments, ThisValNoAssignments);
1208 return ThisValNoAssignments[VN] = UltimateVN;
1209 }
1210
1211 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1212 /// returns false.
1213 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1214 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1215 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1216
1217 // If a live interval is a physical register, check for interference with any
1218 // aliases. The interference check implemented here is a bit more conservative
1219 // than the full interfeence check below. We allow overlapping live ranges
1220 // only when one is a copy of the other.
1221 if (CP.isPhys()) {
1222 for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
1223 if (!li_->hasInterval(*AS))
1224 continue;
1225 const LiveInterval &LHS = li_->getInterval(*AS);
1226 LiveInterval::const_iterator LI = LHS.begin();
1227 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1228 RI != RE; ++RI) {
1229 LI = std::lower_bound(LI, LHS.end(), RI->start);
1230 // Does LHS have an overlapping live range starting before RI?
1231 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1232 (RI->start != RI->valno->def ||
1233 !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
1234 DEBUG({
1235 dbgs() << "\t\tInterference from alias: ";
1236 LHS.print(dbgs(), tri_);
1237 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1238 });
1239 return false;
1240 }
1241
1242 // Check that LHS ranges beginning in this range are copies.
1243 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1244 if (LI->start != LI->valno->def ||
1245 !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
1246 DEBUG({
1247 dbgs() << "\t\tInterference from alias: ";
1248 LHS.print(dbgs(), tri_);
1249 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1250 });
1251 return false;
1252 }
1253 }
1254 }
1255 }
1256 }
1257
1258 // Compute the final value assignment, assuming that the live ranges can be
1259 // coalesced.
1260 SmallVector LHSValNoAssignments;
1261 SmallVector RHSValNoAssignments;
1262 DenseMap LHSValsDefinedFromRHS;
1263 DenseMap RHSValsDefinedFromLHS;
1264 SmallVector NewVNInfo;
1265
1266 LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
1267 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
1268
1269 // Loop over the value numbers of the LHS, seeing if any are defined from
1270 // the RHS.
1271 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1272 i != e; ++i) {
1273 VNInfo *VNI = *i;
1274 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1275 continue;
1276
1277 // Never join with a register that has EarlyClobber redefs.
1278 if (VNI->hasRedefByEC())
1279 return false;
1280
1281 // DstReg is known to be a register in the LHS interval. If the src is
1282 // from the RHS interval, we can use its value #.
1283 if (!CP.isCoalescable(VNI->getCopy()))
1284 continue;
1285
1286 // Figure out the value # from the RHS.
1287 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1288 // The copy could be to an aliased physreg.
1289 if (!lr) continue;
1290 LHSValsDefinedFromRHS[VNI] = lr->valno;
1291 }
1292
1293 // Loop over the value numbers of the RHS, seeing if any are defined from
1294 // the LHS.
1295 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1296 i != e; ++i) {
1297 VNInfo *VNI = *i;
1298 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1299 continue;
1300
1301 // Never join with a register that has EarlyClobber redefs.
1302 if (VNI->hasRedefByEC())
1303 return false;
1304
1305 // DstReg is known to be a register in the RHS interval. If the src is
1306 // from the LHS interval, we can use its value #.
1307 if (!CP.isCoalescable(VNI->getCopy()))
1308 continue;
1309
1310 // Figure out the value # from the LHS.
1311 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1312 // The copy could be to an aliased physreg.
1313 if (!lr) continue;
1314 RHSValsDefinedFromLHS[VNI] = lr->valno;
1315 }
1316
1317 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1318 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1319 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1320
1321 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1322 i != e; ++i) {
1323 VNInfo *VNI = *i;
1324 unsigned VN = VNI->id;
1325 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1326 continue;
1327 ComputeUltimateVN(VNI, NewVNInfo,
1328 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1329 LHSValNoAssignments, RHSValNoAssignments);
1330 }
1331 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1332 i != e; ++i) {
1333 VNInfo *VNI = *i;
1334 unsigned VN = VNI->id;
1335 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1336 continue;
1337 // If this value number isn't a copy from the LHS, it's a new number.
1338 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1339 NewVNInfo.push_back(VNI);
1340 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1341 continue;
1342 }
1343
1344 ComputeUltimateVN(VNI, NewVNInfo,
1345 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1346 RHSValNoAssignments, LHSValNoAssignments);
1347 }
1348
1349 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1350 // interval lists to see if these intervals are coalescable.
1351 LiveInterval::const_iterator I = LHS.begin();
1352 LiveInterval::const_iterator IE = LHS.end();
1353 LiveInterval::const_iterator J = RHS.begin();
1354 LiveInterval::const_iterator JE = RHS.end();
1355
1356 // Skip ahead until the first place of potential sharing.
1357 if (I != IE && J != JE) {
1358 if (I->start < J->start) {
1359 I = std::upper_bound(I, IE, J->start);
1360 if (I != LHS.begin()) --I;
1361 } else if (J->start < I->start) {
1362 J = std::upper_bound(J, JE, I->start);
1363 if (J != RHS.begin()) --J;
1364 }
1365 }
1366
1367 while (I != IE && J != JE) {
1368 // Determine if these two live ranges overlap.
1369 bool Overlaps;
1370 if (I->start < J->start) {
1371 Overlaps = I->end > J->start;
1372 } else {
1373 Overlaps = J->end > I->start;
1374 }
1375
1376 // If so, check value # info to determine if they are really different.
1377 if (Overlaps) {
1378 // If the live range overlap will map to the same value number in the
1379 // result liverange, we can still coalesce them. If not, we can't.
1380 if (LHSValNoAssignments[I->valno->id] !=
1381 RHSValNoAssignments[J->valno->id])
1382 return false;
1383 // If it's re-defined by an early clobber somewhere in the live range,
1384 // then conservatively abort coalescing.
1385 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1386 return false;
1387 }
1388
1389 if (I->end < J->end)
1390 ++I;
1391 else
1392 ++J;
1393 }
1394
1395 // Update kill info. Some live ranges are extended due to copy coalescing.
1396 for (DenseMap::iterator I = LHSValsDefinedFromRHS.begin(),
1397 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1398 VNInfo *VNI = I->first;
1399 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1400 if (VNI->hasPHIKill())
1401 NewVNInfo[LHSValID]->setHasPHIKill(true);
1402 }
1403
1404 // Update kill info. Some live ranges are extended due to copy coalescing.
1405 for (DenseMap::iterator I = RHSValsDefinedFromLHS.begin(),
1406 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1407 VNInfo *VNI = I->first;
1408 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1409 if (VNI->hasPHIKill())
1410 NewVNInfo[RHSValID]->setHasPHIKill(true);
1411 }
1412
1413 if (LHSValNoAssignments.empty())
1414 LHSValNoAssignments.push_back(-1);
1415 if (RHSValNoAssignments.empty())
1416 RHSValNoAssignments.push_back(-1);
1417
1418 // If we get here, we know that we can coalesce the live ranges. Ask the
1419 // intervals to coalesce themselves now.
1420 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1421 mri_);
1422 return true;
1423 }
1424
1425 namespace {
1426 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1427 // depth of the basic block (the unsigned), and then on the MBB number.
1428 struct DepthMBBCompare {
1429 typedef std::pair DepthMBBPair;
1430 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1431 // Deeper loops first
1432 if (LHS.first != RHS.first)
1433 return LHS.first > RHS.first;
1434
1435 // Prefer blocks that are more connected in the CFG. This takes care of
1436 // the most difficult copies first while intervals are short.
1437 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1438 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1439 if (cl != cr)
1440 return cl > cr;
1441
1442 // As a last resort, sort by block number.
1443 return LHS.second->getNumber() < RHS.second->getNumber();
1444 }
1445 };
1446 }
1447
1448 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1449 std::vector &TryAgain) {
1450 DEBUG(dbgs() << MBB->getName() << ":\n");
1451
1452 SmallVector VirtCopies;
1453 SmallVector PhysCopies;
1454 SmallVector ImpDefCopies;
1455 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1456 MII != E;) {
1457 MachineInstr *Inst = MII++;
1458
1459 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1460 unsigned SrcReg, DstReg;
1461 if (Inst->isCopy()) {
1462 DstReg = Inst->getOperand(0).getReg();
1463 SrcReg = Inst->getOperand(1).getReg();
1464 } else if (Inst->isSubregToReg()) {
1465 DstReg = Inst->getOperand(0).getReg();
1466 SrcReg = Inst->getOperand(2).getReg();
1467 } else
1468 continue;
1469
1470 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1471 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1472 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1473 ImpDefCopies.push_back(Inst);
1474 else if (SrcIsPhys || DstIsPhys)
1475 PhysCopies.push_back(Inst);
1476 else
1477 VirtCopies.push_back(Inst);
1478 }
1479
1480 // Try coalescing implicit copies and insert_subreg first,
1481 // followed by copies to / from physical registers, then finally copies
1482 // from virtual registers to virtual registers.
1483 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1484 MachineInstr *TheCopy = ImpDefCopies[i];
1485 bool Again = false;
1486 if (!JoinCopy(TheCopy, Again))
1487 if (Again)
1488 TryAgain.push_back(TheCopy);
1489 }
1490 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1491 MachineInstr *TheCopy = PhysCopies[i];
1492 bool Again = false;
1493 if (!JoinCopy(TheCopy, Again))
1494 if (Again)
1495 TryAgain.push_back(TheCopy);
1496 }
1497 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1498 MachineInstr *TheCopy = VirtCopies[i];
1499 bool Again = false;
1500 if (!JoinCopy(TheCopy, Again))
1501 if (Again)
1502 TryAgain.push_back(TheCopy);
1503 }
1504 }
1505
1506 void SimpleRegisterCoalescing::joinIntervals() {
1507 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1508
1509 std::vector TryAgainList;
1510 if (loopInfo->empty()) {
1511 // If there are no loops in the function, join intervals in function order.
1512 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1513 I != E; ++I)
1514 CopyCoalesceInMBB(I, TryAgainList);
1515 } else {
1516 // Otherwise, join intervals in inner loops before other intervals.
1517 // Unfortunately we can't just iterate over loop hierarchy here because
1518 // there may be more MBB's than BB's. Collect MBB's for sorting.
1519
1520 // Join intervals in the function prolog first. We want to join physical
1521 // registers with virtual registers before the intervals got too long.
1522 std::vector > MBBs;
1523 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1524 MachineBasicBlock *MBB = I;
1525 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1526 }
1527
1528 // Sort by loop depth.
1529 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1530
1531 // Finally, join intervals in loop nest order.
1532 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1533 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1534 }
1535
1536 // Joining intervals can allow other intervals to be joined. Iteratively join
1537 // until we make no progress.
1538 bool ProgressMade = true;
1539 while (ProgressMade) {
1540 ProgressMade = false;
1541
1542 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1543 MachineInstr *&TheCopy = TryAgainList[i];
1544 if (!TheCopy)
1545 continue;
1546
1547 bool Again = false;
1548 bool Success = JoinCopy(TheCopy, Again);
1549 if (Success || !Again) {
1550 TheCopy= 0; // Mark this one as done.
1551 ProgressMade = true;
1552 }
1553 }
1554 }
1555 }
1556
1557 void SimpleRegisterCoalescing::releaseMemory() {
1558 JoinedCopies.clear();
1559 ReMatCopies.clear();
1560 ReMatDefs.clear();
1561 }
1562
1563 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1564 mf_ = &fn;
1565 mri_ = &fn.getRegInfo();
1566 tm_ = &fn.getTarget();
1567 tri_ = tm_->getRegisterInfo();
1568 tii_ = tm_->getInstrInfo();
1569 li_ = &getAnalysis();
1570 ldv_ = &getAnalysis();
1571 AA = &getAnalysis();
1572 loopInfo = &getAnalysis();
1573
1574 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1575 << "********** Function: "
1576 << ((Value*)mf_->getFunction())->getName() << '\n');
1577
1578 if (VerifyCoalescing)
1579 mf_->verify(this, "Before register coalescing");
1580
1581 RegClassInfo.runOnMachineFunction(fn);
1582
1583 // Join (coalesce) intervals if requested.
1584 if (EnableJoining) {
1585 joinIntervals();
1586 DEBUG({
1587 dbgs() << "********** INTERVALS POST JOINING **********\n";
1588 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
1589 I != E; ++I){
1590 I->second->print(dbgs(), tri_);
1591 dbgs() << "\n";
1592 }
1593 });
1594 }
1595
1596 // Perform a final pass over the instructions and compute spill weights
1597 // and remove identity moves.
1598 SmallVector DeadDefs;
1599 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1600 mbbi != mbbe; ++mbbi) {
1601 MachineBasicBlock* mbb = mbbi;
1602 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1603 mii != mie; ) {
1604 MachineInstr *MI = mii;
1605 if (JoinedCopies.count(MI)) {
1606 // Delete all coalesced copies.
1607 bool DoDelete = true;
1608 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1609 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1610 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1611 MI->getNumOperands() > 2)
1612 // Do not delete extract_subreg, insert_subreg of physical
1613 // registers unless the definition is dead. e.g.
1614 // %DO = INSERT_SUBREG %D0, %S0, 1
1615 // or else the scavenger may complain. LowerSubregs will
1616 // delete them later.
1617 DoDelete = false;
1618
1619 if (MI->allDefsAreDead()) {
1620 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1621 li_->hasInterval(SrcReg))
1622 li_->shrinkToUses(&li_->getInterval(SrcReg));
1623 DoDelete = true;
1624 }
1625 if (!DoDelete) {
1626 // We need the instruction to adjust liveness, so make it a KILL.
1627 if (MI->isSubregToReg()) {
1628 MI->RemoveOperand(3);
1629 MI->RemoveOperand(1);
1630 }
1631 MI->setDesc(tii_->get(TargetOpcode::KILL));
1632 mii = llvm::next(mii);
1633 } else {
1634 li_->RemoveMachineInstrFromMaps(MI);
1635 mii = mbbi->erase(mii);
1636 ++numPeep;
1637 }
1638 continue;
1639 }
1640
1641 // Now check if this is a remat'ed def instruction which is now dead.
1642 if (ReMatDefs.count(MI)) {
1643 bool isDead = true;
1644 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1645 const MachineOperand &MO = MI->getOperand(i);
1646 if (!MO.isReg())
1647 continue;
1648 unsigned Reg = MO.getReg();
1649 if (!Reg)
1650 continue;
1651 if (TargetRegisterInfo::isVirtualRegister(Reg))
1652 DeadDefs.push_back(Reg);
1653 if (MO.isDead())
1654 continue;
1655 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1656 !mri_->use_nodbg_empty(Reg)) {
1657 isDead = false;
1658 break;
1659 }
1660 }
1661 if (isDead) {
1662 while (!DeadDefs.empty()) {
1663 unsigned DeadDef = DeadDefs.back();
1664 DeadDefs.pop_back();
1665 RemoveDeadDef(li_->getInterval(DeadDef), MI);
1666 }
1667 li_->RemoveMachineInstrFromMaps(mii);
1668 mii = mbbi->erase(mii);
1669 continue;
1670 } else
1671 DeadDefs.clear();
1672 }
1673
1674 ++mii;
1675
1676 // Check for now unnecessary kill flags.
1677 if (li_->isNotInMIMap(MI)) continue;
1678 SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex();
1679 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1680 MachineOperand &MO = MI->getOperand(i);
1681 if (!MO.isReg() || !MO.isKill()) continue;
1682 unsigned reg = MO.getReg();
1683 if (!reg || !li_->hasInterval(reg)) continue;
1684 if (!li_->getInterval(reg).killedAt(DefIdx)) {
1685 MO.setIsKill(false);
1686 continue;
1687 }
1688 // When leaving a kill flag on a physreg, check if any subregs should
1689 // remain alive.
1690 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1691 continue;
1692 for (const unsigned *SR = tri_->getSubRegisters(reg);
1693 unsigned S = *SR; ++SR)
1694 if (li_->hasInterval(S) && li_->getInterval(S).liveAt(DefIdx))
1695 MI->addRegisterDefined(S, tri_);
1696 }
1697 }
1698 }
1699
1700 DEBUG(dump());
1701 DEBUG(ldv_->dump());
1702 if (VerifyCoalescing)
1703 mf_->verify(this, "After register coalescing");
1704 return true;
1705 }
1706
1707 /// print - Implement the dump method.
1708 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
1709 li_->print(O, m);
1710 }
1711
1712 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1713 return new SimpleRegisterCoalescing();
1714 }
1715
1716 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1717 DEFINING_FILE_FOR(SimpleRegisterCoalescing)
+0
-1538
lib/CodeGen/SimpleRegisterCoalescing.cpp less more
None //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a simple register coalescing pass that attempts to
10 // aggressively coalesce every register copy that it can.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "regcoalescing"
15 #include "RegisterCoalescer.h"
16 #include "VirtRegMap.h"
17 #include "LiveDebugVariables.h"
18 #include "RegisterCoalescer.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include
39 #include
40 using namespace llvm;
41
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49
50 char SimpleRegisterCoalescing::ID = 0;
51 static cl::opt
52 EnableJoining("join-liveintervals",
53 cl::desc("Coalesce copies (default=true)"),
54 cl::init(true));
55
56 static cl::opt
57 DisableCrossClassJoin("disable-cross-class-join",
58 cl::desc("Avoid coalescing cross register class copies"),
59 cl::init(false), cl::Hidden);
60
61 static cl::opt
62 EnablePhysicalJoin("join-physregs",
63 cl::desc("Join physical register copies"),
64 cl::init(false), cl::Hidden);
65
66 static cl::opt
67 VerifyCoalescing("verify-coalescing",
68 cl::desc("Verify machine instrs before and after register coalescing"),
69 cl::Hidden);
70
71 INITIALIZE_AG_PASS_BEGIN(SimpleRegisterCoalescing, RegisterCoalescer,
72 "simple-register-coalescing", "Simple Register Coalescing",
73 false, false, true)
74 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
75 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
76 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
77 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
78 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
79 INITIALIZE_PASS_DEPENDENCY(PHIElimination)
80 INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
81 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
82 INITIALIZE_AG_PASS_END(SimpleRegisterCoalescing, RegisterCoalescer,
83 "simple-register-coalescing", "Simple Register Coalescing",
84 false, false, true)
85
86 char &llvm::SimpleRegisterCoalescingID = SimpleRegisterCoalescing::ID;
87
88 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
89 AU.setPreservesCFG();
90 AU.addRequired();
91 AU.addRequired();
92 AU.addPreserved();
93 AU.addRequired();
94 AU.addPreserved();
95 AU.addPreserved();
96 AU.addRequired();
97 AU.addPreserved();
98 AU.addPreservedID(MachineDominatorsID);
99 AU.addPreservedID(StrongPHIEliminationID);
100 AU.addPreservedID(PHIEliminationID);
101 AU.addPreservedID(TwoAddressInstructionPassID);
102 MachineFunctionPass::getAnalysisUsage(AU);
103 }
104
105 void SimpleRegisterCoalescing::markAsJoined(MachineInstr *CopyMI) {
106 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
107 JoinedCopies.insert(CopyMI);
108
109 /// Mark all register operands of CopyMI as so they won't affect dead
110 /// code elimination.
111 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
112 E = CopyMI->operands_end(); I != E; ++I)
113 if (I->isReg())
114 I->setIsUndef(true);
115 }
116
117 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
118 /// being the source and IntB being the dest, thus this defines a value number
119 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
120 /// see if we can merge these two pieces of B into a single value number,
121 /// eliminating a copy. For example:
122 ///
123 /// A3 = B0
124 /// ...
125 /// B1 = A3 <- this copy
126 ///
127 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
128 /// value number to be replaced with B0 (which simplifies the B liveinterval).
129 ///
130 /// This returns true if an interval was modified.
131 ///
132 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
133 MachineInstr *CopyMI) {
134 // Bail if there is no dst interval - can happen when merging physical subreg
135 // operations.
136 if (!li_->hasInterval(CP.getDstReg()))
137 return false;
138
139 LiveInterval &IntA =
140 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
141 LiveInterval &IntB =
142 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
143 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
144
145 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
146 // the example above.
147 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
148 if (BLR == IntB.end()) return false;
149 VNInfo *BValNo = BLR->valno;
150
151 // Get the location that B is defined at. Two options: either this value has
152 // an unknown definition point or it is defined at CopyIdx. If unknown, we
153 // can't process it.
154 if (!BValNo->isDefByCopy()) return false;
155 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
156
157 // AValNo is the value number in A that defines the copy, A3 in the example.
158 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
159 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
160 // The live range might not exist after fun with physreg coalescing.
161 if (ALR == IntA.end()) return false;
162 VNInfo *AValNo = ALR->valno;
163 // If it's re-defined by an early clobber somewhere in the live range, then
164 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
165 // See PR3149:
166 // 172 %ECX = MOV32rr %reg1039
167 // 180 INLINEASM
168 // sbbl $3,$0>, 10, %EAX, 14, %ECX, 9,
169 // %EAX,
170 // 36, , 1, %reg0, 0, 9, %ECX, 36, , 1, %reg0, 0
171 // 188 %EAX = MOV32rr %EAX
172 // 196 %ECX = MOV32rr %ECX
173 // 204 %ECX = MOV32rr %ECX
174 // 212 %EAX = MOV32rr %EAX
175 // 220 %EAX = MOV32rr %EAX
176 // 228 %reg1039 = MOV32rr %ECX
177 // The early clobber operand ties ECX input to the ECX def.
178 //
179 // The live interval of ECX is represented as this:
180 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
181 // The coalescer has no idea there was a def in the middle of [174,230].
182 if (AValNo->hasRedefByEC())
183 return false;
184
185 // If AValNo is defined as a copy from IntB, we can potentially process this.
186 // Get the instruction that defines this value number.
187 if (!CP.isCoalescable(AValNo->getCopy()))
188 return false;
189
190 // Get the LiveRange in IntB that this value number starts with.
191 LiveInterval::iterator ValLR =
192 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
193 if (ValLR == IntB.end())
194 return false;
195
196 // Make sure that the end of the live range is inside the same block as
197 // CopyMI.
198 MachineInstr *ValLREndInst =
199 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
200 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
201 return false;
202
203 // Okay, we now know that ValLR ends in the same block that the CopyMI
204 // live-range starts. If there are no intervening live ranges between them in
205 // IntB, we can merge them.
206 if (ValLR+1 != BLR) return false;
207
208 // If a live interval is a physical register, conservatively check if any
209 // of its aliases is overlapping the live interval of the virtual register.
210 // If so, do not coalesce.
211 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
212 for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS)
213 if (li_->hasInterval(*AS) && IntA.overlaps(li_->getInterval(*AS))) {
214 DEBUG({
215 dbgs() << "\t\tInterfere with alias ";
216 li_->getInterval(*AS).print(dbgs(), tri_);
217 });
218 return false;
219 }
220 }
221
222 DEBUG({
223 dbgs() << "Extending: ";
224 IntB.print(dbgs(), tri_);
225 });
226
227 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
228 // We are about to delete CopyMI, so need to remove it as the 'instruction
229 // that defines this value #'. Update the valnum with the new defining
230 // instruction #.
231 BValNo->def = FillerStart;
232 BValNo->setCopy(0);
233
234 // Okay, we can merge them. We need to insert a new liverange:
235 // [ValLR.end, BLR.begin) of either value number, then we merge the
236 // two value numbers.
237 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
238
239 // If the IntB live range is assigned to a physical register, and if that
240 // physreg has sub-registers, update their live intervals as well.
241 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
242 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
243 if (!li_->hasInterval(*SR))
244 continue;
245 LiveInterval &SRLI = li_->getInterval(*SR);
246 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
247 SRLI.getNextValue(FillerStart, 0,
248 li_->getVNInfoAllocator())));
249 }
250 }
251
252 // Okay, merge "B1" into the same value number as "B0".
253 if (BValNo != ValLR->valno) {
254 // If B1 is killed by a PHI, then the merged live range must also be killed
255 // by the same PHI, as B0 and B1 can not overlap.
256 bool HasPHIKill = BValNo->hasPHIKill();
257 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
258 if (HasPHIKill)
259 ValLR->valno->setHasPHIKill(true);
260 }
261 DEBUG({
262 dbgs() << " result = ";
263 IntB.print(dbgs(), tri_);
264 dbgs() << "\n";
265 });
266
267 // If the source instruction was killing the source register before the
268 // merge, unset the isKill marker given the live range has been extended.
269 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
270 if (UIdx != -1) {
271 ValLREndInst->getOperand(UIdx).setIsKill(false);
272 }
273
274 // If the copy instruction was killing the destination register before the
275 // merge, find the last use and trim the live range. That will also add the
276 // isKill marker.
277 if (ALR->end == CopyIdx)
278 li_->shrinkToUses(&IntA);
279
280 ++numExtends;
281 return true;
282 }
283
284 /// HasOtherReachingDefs - Return true if there are definitions of IntB
285 /// other than BValNo val# that can reach uses of AValno val# of IntA.
286 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
287 LiveInterval &IntB,
288 VNInfo *AValNo,
289 VNInfo *BValNo) {
290 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
291 AI != AE; ++AI) {
292 if (AI->valno != AValNo) continue;
293 LiveInterval::Ranges::iterator BI =
294 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
295 if (BI != IntB.ranges.begin())
296 --BI;
297 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
298 if (BI->valno == BValNo)
299 continue;
300 if (BI->start <= AI->start && BI->end > AI->start)
301 return true;
302 if (BI->start > AI->start && BI->start < AI->end)
303 return true;
304 }
305 }
306 return false;
307 }
308
309 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
310 /// IntA being the source and IntB being the dest, thus this defines a value
311 /// number in IntB. If the source value number (in IntA) is defined by a
312 /// commutable instruction and its other operand is coalesced to the copy dest
313 /// register, see if we can transform the copy into a noop by commuting the
314 /// definition. For example,
315 ///
316 /// A3 = op A2 B0
317 /// ...
318 /// B1 = A3 <- this copy
319 /// ...
320 /// = op A3 <- more uses
321 ///
322 /// ==>
323 ///
324 /// B2 = op B0 A2
325 /// ...
326 /// B1 = B2 <- now an identify copy
327 /// ...
328 /// = op B2 <- more uses
329 ///
330 /// This returns true if an interval was modified.
331 ///
332 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
333 MachineInstr *CopyMI) {
334 // FIXME: For now, only eliminate the copy by commuting its def when the
335 // source register is a virtual register. We want to guard against cases
336 // where the copy is a back edge copy and commuting the def lengthen the
337 // live interval of the source register to the entire loop.
338 if (CP.isPhys() && CP.isFlipped())
339 return false;
340
341 // Bail if there is no dst interval.
342 if (!li_->hasInterval(CP.getDstReg()))
343 return false;
344
345 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
346
347 LiveInterval &IntA =
348 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
349 LiveInterval &IntB =
350 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
351
352 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
353 // the example above.
354 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
355 if (!BValNo || !BValNo->isDefByCopy())
356 return false;
357
358 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
359
360 // AValNo is the value number in A that defines the copy, A3 in the example.
361 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getUseIndex());
362 assert(AValNo && "COPY source not live");
363
364 // If other defs can reach uses of this def, then it's not safe to perform
365 // the optimization.
366 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
367 return false;
368 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
369 if (!DefMI)
370 return false;
371 const TargetInstrDesc &TID = DefMI->getDesc();
372 if (!TID.isCommutable())
373 return false;
374 // If DefMI is a two-address instruction then commuting it will change the
375 // destination register.
376 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
377 assert(DefIdx != -1);
378 unsigned UseOpIdx;
379 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
380 return false;
381 unsigned Op1, Op2, NewDstIdx;
382 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
383 return false;
384 if (Op1 == UseOpIdx)
385 NewDstIdx = Op2;
386 else if (Op2 == UseOpIdx)
387 NewDstIdx = Op1;
388 else
389 return false;
390
391 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
392 unsigned NewReg = NewDstMO.getReg();
393 if (NewReg != IntB.reg || !NewDstMO.isKill())
394 return false;
395
396 // Make sure there are no other definitions of IntB that would reach the
397 // uses which the new definition can reach.
398 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
399 return false;
400
401 // Abort if the aliases of IntB.reg have values that are not simply the
402 // clobbers from the superreg.
403 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
404 for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS)
405 if (li_->hasInterval(*AS) &&
406 HasOtherReachingDefs(IntA, li_->getInterval(*AS), AValNo, 0))
407 return false;
408
409 // If some of the uses of IntA.reg is already coalesced away, return false.
410 // It's not possible to determine whether it's safe to perform the coalescing.
411 for (MachineRegisterInfo::use_nodbg_iterator UI =
412 mri_->use_nodbg_begin(IntA.reg),
413 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
414 MachineInstr *UseMI = &*UI;
415 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
416 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
417 if (ULR == IntA.end())
418 continue;
419 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
420 return false;
421 }
422
423 DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t'
424 << *DefMI);
425
426 // At this point we have decided that it is legal to do this
427 // transformation. Start by commuting the instruction.
428 MachineBasicBlock *MBB = DefMI->getParent();
429 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
430 if (!NewMI)
431 return false;
432 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
433 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
434 !mri_->constrainRegClass(IntB.reg, mri_->getRegClass(IntA.reg)))
435 return false;
436 if (NewMI != DefMI) {
437 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
438 MBB->insert(DefMI, NewMI);
439 MBB->erase(DefMI);
440 }
441 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
442 NewMI->getOperand(OpIdx).setIsKill();
443
444 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
445 // A = or A, B
446 // ...
447 // B = A
448 // ...
449 // C = A
450 // ...
451 // = B
452
453 // Update uses of IntA of the specific Val# with IntB.
454 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
455 UE = mri_->use_end(); UI != UE;) {
456 MachineOperand &UseMO = UI.getOperand();
457 MachineInstr *UseMI = &*UI;
458 ++UI;
459 if (JoinedCopies.count(UseMI))
460 continue;
461 if (UseMI->isDebugValue()) {
462 // FIXME These don't have an instruction index. Not clear we have enough
463 // info to decide whether to do this replacement or not. For now do it.
464 UseMO.setReg(NewReg);
465 continue;
466 }
467 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
468 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
469 if (ULR == IntA.end() || ULR->valno != AValNo)
470 continue;
471 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
472 UseMO.substPhysReg(NewReg, *tri_);
473 else
474 UseMO.setReg(NewReg);
475 if (UseMI == CopyMI)
476 continue;
477 if (!UseMI->isCopy())
478 continue;
479 if (UseMI->getOperand(0).getReg() != IntB.reg ||
480 UseMI->getOperand(0).getSubReg())
481 continue;
482
483 // This copy will become a noop. If it's defining a new val#, merge it into
484 // BValNo.
485 SlotIndex DefIdx = UseIdx.getDefIndex();
486 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
487 if (!DVNI)
488 continue;
489 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
490 assert(DVNI->def == DefIdx);
491 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
492 markAsJoined(UseMI);
493 }
494
495 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
496 // is updated.
497 VNInfo *ValNo = BValNo;
498 ValNo->def = AValNo->def;
499 ValNo->setCopy(0);
500 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
501 AI != AE; ++AI) {
502 if (AI->valno != AValNo) continue;
503 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
504 }
505 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
506
507 IntA.removeValNo(AValNo);
508 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
509 ++numCommutes;
510 return true;
511 }
512
513 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
514 /// computation, replace the copy by rematerialize the definition.
515 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
516 bool preserveSrcInt,
517 unsigned DstReg,
518 unsigned DstSubIdx,
519 MachineInstr *CopyMI) {
520 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
521 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
522 assert(SrcLR != SrcInt.end() && "Live range not found!");
523 VNInfo *ValNo = SrcLR->valno;
524 // If other defs can reach uses of this def, then it's not safe to perform
525 // the optimization.
526 if (ValNo->isPHIDef() || ValNo->isUnused() || ValNo->hasPHIKill())
527 return false;
528 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
529 if (!DefMI)
530 return false;
531 assert(DefMI && "Defining instruction disappeared");
532 const TargetInstrDesc &TID = DefMI->getDesc();
533 if (!TID.isAsCheapAsAMove())
534 return false;
535 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
536 return false;
537 bool SawStore = false;
538 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
539 return false;
540 if (TID.getNumDefs() != 1)
541 return false;
542 if (!DefMI->isImplicitDef()) {
543 // Make sure the copy destination register class fits the instruction
544 // definition register class. The mismatch can happen as a result of earlier
545 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
546 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
547 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
548 if (mri_->getRegClass(DstReg) != RC)
549 return false;
550 } else if (!RC->contains(DstReg))
551 return false;
552 }
553
554 // If destination register has a sub-register index on it, make sure it
555 // matches the instruction register class.
556 if (DstSubIdx) {
557 const TargetInstrDesc &TID = DefMI->getDesc();
558 if (TID.getNumDefs() != 1)
559 return false;
560 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
561 const TargetRegisterClass *DstSubRC =
562 DstRC->getSubRegisterRegClass(DstSubIdx);
563 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
564 if (DefRC == DstRC)
565 DstSubIdx = 0;
566 else if (DefRC != DstSubRC)
567 return false;
568 }
569
570 RemoveCopyFlag(DstReg, CopyMI);
571
572 MachineBasicBlock *MBB = CopyMI->getParent();
573 MachineBasicBlock::iterator MII =
574 llvm::next(MachineBasicBlock::iterator(CopyMI));
575 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
576 MachineInstr *NewMI = prior(MII);
577
578 // CopyMI may have implicit operands, transfer them over to the newly
579 // rematerialized instruction. And update implicit def interval valnos.
580 for (unsigned i = CopyMI->getDesc().getNumOperands(),
581 e = CopyMI->getNumOperands(); i != e; ++i) {
582 MachineOperand &MO = CopyMI->getOperand(i);
583 if (MO.isReg() && MO.isImplicit())
584 NewMI->addOperand(MO);
585 if (MO.isDef())
586 RemoveCopyFlag(MO.getReg(), CopyMI);
587 }
588
589 NewMI->copyImplicitOps(CopyMI);
590 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
591 CopyMI->eraseFromParent();
592 ReMatCopies.insert(CopyMI);
593 ReMatDefs.insert(DefMI);
594 DEBUG(dbgs() << "Remat: " << *NewMI);
595 ++NumReMats;
596
597 // The source interval can become smaller because we removed a use.
598 if (preserveSrcInt)
599 li_->shrinkToUses(&SrcInt);
600
601 return true;
602 }
603
604 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
605 /// update the subregister number if it is not zero. If DstReg is a
606 /// physical register and the existing subregister number of the def / use
607 /// being updated is not zero, make sure to set it to the correct physical
608 /// subregister.
609 void
610 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
611 bool DstIsPhys = CP.isPhys();
612 unsigned SrcReg = CP.getSrcReg();
613 unsigned DstReg = CP.getDstReg();
614 unsigned SubIdx = CP.getSubIdx();
615
616 // Update LiveDebugVariables.
617 ldv_->renameRegister(SrcReg, DstReg, SubIdx);
618
619 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
620 MachineInstr *UseMI = I.skipInstruction();) {
621 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
622 // instead.
623 if (DstIsPhys) {
624 if (UseMI->isCopy() &&
625 !UseMI->getOperand(1).getSubReg() &&
626 !UseMI->getOperand(0).getSubReg() &&
627 UseMI->getOperand(1).getReg() == SrcReg &&
628 UseMI->getOperand(0).getReg() != SrcReg &&
629 UseMI->getOperand(0).getReg() != DstReg &&
630 !JoinedCopies.count(UseMI) &&
631 ReMaterializeTrivialDef(li_->getInterval(SrcReg), false,
632 UseMI->getOperand(0).getReg(), 0, UseMI))
633 continue;
634 }
635
636 SmallVector Ops;
637 bool Reads, Writes;
638 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
639 bool Kills = false, Deads = false;
640
641 // Replace SrcReg with DstReg in all UseMI operands.
642 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
643 MachineOperand &MO = UseMI->getOperand(Ops[i]);
644 Kills |= MO.isKill();
645 Deads |= MO.isDead();
646
647 if (DstIsPhys)
648 MO.substPhysReg(DstReg, *tri_);
649 else
650 MO.substVirtReg(DstReg, SubIdx, *tri_);
651 }
652
653 // This instruction is a copy that will be removed.
654 if (JoinedCopies.count(UseMI))
655 continue;
656
657 if (SubIdx) {
658 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
659 // read-modify-write of DstReg.
660 if (Deads)
661 UseMI->addRegisterDead(DstReg, tri_);
662 else if (!Reads && Writes)
663 UseMI->addRegisterDefined(DstReg, tri_);
664
665 // Kill flags apply to the whole physical register.
666 if (DstIsPhys && Kills)
667 UseMI->addRegisterKilled(DstReg, tri_);
668 }
669
670 DEBUG({
671 dbgs() << "\t\tupdated: ";
672 if (!UseMI->isDebugValue())
673 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
674 dbgs() << *UseMI;
675 });
676 }
677 }
678
679 /// removeIntervalIfEmpty - Check if the live interval of a physical register
680 /// is empty, if so remove it and also remove the empty intervals of its
681 /// sub-registers. Return true if live interval is removed.
682 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
683 const TargetRegisterInfo *tri_) {
684 if (li.empty()) {
685 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
686 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
687 if (!li_->hasInterval(*SR))
688 continue;
689 LiveInterval &sli = li_->getInterval(*SR);
690 if (sli.empty())
691 li_->removeInterval(*SR);
692 }
693 li_->removeInterval(li.reg);
694 return true;
695 }
696 return false;
697 }
698
699 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
700 /// the val# it defines. If the live interval becomes empty, remove it as well.
701 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
702 MachineInstr *DefMI) {
703 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
704 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
705 if (DefIdx != MLR->valno->def)
706 return false;
707 li.removeValNo(MLR->valno);
708 return removeIntervalIfEmpty(li, li_, tri_);
709 }
710
711 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
712 const MachineInstr *CopyMI) {
713 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
714 if (li_->hasInterval(DstReg)) {
715 LiveInterval &LI = li_->getInterval(DstReg);
716 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
717 if (LR->valno->def == DefIdx)
718 LR->valno->setCopy(0);
719 }
720 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
721 return;
722 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
723 if (!li_->hasInterval(*AS))
724 continue;
725 LiveInterval &LI = li_->getInterval(*AS);
726 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
727 if (LR->valno->def == DefIdx)
728 LR->valno->setCopy(0);
729 }
730 }
731
732 /// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
733 /// We need to be careful about coalescing a source physical register with a
734 /// virtual register. Once the coalescing is done, it cannot be broken and these
735 /// are not spillable! If the destination interval uses are far away, think
736 /// twice about coalescing them!
737 bool SimpleRegisterCoalescing::shouldJoinPhys(CoalescerPair &CP) {
738 bool Allocatable = li_->isAllocatable(CP.getDstReg());
739 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
740
741 /// Always join simple intervals that are defined by a single copy from a
742 /// reserved register. This doesn't increase register pressure, so it is
743 /// always beneficial.
744 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
745 return true;
746
747 if (!EnablePhysicalJoin) {
748 DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
749 return false;
750 }
751
752 // Only coalesce to allocatable physreg, we don't want to risk modifying
753 // reserved registers.
754 if (!Allocatable) {
755 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
756 return false; // Not coalescable.
757 }
758
759 // Don't join with physregs that have a ridiculous number of live
760 // ranges. The data structure performance is really bad when that
761 // happens.
762 if (li_->hasInterval(CP.getDstReg()) &&
763 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
764 ++numAborts;
765 DEBUG(dbgs()
766 << "\tPhysical register live interval too complicated, abort!\n");
767 return false;
768 }
769
770 // FIXME: Why are we skipping this test for partial copies?
771 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
772 if (!CP.isPartial()) {
773 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
774 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
775 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
776 if (Length > Threshold) {
777 ++numAborts;
778 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
779 return false;
780 }
781 }
782 return true;
783 }
784
785 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
786 /// two virtual registers from different register classes.
787 bool
788 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
789 unsigned DstReg,
790 const TargetRegisterClass *SrcRC,
791 const TargetRegisterClass *DstRC,
792 const TargetRegisterClass *NewRC) {
793 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
794 // This heuristics is good enough in practice, but it's obviously not *right*.
795 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
796 // out all but the most restrictive register classes.
797 if (NewRCCount > 4 ||
798 // Early exit if the function is fairly small, coalesce aggressively if
799 // that's the case. For really special register classes with 3 or
800 // fewer registers, be a bit more careful.
801 (li_->getFuncInstructionCount() / NewRCCount) < 8)
802 return true;
803 LiveInterval &SrcInt = li_->getInterval(SrcReg);
804 LiveInterval &DstInt = li_->getInterval(DstReg);
805 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
806 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
807
808 // Coalesce aggressively if the intervals are small compared to the number of
809 // registers in the new class. The number 4 is fairly arbitrary, chosen to be
810 // less aggressive than the 8 used for the whole function size.
811 const unsigned ThresSize = 4 * NewRCCount;
812 if (SrcSize <= ThresSize && DstSize <= ThresSize)
813 return true;
814
815 // Estimate *register use density*. If it doubles or more, abort.
816 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
817 mri_->use_nodbg_end());
818 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
819 mri_->use_nodbg_end());
820 unsigned NewUses = SrcUses + DstUses;
821 unsigned NewSize = SrcSize + DstSize;
822 if (SrcRC != NewRC && SrcSize > ThresSize) {
823 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
824 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
825 return false;
826 }
827 if (DstRC != NewRC && DstSize > ThresSize) {
828 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
829 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
830 return false;
831 }
832 return true;
833 }
834
835
836 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
837 /// which are the src/dst of the copy instruction CopyMI. This returns true
838 /// if the copy was successfully coalesced away. If it is not currently
839 /// possible to coalesce this interval, but it may be possible if other
840 /// things get coalesced, then it returns true by reference in 'Again'.
841 bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI, bool &Again) {
842
843 Again = false;
844 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
845 return false; // Already done.
846
847 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
848
849 CoalescerPair CP(*tii_, *tri_);
850 if (!CP.setRegisters(CopyMI)) {
851 DEBUG(dbgs() << "\tNot coalescable.\n");
852 return false;
853 }
854
855 // If they are already joined we continue.
856 if (CP.getSrcReg() == CP.getDstReg()) {
857 markAsJoined(CopyMI);
858 DEBUG(dbgs() << "\tCopy already coalesced.\n");
859 return false; // Not coalescable.
860 }
861
862 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_)
863 << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx())
864 << "\n");
865
866 // Enforce policies.
867 if (CP.isPhys()) {
868 if (!shouldJoinPhys(CP)) {
869 // Before giving up coalescing, if definition of source is defined by
870 // trivial computation, try rematerializing it.
871 if (!CP.isFlipped() &&
872 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), true,
873 CP.getDstReg(), 0, CopyMI))
874 return true;
875 return false;
876 }
877 } else {
878 // Avoid constraining virtual register regclass too much.
879 if (CP.isCrossClass()) {
880 DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
881 if (DisableCrossClassJoin) {
882 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
883 return false;
884 }
885 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
886 mri_->getRegClass(CP.getSrcReg()),
887 mri_->getRegClass(CP.getDstReg()),
888 CP.getNewRC())) {
889 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
890 Again = true; // May be possible to coalesce later.
891 return false;
892 }
893 }
894
895 // When possible, let DstReg be the larger interval.
896 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
897 li_->getInterval(CP.getDstReg()).ranges.size())
898 CP.flip();
899 }
900
901 // Okay, attempt to join these two intervals. On failure, this returns false.
902 // Otherwise, if one of the intervals being joined is a physreg, this method
903 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
904 // been modified, so we can use this information below to update aliases.
905 if (!JoinIntervals(CP)) {
906 // Coalescing failed.
907
908 // If definition of source is defined by trivial computation, try
909 // rematerializing it.
910 if (!CP.isFlipped() &&
911 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), true,
912 CP.getDstReg(), 0, CopyMI))
913 return true;
914
915 // If we can eliminate the copy without merging the live ranges, do so now.
916 if (!CP.isPartial()) {
917 if (AdjustCopiesBackFrom(CP, CopyMI) ||
918 RemoveCopyByCommutingDef(CP, CopyMI)) {
919 markAsJoined(CopyMI);
920 DEBUG(dbgs() << "\tTrivial!\n");
921 return true;
922 }
923 }
924
925 // Otherwise, we are unable to join the intervals.
926 DEBUG(dbgs() << "\tInterference!\n");
927 Again = true; // May be possible to coalesce later.
928 return false;
929 }
930
931 // Coalescing to a virtual register that is of a sub-register class of the
932 // other. Make sure the resulting register is set to the right register class.
933 if (CP.isCrossClass()) {
934 ++numCrossRCs;
935 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
936 }
937
938 // Remember to delete the copy instruction.
939 markAsJoined(CopyMI);
940
941 UpdateRegDefsUses(CP);
942
943 // If we have extended the live range of a physical register, make sure we
944 // update live-in lists as well.
945 if (CP.isPhys()) {
946 SmallVector BlockSeq;
947 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
948 // ranges for this, and they are preserved.
949 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
950 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
951 I != E; ++I ) {
952 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
953 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
954 MachineBasicBlock &block = *BlockSeq[idx];
955 if (!block.isLiveIn(CP.getDstReg()))
956 block.addLiveIn(CP.getDstReg());
957 }
958 BlockSeq.clear();
959 }
960 }
961
962 // SrcReg is guarateed to be the register whose live interval that is
963 // being merged.
964 li_->removeInterval(CP.getSrcReg());
965
966 // Update regalloc hint.
967 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
968
969 DEBUG({
970 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
971 dbgs() << "\tJoined. Result = ";
972 DstInt.print(dbgs(), tri_);
973 dbgs() << "\n";
974 });
975
976 ++numJoins;
977 return true;
978 }
979
980 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
981 /// compute what the resultant value numbers for each value in the input two
982 /// ranges will be. This is complicated by copies between the two which can
983 /// and will commonly cause multiple value numbers to be merged into one.
984 ///
985 /// VN is the value number that we're trying to resolve. InstDefiningValue
986 /// keeps track of the new InstDefiningValue assignment for the result
987 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
988 /// whether a value in this or other is a copy from the opposite set.
989 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
990 /// already been assigned.
991 ///
992 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
993 /// contains the value number the copy is from.
994 ///
995 static unsigned ComputeUltimateVN(VNInfo *VNI,
996 SmallVector &NewVNInfo,
997 DenseMap &ThisFromOther,
998 DenseMap &OtherFromThis,
999 SmallVector &ThisValNoAssignments,
1000 SmallVector &OtherValNoAssignments) {
1001 unsigned VN = VNI->id;
1002
1003 // If the VN has already been computed, just return it.
1004 if (ThisValNoAssignments[VN] >= 0)
1005 return ThisValNoAssignments[VN];
1006 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1007
1008 // If this val is not a copy from the other val, then it must be a new value
1009 // number in the destination.
1010 DenseMap::iterator I = ThisFromOther.find(VNI);
1011 if (I == ThisFromOther.end()) {
1012 NewVNInfo.push_back(VNI);
1013 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1014 }
1015 VNInfo *OtherValNo = I->second;
1016
1017 // Otherwise, this *is* a copy from the RHS. If the other side has already
1018 // been computed, return it.
1019 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1020 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1021
1022 // Mark this value number as currently being computed, then ask what the
1023 // ultimate value # of the other value is.
1024 ThisValNoAssignments[VN] = -2;
1025 unsigned UltimateVN =
1026 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1027 OtherValNoAssignments, ThisValNoAssignments);
1028 return ThisValNoAssignments[VN] = UltimateVN;
1029 }
1030
1031 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1032 /// returns false.
1033 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1034 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1035 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1036
1037 // If a live interval is a physical register, check for interference with any
1038 // aliases. The interference check implemented here is a bit more conservative
1039 // than the full interfeence check below. We allow overlapping live ranges
1040 // only when one is a copy of the other.
1041 if (CP.isPhys()) {
1042 for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
1043 if (!li_->hasInterval(*AS))
1044 continue;
1045 const LiveInterval &LHS = li_->getInterval(*AS);
1046 LiveInterval::const_iterator LI = LHS.begin();
1047 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1048 RI != RE; ++RI) {
1049 LI = std::lower_bound(LI, LHS.end(), RI->start);
1050 // Does LHS have an overlapping live range starting before RI?
1051 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1052 (RI->start != RI->valno->def ||
1053 !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
1054 DEBUG({
1055 dbgs() << "\t\tInterference from alias: ";
1056 LHS.print(dbgs(), tri_);
1057 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1058 });
1059 return false;
1060 }
1061
1062 // Check that LHS ranges beginning in this range are copies.
1063 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1064 if (LI->start != LI->valno->def ||
1065 !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
1066 DEBUG({
1067 dbgs() << "\t\tInterference from alias: ";
1068 LHS.print(dbgs(), tri_);
1069 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1070 });
1071 return false;
1072 }
1073 }
1074 }
1075 }
1076 }
1077
1078 // Compute the final value assignment, assuming that the live ranges can be
1079 // coalesced.
1080 SmallVector LHSValNoAssignments;
1081 SmallVector RHSValNoAssignments;
1082 DenseMap LHSValsDefinedFromRHS;
1083 DenseMap RHSValsDefinedFromLHS;
1084 SmallVector NewVNInfo;
1085
1086 LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
1087 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
1088
1089 // Loop over the value numbers of the LHS, seeing if any are defined from
1090 // the RHS.
1091 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1092 i != e; ++i) {
1093 VNInfo *VNI = *i;
1094 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1095 continue;
1096
1097 // Never join with a register that has EarlyClobber redefs.
1098 if (VNI->hasRedefByEC())
1099 return false;
1100
1101 // DstReg is known to be a register in the LHS interval. If the src is
1102 // from the RHS interval, we can use its value #.
1103 if (!CP.isCoalescable(VNI->getCopy()))
1104 continue;
1105
1106 // Figure out the value # from the RHS.
1107 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1108 // The copy could be to an aliased physreg.
1109 if (!lr) continue;
1110 LHSValsDefinedFromRHS[VNI] = lr->valno;
1111 }
1112
1113 // Loop over the value numbers of the RHS, seeing if any are defined from
1114 // the LHS.
1115 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1116 i != e; ++i) {
1117 VNInfo *VNI = *i;
1118 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy?
1119 continue;
1120
1121 // Never join with a register that has EarlyClobber redefs.
1122 if (VNI->hasRedefByEC())
1123 return false;
1124
1125 // DstReg is known to be a register in the RHS interval. If the src is
1126 // from the LHS interval, we can use its value #.
1127 if (!CP.isCoalescable(VNI->getCopy()))
1128 continue;
1129
1130 // Figure out the value # from the LHS.
1131 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1132 // The copy could be to an aliased physreg.
1133 if (!lr) continue;
1134 RHSValsDefinedFromLHS[VNI] = lr->valno;
1135 }
1136
1137 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1138 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1139 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1140
1141 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1142 i != e; ++i) {
1143 VNInfo *VNI = *i;
1144 unsigned VN = VNI->id;
1145 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1146 continue;
1147 ComputeUltimateVN(VNI, NewVNInfo,
1148 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1149 LHSValNoAssignments, RHSValNoAssignments);
1150 }
1151 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1152 i != e; ++i) {
1153 VNInfo *VNI = *i;
1154 unsigned VN = VNI->id;
1155 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1156 continue;
1157 // If this value number isn't a copy from the LHS, it's a new number.
1158 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1159 NewVNInfo.push_back(VNI);
1160 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1161 continue;
1162 }
1163
1164 ComputeUltimateVN(VNI, NewVNInfo,
1165 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1166 RHSValNoAssignments, LHSValNoAssignments);
1167 }
1168
1169 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1170 // interval lists to see if these intervals are coalescable.
1171 LiveInterval::const_iterator I = LHS.begin();
1172 LiveInterval::const_iterator IE = LHS.end();
1173 LiveInterval::const_iterator J = RHS.begin();
1174 LiveInterval::const_iterator JE = RHS.end();
1175
1176 // Skip ahead until the first place of potential sharing.
1177 if (I != IE && J != JE) {
1178 if (I->start < J->start) {
1179 I = std::upper_bound(I, IE, J->start);
1180 if (I != LHS.begin()) --I;
1181 } else if (J->start < I->start) {
1182 J = std::upper_bound(J, JE, I->start);
1183 if (J != RHS.begin()) --J;
1184 }
1185 }
1186
1187 while (I != IE && J != JE) {
1188 // Determine if these two live ranges overlap.
1189 bool Overlaps;
1190 if (I->start < J->start) {
1191 Overlaps = I->end > J->start;
1192 } else {
1193 Overlaps = J->end > I->start;
1194 }
1195
1196 // If so, check value # info to determine if they are really different.
1197 if (Overlaps) {
1198 // If the live range overlap will map to the same value number in the
1199 // result liverange, we can still coalesce them. If not, we can't.
1200 if (LHSValNoAssignments[I->valno->id] !=
1201 RHSValNoAssignments[J->valno->id])
1202 return false;
1203 // If it's re-defined by an early clobber somewhere in the live range,
1204 // then conservatively abort coalescing.
1205 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1206 return false;
1207 }
1208
1209 if (I->end < J->end)
1210 ++I;
1211 else
1212 ++J;
1213 }
1214
1215 // Update kill info. Some live ranges are extended due to copy coalescing.
1216 for (DenseMap::iterator I = LHSValsDefinedFromRHS.begin(),
1217 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1218 VNInfo *VNI = I->first;
1219 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1220 if (VNI->hasPHIKill())
1221 NewVNInfo[LHSValID]->setHasPHIKill(true);
1222 }
1223
1224 // Update kill info. Some live ranges are extended due to copy coalescing.
1225 for (DenseMap::iterator I = RHSValsDefinedFromLHS.begin(),
1226 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1227 VNInfo *VNI = I->first;
1228 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1229 if (VNI->hasPHIKill())
1230 NewVNInfo[RHSValID]->setHasPHIKill(true);
1231 }
1232
1233 if (LHSValNoAssignments.empty())
1234 LHSValNoAssignments.push_back(-1);
1235 if (RHSValNoAssignments.empty())
1236 RHSValNoAssignments.push_back(-1);
1237
1238 // If we get here, we know that we can coalesce the live ranges. Ask the
1239 // intervals to coalesce themselves now.
1240 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1241 mri_);
1242 return true;
1243 }
1244
1245 namespace {
1246 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1247 // depth of the basic block (the unsigned), and then on the MBB number.
1248 struct DepthMBBCompare {
1249 typedef std::pair DepthMBBPair;
1250 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1251 // Deeper loops first
1252 if (LHS.first != RHS.first)
1253 return LHS.first > RHS.first;
1254
1255 // Prefer blocks that are more connected in the CFG. This takes care of
1256 // the most difficult copies first while intervals are short.
1257 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1258 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1259 if (cl != cr)
1260 return cl > cr;
1261
1262 // As a last resort, sort by block number.
1263 return LHS.second->getNumber() < RHS.second->getNumber();
1264 }
1265 };
1266 }
1267
1268 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1269 std::vector &TryAgain) {
1270 DEBUG(dbgs() << MBB->getName() << ":\n");
1271
1272 SmallVector VirtCopies;
1273 SmallVector PhysCopies;
1274 SmallVector ImpDefCopies;
1275 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1276 MII != E;) {
1277 MachineInstr *Inst = MII++;
1278
1279 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1280 unsigned SrcReg, DstReg;
1281 if (Inst->isCopy()) {
1282 DstReg = Inst->getOperand(0).getReg();
1283 SrcReg = Inst->getOperand(1).getReg();
1284 } else if (Inst->isSubregToReg()) {
1285 DstReg = Inst->getOperand(0).getReg();
1286 SrcReg = Inst->getOperand(2).getReg();
1287 } else
1288 continue;
1289
1290 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1291 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1292 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1293 ImpDefCopies.push_back(Inst);
1294 else if (SrcIsPhys || DstIsPhys)
1295 PhysCopies.push_back(Inst);
1296 else
1297 VirtCopies.push_back(Inst);
1298 }
1299
1300 // Try coalescing implicit copies and insert_subreg first,
1301 // followed by copies to / from physical registers, then finally copies
1302 // from virtual registers to virtual registers.
1303 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1304 MachineInstr *TheCopy = ImpDefCopies[i];
1305 bool Again = false;
1306 if (!JoinCopy(TheCopy, Again))
1307 if (Again)
1308 TryAgain.push_back(TheCopy);
1309 }
1310 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1311 MachineInstr *TheCopy = PhysCopies[i];
1312 bool Again = false;
1313 if (!JoinCopy(TheCopy, Again))
1314 if (Again)
1315 TryAgain.push_back(TheCopy);
1316 }
1317 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1318 MachineInstr *TheCopy = VirtCopies[i];
1319 bool Again = false;
1320 if (!JoinCopy(TheCopy, Again))
1321 if (Again)
1322 TryAgain.push_back(TheCopy);
1323 }
1324 }
1325
1326 void SimpleRegisterCoalescing::joinIntervals() {
1327 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1328
1329 std::vector TryAgainList;
1330 if (loopInfo->empty()) {
1331 // If there are no loops in the function, join intervals in function order.
1332 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1333 I != E; ++I)
1334 CopyCoalesceInMBB(I, TryAgainList);
1335 } else {
1336 // Otherwise, join intervals in inner loops before other intervals.
1337 // Unfortunately we can't just iterate over loop hierarchy here because
1338 // there may be more MBB's than BB's. Collect MBB's for sorting.
1339
1340 // Join intervals in the function prolog first. We want to join physical
1341 // registers with virtual registers before the intervals got too long.
1342 std::vector > MBBs;
1343 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1344 MachineBasicBlock *MBB = I;
1345 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1346 }
1347
1348 // Sort by loop depth.
1349 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1350
1351 // Finally, join intervals in loop nest order.
1352 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1353 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1354 }
1355
1356 // Joining intervals can allow other intervals to be joined. Iteratively join
1357 // until we make no progress.
1358 bool ProgressMade = true;
1359 while (ProgressMade) {
1360 ProgressMade = false;
1361
1362 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1363 MachineInstr *&TheCopy = TryAgainList[i];
1364 if (!TheCopy)
1365 continue;
1366
1367 bool Again = false;
1368 bool Success = JoinCopy(TheCopy, Again);
1369 if (Success || !Again) {
1370 TheCopy= 0; // Mark this one as done.
1371 ProgressMade = true;
1372 }
1373 }
1374 }
1375 }
1376
1377 void SimpleRegisterCoalescing::releaseMemory() {
1378 JoinedCopies.clear();
1379 ReMatCopies.clear();
1380 ReMatDefs.clear();
1381 }
1382
1383 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1384 mf_ = &fn;
1385 mri_ = &fn.getRegInfo();
1386 tm_ = &fn.getTarget();
1387 tri_ = tm_->getRegisterInfo();
1388 tii_ = tm_->getInstrInfo();
1389 li_ = &getAnalysis();
1390 ldv_ = &getAnalysis();
1391 AA = &getAnalysis();
1392 loopInfo = &getAnalysis();
1393
1394 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1395 << "********** Function: "
1396 << ((Value*)mf_->getFunction())->getName() << '\n');
1397
1398 if (VerifyCoalescing)
1399 mf_->verify(this, "Before register coalescing");
1400
1401 RegClassInfo.runOnMachineFunction(fn);
1402
1403 // Join (coalesce) intervals if requested.
1404 if (EnableJoining) {
1405 joinIntervals();
1406 DEBUG({
1407 dbgs() << "********** INTERVALS POST JOINING **********\n";
1408 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
1409 I != E; ++I){
1410 I->second->print(dbgs(), tri_);
1411 dbgs() << "\n";
1412 }
1413 });
1414 }
1415
1416 // Perform a final pass over the instructions and compute spill weights
1417 // and remove identity moves.
1418 SmallVector DeadDefs;
1419 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1420 mbbi != mbbe; ++mbbi) {
1421 MachineBasicBlock* mbb = mbbi;
1422 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1423 mii != mie; ) {
1424 MachineInstr *MI = mii;
1425 if (JoinedCopies.count(MI)) {
1426 // Delete all coalesced copies.
1427 bool DoDelete = true;
1428 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1429 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1430 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1431 MI->getNumOperands() > 2)
1432 // Do not delete extract_subreg, insert_subreg of physical
1433 // registers unless the definition is dead. e.g.
1434 // %DO = INSERT_SUBREG %D0, %S0, 1
1435 // or else the scavenger may complain. LowerSubregs will
1436 // delete them later.
1437 DoDelete = false;
1438
1439 if (MI->allDefsAreDead()) {
1440 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1441 li_->hasInterval(SrcReg))
1442 li_->shrinkToUses(&li_->getInterval(SrcReg));
1443 DoDelete = true;
1444 }
1445 if (!DoDelete) {
1446 // We need the instruction to adjust liveness, so make it a KILL.
1447 if (MI->isSubregToReg()) {
1448 MI->RemoveOperand(3);
1449 MI->RemoveOperand(1);
1450 }
1451 MI->setDesc(tii_->get(TargetOpcode::KILL));
1452 mii = llvm::next(mii);
1453 } else {
1454 li_->RemoveMachineInstrFromMaps(MI);
1455 mii = mbbi->erase(mii);
1456 ++numPeep;
1457 }
1458 continue;
1459 }
1460
1461 // Now check if this is a remat'ed def instruction which is now dead.
1462 if (ReMatDefs.count(MI)) {
1463 bool isDead = true;
1464 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1465 const MachineOperand &MO = MI->getOperand(i);
1466 if (!MO.isReg())
1467 continue;
1468 unsigned Reg = MO.getReg();
1469 if (!Reg)
1470 continue;
1471 if (TargetRegisterInfo::isVirtualRegister(Reg))
1472 DeadDefs.push_back(Reg);
1473 if (MO.isDead())
1474 continue;
1475 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1476 !mri_->use_nodbg_empty(Reg)) {
1477 isDead = false;
1478 break;
1479 }
1480 }
1481 if (isDead) {
1482 while (!DeadDefs.empty()) {
1483 unsigned DeadDef = DeadDefs.back();
1484 DeadDefs.pop_back();
1485 RemoveDeadDef(li_->getInterval(DeadDef), MI);
1486 }
1487 li_->RemoveMachineInstrFromMaps(mii);
1488 mii = mbbi->erase(mii);
1489 continue;
1490 } else
1491 DeadDefs.clear();
1492 }
1493
1494 ++mii;
1495
1496 // Check for now unnecessary kill flags.
1497 if (li_->isNotInMIMap(MI)) continue;
1498 SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex();
1499 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1500 MachineOperand &MO = MI->getOperand(i);
1501 if (!MO.isReg() || !MO.isKill()) continue;
1502 unsigned reg = MO.getReg();
1503 if (!reg || !li_->hasInterval(reg)) continue;
1504 if (!li_->getInterval(reg).killedAt(DefIdx)) {
1505 MO.setIsKill(false);
1506 continue;
1507 }
1508 // When leaving a kill flag on a physreg, check if any subregs should
1509 // remain alive.
1510 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1511 continue;
1512 for (const unsigned *SR = tri_->getSubRegisters(reg);
1513 unsigned S = *SR; ++SR)
1514 if (li_->hasInterval(S) && li_->getInterval(S).liveAt(DefIdx))
1515 MI->addRegisterDefined(S, tri_);
1516 }
1517 }
1518 }
1519
1520 DEBUG(dump());
1521 DEBUG(ldv_->dump());
1522 if (VerifyCoalescing)
1523 mf_->verify(this, "After register coalescing");
1524 return true;
1525 }
1526
1527 /// print - Implement the dump method.
1528 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
1529 li_->print(O, m);
1530 }
1531
1532 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1533 return new SimpleRegisterCoalescing();
1534 }
1535
1536 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1537 DEFINING_FILE_FOR(SimpleRegisterCoalescing)