llvm.org GIT mirror llvm / 64110ff
Add SchedRW as an Instruction field. Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
3 changed file(s) with 14 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
15581558 ///
15591559 Init *getValueInit(StringRef FieldName) const;
15601560
1561 /// Return true if the named field is unset.
1562 bool isValueUnset(StringRef FieldName) const {
1563 return getValueInit(FieldName) == UnsetInit::get();
1564 }
1565
15611566 /// getValueAsString - This method looks up the specified field and returns
15621567 /// its value as a string, throwing an exception if the field does not exist
15631568 /// or if the value is not a string.
396396
397397 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
398398
399 // Scheduling information from TargetSchedule.td.
400 list SchedRW;
401
399402 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
400403
401404 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
216216 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
217217 E = Target.inst_end(); I != E; ++I) {
218218 Record *SchedDef = (*I)->TheDef;
219 if (!SchedDef->isSubClassOf("Sched"))
219 if (SchedDef->isValueUnset("SchedRW"))
220220 continue;
221221 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
222222 for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
528528 // instruction definition that inherits from class Sched.
529529 for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
530530 E = Target.inst_end(); I != E; ++I) {
531 if (!(*I)->TheDef->isSubClassOf("Sched"))
531 if ((*I)->TheDef->isValueUnset("SchedRW"))
532532 continue;
533533 IdxVec Writes, Reads;
534534 findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
552552 E = Target.inst_end(); I != E; ++I) {
553553 Record *SchedDef = (*I)->TheDef;
554554 std::string InstName = (*I)->TheDef->getName();
555 if (SchedDef->isSubClassOf("Sched")) {
555 if (!SchedDef->isValueUnset("SchedRW")) {
556556 IdxVec Writes;
557557 IdxVec Reads;
558558 findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
583583 }
584584 continue;
585585 }
586 if (!SchedDef->isSubClassOf("Sched")
586 if (SchedDef->isValueUnset("SchedRW")
587587 && (SchedDef->getValueAsDef("Itinerary")->getName() == "NoItinerary")) {
588588 dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n';
589589 }
626626
627627 // If this opcode isn't mapped by the subtarget fallback to the instruction
628628 // definition's SchedRW or ItinDef values.
629 if (Inst.TheDef->isSubClassOf("Sched")) {
629 if (!Inst.TheDef->isValueUnset("SchedRW")) {
630630 RecVec RWs = Inst.TheDef->getValueAsListOfDefs("SchedRW");
631631 return getSchedClassIdx(RWs);
632632 }
718718 // class because that is the fall-back class for other processors.
719719 Record *ItinDef = (*I)->getValueAsDef("Itinerary");
720720 SCIdx = SchedClassIdxMap.lookup(ItinDef->getName());
721 if (!SCIdx && (*I)->isSubClassOf("Sched"))
721 if (!SCIdx && !(*I)->isValueUnset("SchedRW"))
722722 SCIdx = getSchedClassIdx((*I)->getValueAsListOfDefs("SchedRW"));
723723 }
724724 unsigned CIdx = 0, CEnd = ClassInstrs.size();