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AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp Summary: The assembly printing of these is still missing the encoding size suffix, but this will be fixed in a later commit. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249424 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
8 changed file(s) with 106 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
346346 bool ParseSectionDirectiveHSAText();
347347
348348 public:
349 public:
350 enum AMDGPUMatchResultTy {
351 Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
352 };
353
349354 AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
350355 const MCInstrInfo &MII,
351356 const MCTargetOptions &Options)
554559 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
555560 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
556561 return Match_InvalidOperand;
562
563 if ((TSFlags & SIInstrFlags::VOP3) &&
564 (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
565 getForcedEncodingSize() != 64)
566 return Match_PreferE32;
557567
558568 return Match_Success;
559569 }
613623 }
614624 return Error(ErrorLoc, "invalid operand for instruction");
615625 }
626 case Match_PreferE32:
627 return Error(IDLoc, "internal error: instruction without _e64 suffix "
628 "should be encoded as e32");
616629 }
617630 llvm_unreachable("Implement any new match types added!");
618631 }
17001713 }
17011714
17021715 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
1703 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);
1704 unsigned i = 2;
1716
1717 unsigned i = 1;
1718 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
1719 if (Desc.getNumDefs() > 0) {
1720 ((AMDGPUOperand &)*Operands[i++]).addRegOperands(Inst, 1);
1721 }
17051722
17061723 std::map OptionalIdx;
17071724
3636 MIMG = 1 << 18,
3737 FLAT = 1 << 19,
3838 WQM = 1 << 20,
39 VGPRSpill = 1 << 21
39 VGPRSpill = 1 << 21,
40 VOPAsmPrefer32Bit = 1 << 22
4041 };
4142 }
4243
4040 field bits<1> WQM = 0;
4141 field bits<1> VGPRSpill = 0;
4242
43 // This bit tells the assembler to use the 32-bit encoding in case it
44 // is unable to infer the encoding from the operands.
45 field bits<1> VOPAsmPrefer32Bit = 0;
46
4347 // These need to be kept in sync with the enum in SIInstrFlags.
4448 let TSFlags{0} = VM_CNT;
4549 let TSFlags{1} = EXP_CNT;
6771 let TSFlags{19} = FLAT;
6872 let TSFlags{20} = WQM;
6973 let TSFlags{21} = VGPRSpill;
74 let TSFlags{22} = VOPAsmPrefer32Bit;
7075
7176 let SchedRW = [Write32Bit];
7277 }
988988 let ParserMatchClass = InputModsMatchClass;
989989 }
990990
991 class getNumSrcArgs1, ValueType Src2> {
991 class getNumSrcArgs0, ValueType Src1, ValueType Src2> {
992992 int ret =
993 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
993 !if (!eq(Src0.Value, untyped.Value), 0,
994 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
994995 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
995 3)); // VOP3
996 3))); // VOP3
996997 }
997998
998999 // Returns the register class to use for the destination of VOP[123C]
10841085 // Returns the assembly string for the inputs and outputs of a VOP[12C]
10851086 // instruction. This does not add the _e32 suffix, so it can be reused
10861087 // by getAsm64.
1087 class getAsm32 <int NumSrcArgs> {
1088 class getAsm32 <bit HasDst, int NumSrcArgs> {
1089 string dst = "$dst";
1090 string src0 = ", $src0";
10881091 string src1 = ", $src1";
10891092 string src2 = ", $src2";
1090 string ret = "$dst, $src0"#
1091 !if(!eq(NumSrcArgs, 1), "", src1)#
1092 !if(!eq(NumSrcArgs, 3), src2, "");
1093 string ret = !if(HasDst, dst, "") #
1094 !if(!eq(NumSrcArgs, 1), src0, "") #
1095 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1096 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
10931097 }
10941098
10951099 // Returns the assembly string for the inputs and outputs of a VOP3
10961100 // instruction.
1097 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
1101 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
10981102 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
10991103 string src1 = !if(!eq(NumSrcArgs, 1), "",
11001104 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
11021106 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
11031107 string ret =
11041108 !if(!eq(HasModifiers, 0),
1105 getAsm32<NumSrcArgs>.ret,
1109 getAsm32<HasDst, NumSrcArgs>.ret,
11061110 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
11071111 }
11081112
11211125 field RegisterOperand Src1RC64 = getVOP3SrcForVT.ret;
11221126 field RegisterOperand Src2RC64 = getVOP3SrcForVT.ret;
11231127
1124 field bit HasDst32 = !if(!eq(DstVT, untyped), 0, 1);
1125 field int NumSrcArgs = getNumSrcArgs.ret;
1128 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1129 field bit HasDst32 = HasDst;
1130 field int NumSrcArgs = getNumSrcArgs.ret;
11261131 field bit HasModifiers = hasModifiers.ret;
11271132
1128 field dag Outs = (outs DstRC:$dst);
1133 field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
11291134
11301135 // VOP3b instructions are a special case with a second explicit
11311136 // output. This is manually overridden for them.
11361141 field dag Ins64 = getIns64
11371142 HasModifiers>.ret;
11381143
1139 field string Asm32 = getAsm32.ret;
1140 field string Asm64 = getAsm64s>.ret;
1144 field string Asm32 = getAsm32s>.ret;
1145 field string Asm64 = getAsm64.ret;
11411146 }
11421147
11431148 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
11491154 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
11501155 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
11511156 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1157
1158 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
11521159
11531160 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
11541161 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
12451252 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
12461253 let Ins64 = getIns64, 3,
12471254 HasModifiers>.ret;
1248 let Asm32 = getAsm32<2>.ret;
1249 let Asm64 = getAsm64<2, HasModifiers>.ret;
1255 let Asm32 = getAsm32<1, 2>.ret;
1256 let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
12501257 }
12511258 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
12521259 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
14231430 MnemonicAlias {
14241431 let isPseudo = 1;
14251432 let isCodeGenOnly = 1;
1433
1434 field bit vdst;
1435 field bit src0;
14261436 }
14271437
14281438 class VOP3_Real_si op, dag outs, dag ins, string asm, string opName> :
11551155 // VOP1 Instructions
11561156 //===----------------------------------------------------------------------===//
11571157
1158 let vdst = 0, src0 = 0 in {
1159 defm V_NOP : VOP1_m , (outs), (ins), "v_nop", [], "v_nop">;
1158 let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
1159 defm V_NOP : VOP1Inst , "v_nop", VOP_NONE>;
11601160 }
11611161
11621162 let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
13311331 defm V_FREXP_MANT_F32 : VOP1Inst , "v_frexp_mant_f32",
13321332 VOP_F32_F32
13331333 >;
1334 let vdst = 0, src0 = 0 in {
1335 defm V_CLREXCP : VOP1_m , (outs), (ins), "v_clrexcp", [],
1336 "v_clrexcp"
1337 >;
1334 let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
1335 defm V_CLREXCP : VOP1Inst , "v_clrexcp", VOP_NONE>;
13381336 }
13391337 defm V_MOVRELD_B32 : VOP1Inst , "v_movreld_b32", VOP_I32_I32>;
13401338 defm V_MOVRELS_B32 : VOP1Inst , "v_movrels_b32", VOP_I32_I32>;
77 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
88 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
99
10 // Force 32-bit encoding
11
12 // GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
13 v_mov_b32_e32 v1, v2
14
15 // Force 32-bit encoding for special instructions
16 // FIXME: We should be printing _e32 suffixes for these:
17
18 // GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
19 v_nop_e32
20
21 // SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
22 // VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
23 v_clrexcp_e32
24
25 //===----------------------------------------------------------------------===//
26 // Instructions
27 //===----------------------------------------------------------------------===//
28
1029
1130 // GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
1231 v_nop
0 // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
1 // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
2 // XFAIL: *
3
4 // FIXME: We should be printing _e64 suffixes for these.
5 // FIXME: When this is fixed delete this file and fix test case in vop3.s
6
7 v_nop_e64
8 // SICI: v_nop_e64 ; encoding: [0x00,0x00,0x00,0xd3,0x00,0x00,0x00,0x00]
9 // VI: v_nop_e64 ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
10
11 v_clrexcp_e64
12 // SICI: v_clrexcp_e64 ; encoding: [0x00,0x00,0x82,0xd3,0x00,0x00,0x00,0x00]
13 // VI: v_clrexcp_e64 ; encoding: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
117117 // VOP1 Instructions
118118 //===----------------------------------------------------------------------===//
119119
120 // Test forced e64 encoding with e32 operands
121
122 v_mov_b32_e64 v1, v2
123 // SICI: v_mov_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x02,0xd3,0x02,0x01,0x00,0x00]
124 // VI: v_mov_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x41,0xd1,0x02,0x01,0x00,0x00]
125
126 // Force e64 encoding for special instructions.
127 // FIXME, we should be printing the _e64 suffix for v_nop and v_clrexcp.
128
129 v_nop_e64
130 // SICI: v_nop ; encoding: [0x00,0x00,0x00,0xd3,0x00,0x00,0x00,0x00]
131 // VI: v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
132
133 v_clrexcp_e64
134 // SICI: v_clrexcp ; encoding: [0x00,0x00,0x82,0xd3,0x00,0x00,0x00,0x00]
135 // VI: v_clrexcp ; encoding: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
136
120137 //
121138 // Modifier tests:
122139 //