llvm.org GIT mirror llvm / 63b3d71
There shalt be only one "immediate" operand type! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 14 years ago
18 changed file(s) with 51 addition(s) and 86 deletion(s). Raw diff Collapse all Expand all
6161
6262 enum MachineOperandType {
6363 MO_VirtualRegister, // virtual register for *value
64 MO_SignExtendedImmed,
65 MO_UnextendedImmed,
64 MO_Immediate, // Immediate Operand
6665 MO_MachineBasicBlock, // MachineBasicBlock reference
6766 MO_FrameIndex, // Abstract Stack Frame Index
6867 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
159158 /// Accessors that tell you what kind of MachineOperand you're looking at.
160159 ///
161160 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
162 bool isImmediate() const {
163 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
164 }
161 bool isImmediate() const { return opType == MO_Immediate; }
165162 bool isFrameIndex() const { return opType == MO_FrameIndex; }
166163 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
167164 bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
379376 assert(!OperandsComplete() &&
380377 "Trying to add an operand to a machine instr that is already done!");
381378 operands.push_back(
382 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
379 MachineOperand(intValue, MachineOperand::MO_Immediate));
383380 }
384381
385382 /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument
388385 void addZeroExtImm64Operand(uint64_t intValue) {
389386 assert(!OperandsComplete() &&
390387 "Trying to add an operand to a machine instr that is already done!");
391 operands.push_back(
392 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
393 }
394
395 /// addSignExtImmOperand - Add a zero extended constant argument to the
396 /// machine instruction.
397 ///
398 void addSignExtImmOperand(int intValue) {
399 assert(!OperandsComplete() &&
400 "Trying to add an operand to a machine instr that is already done!");
401 operands.push_back(
402 MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed));
388 operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate));
403389 }
404390
405391 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
4343 ///
4444 const MachineInstrBuilder &addImm(int Val) const {
4545 MI->addZeroExtImmOperand(Val);
46 return *this;
47 }
48
49 /// addSImm - Add a new sign extended immediate operand...
50 ///
51 const MachineInstrBuilder &addSImm(int val) const {
52 MI->addSignExtImmOperand(val);
5346 return *this;
5447 }
5548
159159 case MachineOperand::MO_VirtualRegister:
160160 OutputReg(OS, MO.getReg(), MRI);
161161 break;
162 case MachineOperand::MO_SignExtendedImmed:
163 OS << (long)MO.getImmedValue();
164 break;
165 case MachineOperand::MO_UnextendedImmed:
162 case MachineOperand::MO_Immediate:
166163 OS << (long)MO.getImmedValue();
167164 break;
168165 case MachineOperand::MO_MachineBasicBlock:
259256 case MachineOperand::MO_VirtualRegister:
260257 OutputReg(OS, MO.getReg());
261258 break;
262 case MachineOperand::MO_SignExtendedImmed:
263 OS << (long)MO.getImmedValue();
264 break;
265 case MachineOperand::MO_UnextendedImmed:
259 case MachineOperand::MO_Immediate:
266260 OS << (long)MO.getImmedValue();
267261 break;
268262 case MachineOperand::MO_MachineBasicBlock:
9696 O << RI.get(MO.getReg()).Name;
9797 return;
9898
99 case MachineOperand::MO_SignExtendedImmed:
100 case MachineOperand::MO_UnextendedImmed:
99 case MachineOperand::MO_Immediate:
101100 std::cerr << "printOp() does not handle immediate values\n";
102101 abort();
103102 return;
233233 //inst off the SP/FP
234234 //fix up the old:
235235 MI.SetMachineOperandReg(i + 1, Alpha::R28);
236 MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed,
236 MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
237237 getLower16(Offset));
238238 //insert the new
239239 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
240240 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
241241 MBB.insert(II, nMI);
242242 } else {
243 MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
243 MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
244244 }
245245 }
246246
169169 }
170170
171171 void IA64AsmPrinter::printOp(const MachineOperand &MO,
172 bool isBRCALLinsn /* = false */) {
172 bool isBRCALLinsn /* = false */) {
173173 const MRegisterInfo &RI = *TM.getRegisterInfo();
174174 switch (MO.getType()) {
175175 case MachineOperand::MO_VirtualRegister:
176176 O << RI.get(MO.getReg()).Name;
177177 return;
178178
179 case MachineOperand::MO_SignExtendedImmed:
180 case MachineOperand::MO_UnextendedImmed:
181 O << /*(unsigned int)*/MO.getImmedValue();
179 case MachineOperand::MO_Immediate:
180 O << MO.getImmedValue();
182181 return;
183182 case MachineOperand::MO_MachineBasicBlock:
184183 printBasicBlockLabel(MO.getMachineBasicBlock());
2828 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
2929 bool mem = true) {
3030 if (mem)
31 return MIB.addSImm(Offset).addFrameIndex(FI);
31 return MIB.addImm(Offset).addFrameIndex(FI);
3232 else
33 return MIB.addFrameIndex(FI).addSImm(Offset);
33 return MIB.addFrameIndex(FI).addImm(Offset);
3434 }
3535
3636 /// addConstantPoolReference - This function is used to add a reference to the
4242 inline const MachineInstrBuilder&
4343 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
4444 int Offset = 0) {
45 return MIB.addSImm(Offset).addConstantPoolIndex(CPI);
45 return MIB.addImm(Offset).addConstantPoolIndex(CPI);
4646 }
4747
4848 } // End llvm namespace
121121 MachineInstr *New;
122122 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
123123 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
124 .addSImm(-Amount);
124 .addImm(-Amount);
125125 } else {
126126 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
127127 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
128 .addSImm(Amount);
128 .addImm(Amount);
129129 }
130130
131131 // Replace the pseudo instruction with a new instruction...
172172 // (the bundler wants to know this)
173173 //insert the new
174174 MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
175 .addReg(BaseRegister).addSImm(Offset);
175 .addReg(BaseRegister).addImm(Offset);
176176 MBB.insert(II, nMI);
177177 } else { // it's big
178178 //fix up the old:
180180 MI.getOperand(i).setUse(); // mark r22 as being used
181181 // (the bundler wants to know this)
182182 MachineInstr* nMI;
183 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
183 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
184184 MBB.insert(II, nMI);
185185 nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
186186 .addReg(IA64::r22);
271271 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
272272 MBB.insert(MBBI, MI);
273273 } else { // we use r22 as a scratch register here
274 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
274 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
275275 // FIXME: MOVLSI32 expects a _u_32imm
276276 MBB.insert(MBBI, MI); // first load the decrement into r22
277277 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
355355 O << RI.get(MO.getReg()).Name;
356356 return;
357357
358 case MachineOperand::MO_SignExtendedImmed:
359 case MachineOperand::MO_UnextendedImmed:
358 case MachineOperand::MO_Immediate:
360359 std::cerr << "printOp() does not handle immediate values\n";
361360 abort();
362361 return;
130130 if (Displacement >= -32768 && Displacement <= 32767) {
131131 BuildMI(*MBB, MBBJ, Opcode, 2).addReg(CRReg).addMBB(trueMBB);
132132 } else {
133 BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8);
133 BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addImm(8);
134134 BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB);
135135 }
136136
3232 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
3333 bool mem = true) {
3434 if (mem)
35 return MIB.addSImm(Offset).addFrameIndex(FI);
35 return MIB.addImm(Offset).addFrameIndex(FI);
3636 else
37 return MIB.addFrameIndex(FI).addSImm(Offset);
37 return MIB.addFrameIndex(FI).addImm(Offset);
3838 }
3939
4040 /// addConstantPoolReference - This function is used to add a reference to the
4646 inline const MachineInstrBuilder&
4747 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
4848 int Offset = 0) {
49 return MIB.addSImm(Offset).addConstantPoolIndex(CPI);
49 return MIB.addImm(Offset).addConstantPoolIndex(CPI);
5050 }
5151
5252 } // End llvm namespace
268268
269269 // Replace the pseudo instruction with a new instruction...
270270 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
271 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
271 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
272272 } else {
273273 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
274 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
274 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
275275 }
276276 }
277277 }
310310 if (Offset > 32767 || Offset < -32768) {
311311 // Insert a set of r0 with the full offset value before the ld, st, or add
312312 MachineBasicBlock *MBB = MI.getParent();
313 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
313 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
314314 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
315315
316316 // convert into indexed form of the instruction
332332 Offset >>= 2; // The actual encoded value has the low two bits zero.
333333 break;
334334 }
335 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
336 Offset);
335 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
337336 }
338337 }
339338
510509 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
511510 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
512511 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
513 .addSImm(MaxAlign-NumBytes);
512 .addImm(MaxAlign-NumBytes);
514513 BuildMI(MBB, MBBI, PPC::STWUX, 3)
515514 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
516515 } else if (NumBytes <= 32768) {
517 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
516 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
518517 .addReg(PPC::R1);
519518 } else {
520 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
519 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
521520 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
522521 .addImm(NegNumbytes & 0xFFFF);
523522 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
533532 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
534533 Moves.push_back(new MachineMove(LabelID, Dst, Src));
535534
536 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
535 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
537536 }
538537
539538 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
540539 if (HasFP) {
541540 BuildMI(MBB, MBBI, PPC::STW, 3)
542 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
541 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
543542 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
544543 }
545544 }
563562 // its stack slot.
564563 if (hasFP(MF)) {
565564 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
566 .addSImm(GPRSize).addReg(PPC::R31);
565 .addImm(GPRSize).addReg(PPC::R31);
567566 }
568567
569568 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
570569 // on entry to the function. Add this offset back now.
571570 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
572571 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
573 .addReg(PPC::R1).addSImm(NumBytes);
572 .addReg(PPC::R1).addImm(NumBytes);
574573 } else {
575 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
574 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
576575 }
577576 }
578577 }
152152 O << "%reg" << MO.getReg();
153153 break;
154154
155 case MachineOperand::MO_SignExtendedImmed:
156 case MachineOperand::MO_UnextendedImmed:
155 case MachineOperand::MO_Immediate:
157156 O << (int)MO.getImmedValue();
158157 break;
159158 case MachineOperand::MO_MachineBasicBlock:
191190 if (OpTy == MachineOperand::MO_VirtualRegister &&
192191 MI->getOperand(opNum+1).getReg() == SP::G0)
193192 return; // don't print "+%g0"
194 if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
195 OpTy == MachineOperand::MO_UnextendedImmed) &&
193 if (OpTy == MachineOperand::MO_Immediate &&
196194 MI->getOperand(opNum+1).getImmedValue() == 0)
197195 return; // don't print "+0"
198196
110110 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
111111 Size = -Size;
112112 if (Size)
113 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size);
113 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
114114 MBB.erase(I);
115115 }
116116
135135 // If the offset is small enough to fit in the immediate field, directly
136136 // encode it.
137137 MI.SetMachineOperandReg(i, SP::I6);
138 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
138 MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
139139 } else {
140140 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
141141 // scavenge a register here instead of reserving G1 all of the time.
146146 SP::G1).addReg(SP::G1).addReg(SP::I6);
147147 // Insert: G1+%lo(offset) into the user.
148148 MI.SetMachineOperandReg(i, SP::G1);
149 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
149 MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
150150 Offset & ((1 << 10)-1));
151151 }
152152 }
115115 O << (char)tolower(*Name);
116116 return;
117117
118 case MachineOperand::MO_SignExtendedImmed:
119 case MachineOperand::MO_UnextendedImmed:
118 case MachineOperand::MO_Immediate:
120119 if (!Modifier || strcmp(Modifier, "debug") != 0)
121120 O << '$';
122121 O << (int)MO.getImmedValue();
6060 unsigned Reg) {
6161 // Because memory references are always represented with four
6262 // values, this adds: Reg, [1, NoReg, 0] to the instruction.
63 return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(0);
63 return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0);
6464 }
6565
6666
7070 ///
7171 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
7272 unsigned Reg, int Offset) {
73 return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(Offset);
73 return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset);
7474 }
7575
7676 /// addRegReg - This function is used to add a memory reference of the form:
7777 /// [Reg + Reg].
7878 inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
7979 unsigned Reg1, unsigned Reg2) {
80 return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addSImm(0);
80 return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0);
8181 }
8282
8383 inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
9494 if (AM.GV)
9595 return MIB.addGlobalAddress(AM.GV, AM.Disp);
9696 else
97 return MIB.addSImm(AM.Disp);
97 return MIB.addImm(AM.Disp);
9898 }
9999
100100 /// addFrameReference - This function is used to add a reference to the base of
104104 ///
105105 inline const MachineInstrBuilder &
106106 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
107 return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addSImm(Offset);
107 return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset);
108108 }
109109
110110 /// addConstantPoolReference - This function is used to add a reference to the
116116 inline const MachineInstrBuilder &
117117 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
118118 int Offset = 0) {
119 return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset);
119 return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset);
120120 }
121121
122122 } // End llvm namespace
106106 O << "reg" << MO.getReg();
107107 return;
108108
109 case MachineOperand::MO_SignExtendedImmed:
110 case MachineOperand::MO_UnextendedImmed:
109 case MachineOperand::MO_Immediate:
111110 O << (int)MO.getImmedValue();
112111 return;
113112 case MachineOperand::MO_MachineBasicBlock:
675675 else
676676 Offset += 4; // Skip the saved EBP
677677
678 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
678 MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
679679 }
680680
681681 void