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[ARM] Add MVE integer vector min/max instructions. Summary: These form a small family of their own, to go with the floating-point VMINNM/VMAXNM instructions added in a previous commit. They introduce the first of many special cases in the mnemonic recognition code, because VMIN with the E suffix used by the VPT predication system needs to avoid being interpreted as the nonexistent instruction 'VMI' with an ordinary 'NE' condition suffix. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363695 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
4 changed file(s) with 134 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
641641 def MVE_VMINNMf32 : MVE_VMINMAXNM<"vminnm", "f32", 0b0, 0b1>;
642642 def MVE_VMINNMf16 : MVE_VMINMAXNM<"vminnm", "f16", 0b1, 0b1>;
643643
644 class MVE_VMINMAX size,
645 bit bit_4, list pattern=[]>
646 : MVE_comp {
647
648 let Inst{28} = U;
649 let Inst{25-24} = 0b11;
650 let Inst{23} = 0b0;
651 let Inst{21-20} = size{1-0};
652 let Inst{11} = 0b0;
653 let Inst{8} = 0b0;
654 let Inst{6} = 0b1;
655 let Inst{4} = bit_4;
656 }
657
658 multiclass MVE_VMINMAX_all_sizes {
659 def s8 : MVE_VMINMAX;
660 def s16 : MVE_VMINMAX;
661 def s32 : MVE_VMINMAX;
662 def u8 : MVE_VMINMAX;
663 def u16 : MVE_VMINMAX;
664 def u32 : MVE_VMINMAX;
665 }
666
667 defm MVE_VMAX : MVE_VMINMAX_all_sizes<"vmax", 0b0>;
668 defm MVE_VMIN : MVE_VMINMAX_all_sizes<"vmin", 0b1>;
669
644670 // end of mve_comp instructions
645671
646672 class MVE_VPT size, dag iops, string asm, list pattern=[]>
59325932 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
59335933 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
59345934 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5935 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5935 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
5936 !(hasMVE() && Mnemonic == "vmine")) {
59365937 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59375938 if (CC != ~0U) {
59385939 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1212 # CHECK-NOFP-NOT: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
1313 # ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
1414 vminnm.f16 q3, q0, q1
15
16 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
17 # CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
18 vmin.s8 q3, q0, q7
19
20 # CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
21 # CHECK-NOFP: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
22 vmin.s16 q0, q1, q2
23
24 # CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
25 # CHECK-NOFP: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
26 vmin.s32 q0, q1, q2
27
28 # CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
29 # CHECK-NOFP: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
30 vmin.u8 q0, q1, q2
31
32 # CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
33 # CHECK-NOFP: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
34 vmin.u16 q0, q1, q2
35
36 # CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
37 # CHECK-NOFP: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
38 vmin.u32 q0, q1, q2
39
40 # CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
41 # CHECK-NOFP: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
42 vmax.s8 q3, q0, q7
43
44 # CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
45 # CHECK-NOFP: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
46 vmax.s16 q0, q1, q2
47
48 # CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
49 # CHECK-NOFP: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
50 vmax.s32 q0, q1, q2
51
52 # CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
53 # CHECK-NOFP: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
54 vmax.u8 q0, q1, q2
55
56 # CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
57 # CHECK-NOFP: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
58 vmax.u16 q0, q1, q2
59
60 # CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
61 # CHECK-NOFP: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
62 vmax.u32 q0, q1, q2
63
64 vpste
65 vmint.s8 q0, q1, q2
66 vmine.s16 q0, q1, q2
67 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
68 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
69 # CHECK: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
70 # CHECK-NOFP: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
71 # CHECK: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
72 # CHECK-NOFP: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
88 # CHECK: vminnm.f16 q3, q0, q1 @ encoding: [0x30,0xff,0x52,0x6f]
99 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
1010 [0x30,0xff,0x52,0x6f]
11
12 # CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0x00,0xef,0x5e,0x66]
15
16 # CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0x12,0xef,0x54,0x06]
19
20 # CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0x22,0xef,0x54,0x06]
23
24 # CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0x02,0xff,0x54,0x06]
27
28 # CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0x12,0xff,0x54,0x06]
31
32 # CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0x22,0xff,0x54,0x06]
35
36 # CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x00,0xef,0x4e,0x66]
39
40 # CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0x12,0xef,0x44,0x06]
43
44 # CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x22,0xef,0x44,0x06]
47
48 # CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0x02,0xff,0x44,0x06]
51
52 # CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x12,0xff,0x44,0x06]
55
56 # CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x22,0xff,0x44,0x06]