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[X86] Add BMI1 scheduling tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308135 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
1 changed file(s) with 428 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mattr=+bmi | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
7
8 define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) {
9 ; GENERIC-LABEL: test_andn_i16:
10 ; GENERIC: # BB#0:
11 ; GENERIC-NEXT: andnl %esi, %edi, %eax
12 ; GENERIC-NEXT: notl %edi
13 ; GENERIC-NEXT: andw (%rdx), %di
14 ; GENERIC-NEXT: addl %edi, %eax
15 ; GENERIC-NEXT: # kill: %AX %AX %EAX
16 ; GENERIC-NEXT: retq
17 ;
18 ; HASWELL-LABEL: test_andn_i16:
19 ; HASWELL: # BB#0:
20 ; HASWELL-NEXT: andnl %esi, %edi, %eax # sched: [1:0.50]
21 ; HASWELL-NEXT: notl %edi # sched: [1:0.25]
22 ; HASWELL-NEXT: andw (%rdx), %di # sched: [5:0.50]
23 ; HASWELL-NEXT: addl %edi, %eax # sched: [1:0.25]
24 ; HASWELL-NEXT: # kill: %AX %AX %EAX
25 ; HASWELL-NEXT: retq # sched: [1:1.00]
26 ;
27 ; BTVER2-LABEL: test_andn_i16:
28 ; BTVER2: # BB#0:
29 ; BTVER2-NEXT: andnl %esi, %edi, %eax # sched: [1:0.50]
30 ; BTVER2-NEXT: notl %edi # sched: [1:0.50]
31 ; BTVER2-NEXT: andw (%rdx), %di # sched: [4:1.00]
32 ; BTVER2-NEXT: addl %edi, %eax # sched: [1:0.50]
33 ; BTVER2-NEXT: # kill: %AX %AX %EAX
34 ; BTVER2-NEXT: retq # sched: [4:1.00]
35 %1 = load i16, i16 *%a2
36 %2 = xor i16 %a0, -1
37 %3 = and i16 %2, %a1
38 %4 = and i16 %2, %1
39 %5 = add i16 %3, %4
40 ret i16 %5
41 }
42
43 define i32 @test_andn_i32(i32 %a0, i32 %a1, i32 *%a2) {
44 ; GENERIC-LABEL: test_andn_i32:
45 ; GENERIC: # BB#0:
46 ; GENERIC-NEXT: andnl %esi, %edi, %ecx
47 ; GENERIC-NEXT: andnl (%rdx), %edi, %eax
48 ; GENERIC-NEXT: addl %ecx, %eax
49 ; GENERIC-NEXT: retq
50 ;
51 ; HASWELL-LABEL: test_andn_i32:
52 ; HASWELL: # BB#0:
53 ; HASWELL-NEXT: andnl %esi, %edi, %ecx # sched: [1:0.50]
54 ; HASWELL-NEXT: andnl (%rdx), %edi, %eax # sched: [4:0.50]
55 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
56 ; HASWELL-NEXT: retq # sched: [1:1.00]
57 ;
58 ; BTVER2-LABEL: test_andn_i32:
59 ; BTVER2: # BB#0:
60 ; BTVER2-NEXT: andnl (%rdx), %edi, %eax # sched: [4:1.00]
61 ; BTVER2-NEXT: andnl %esi, %edi, %ecx # sched: [1:0.50]
62 ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
63 ; BTVER2-NEXT: retq # sched: [4:1.00]
64 %1 = load i32, i32 *%a2
65 %2 = xor i32 %a0, -1
66 %3 = and i32 %2, %a1
67 %4 = and i32 %2, %1
68 %5 = add i32 %3, %4
69 ret i32 %5
70 }
71
72 define i64 @test_andn_i64(i64 %a0, i64 %a1, i64 *%a2) {
73 ; GENERIC-LABEL: test_andn_i64:
74 ; GENERIC: # BB#0:
75 ; GENERIC-NEXT: andnq %rsi, %rdi, %rcx
76 ; GENERIC-NEXT: andnq (%rdx), %rdi, %rax
77 ; GENERIC-NEXT: addq %rcx, %rax
78 ; GENERIC-NEXT: retq
79 ;
80 ; HASWELL-LABEL: test_andn_i64:
81 ; HASWELL: # BB#0:
82 ; HASWELL-NEXT: andnq %rsi, %rdi, %rcx # sched: [1:0.50]
83 ; HASWELL-NEXT: andnq (%rdx), %rdi, %rax # sched: [4:0.50]
84 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
85 ; HASWELL-NEXT: retq # sched: [1:1.00]
86 ;
87 ; BTVER2-LABEL: test_andn_i64:
88 ; BTVER2: # BB#0:
89 ; BTVER2-NEXT: andnq (%rdx), %rdi, %rax # sched: [4:1.00]
90 ; BTVER2-NEXT: andnq %rsi, %rdi, %rcx # sched: [1:0.50]
91 ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
92 ; BTVER2-NEXT: retq # sched: [4:1.00]
93 %1 = load i64, i64 *%a2
94 %2 = xor i64 %a0, -1
95 %3 = and i64 %2, %a1
96 %4 = and i64 %2, %1
97 %5 = add i64 %3, %4
98 ret i64 %5
99 }
100
101 define i32 @test_bextr_i32(i32 %a0, i32 %a1, i32 *%a2) {
102 ; GENERIC-LABEL: test_bextr_i32:
103 ; GENERIC: # BB#0:
104 ; GENERIC-NEXT: bextrl %edi, (%rdx), %ecx
105 ; GENERIC-NEXT: bextrl %edi, %esi, %eax
106 ; GENERIC-NEXT: addl %ecx, %eax
107 ; GENERIC-NEXT: retq
108 ;
109 ; HASWELL-LABEL: test_bextr_i32:
110 ; HASWELL: # BB#0:
111 ; HASWELL-NEXT: bextrl %edi, (%rdx), %ecx # sched: [6:0.50]
112 ; HASWELL-NEXT: bextrl %edi, %esi, %eax # sched: [2:0.50]
113 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
114 ; HASWELL-NEXT: retq # sched: [1:1.00]
115 ;
116 ; BTVER2-LABEL: test_bextr_i32:
117 ; BTVER2: # BB#0:
118 ; BTVER2-NEXT: bextrl %edi, (%rdx), %ecx # sched: [?:0.000000e+00]
119 ; BTVER2-NEXT: bextrl %edi, %esi, %eax # sched: [?:0.000000e+00]
120 ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
121 ; BTVER2-NEXT: retq # sched: [4:1.00]
122 %1 = load i32, i32 *%a2
123 %2 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %1, i32 %a0)
124 %3 = tail call i32 @llvm.x86.bmi.bextr.32(i32 %a1, i32 %a0)
125 %4 = add i32 %2, %3
126 ret i32 %4
127 }
128 declare i32 @llvm.x86.bmi.bextr.32(i32, i32)
129
130 define i64 @test_bextr_i64(i64 %a0, i64 %a1, i64 *%a2) {
131 ; GENERIC-LABEL: test_bextr_i64:
132 ; GENERIC: # BB#0:
133 ; GENERIC-NEXT: bextrq %rdi, (%rdx), %rcx
134 ; GENERIC-NEXT: bextrq %rdi, %rsi, %rax
135 ; GENERIC-NEXT: addq %rcx, %rax
136 ; GENERIC-NEXT: retq
137 ;
138 ; HASWELL-LABEL: test_bextr_i64:
139 ; HASWELL: # BB#0:
140 ; HASWELL-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [6:0.50]
141 ; HASWELL-NEXT: bextrq %rdi, %rsi, %rax # sched: [2:0.50]
142 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
143 ; HASWELL-NEXT: retq # sched: [1:1.00]
144 ;
145 ; BTVER2-LABEL: test_bextr_i64:
146 ; BTVER2: # BB#0:
147 ; BTVER2-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [?:0.000000e+00]
148 ; BTVER2-NEXT: bextrq %rdi, %rsi, %rax # sched: [?:0.000000e+00]
149 ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
150 ; BTVER2-NEXT: retq # sched: [4:1.00]
151 %1 = load i64, i64 *%a2
152 %2 = tail call i64 @llvm.x86.bmi.bextr.64(i64 %1, i64 %a0)
153 %3 = tail call i64 @llvm.x86.bmi.bextr.64(i64 %a1, i64 %a0)
154 %4 = add i64 %2, %3
155 ret i64 %4
156 }
157 declare i64 @llvm.x86.bmi.bextr.64(i64, i64)
158
159 define i32 @test_blsi_i32(i32 %a0, i32 *%a1) {
160 ; GENERIC-LABEL: test_blsi_i32:
161 ; GENERIC: # BB#0:
162 ; GENERIC-NEXT: blsil (%rsi), %ecx
163 ; GENERIC-NEXT: blsil %edi, %eax
164 ; GENERIC-NEXT: addl %ecx, %eax
165 ; GENERIC-NEXT: retq
166 ;
167 ; HASWELL-LABEL: test_blsi_i32:
168 ; HASWELL: # BB#0:
169 ; HASWELL-NEXT: blsil (%rsi), %ecx # sched: [4:0.50]
170 ; HASWELL-NEXT: blsil %edi, %eax # sched: [1:0.50]
171 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
172 ; HASWELL-NEXT: retq # sched: [1:1.00]
173 ;
174 ; BTVER2-LABEL: test_blsi_i32:
175 ; BTVER2: # BB#0:
176 ; BTVER2-NEXT: blsil (%rsi), %ecx # sched: [?:0.000000e+00]
177 ; BTVER2-NEXT: blsil %edi, %eax # sched: [?:0.000000e+00]
178 ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
179 ; BTVER2-NEXT: retq # sched: [4:1.00]
180 %1 = load i32, i32 *%a1
181 %2 = sub i32 0, %1
182 %3 = sub i32 0, %a0
183 %4 = and i32 %1, %2
184 %5 = and i32 %a0, %3
185 %6 = add i32 %4, %5
186 ret i32 %6
187 }
188
189 define i64 @test_blsi_i64(i64 %a0, i64 *%a1) {
190 ; GENERIC-LABEL: test_blsi_i64:
191 ; GENERIC: # BB#0:
192 ; GENERIC-NEXT: blsiq (%rsi), %rcx
193 ; GENERIC-NEXT: blsiq %rdi, %rax
194 ; GENERIC-NEXT: addq %rcx, %rax
195 ; GENERIC-NEXT: retq
196 ;
197 ; HASWELL-LABEL: test_blsi_i64:
198 ; HASWELL: # BB#0:
199 ; HASWELL-NEXT: blsiq (%rsi), %rcx # sched: [4:0.50]
200 ; HASWELL-NEXT: blsiq %rdi, %rax # sched: [1:0.50]
201 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
202 ; HASWELL-NEXT: retq # sched: [1:1.00]
203 ;
204 ; BTVER2-LABEL: test_blsi_i64:
205 ; BTVER2: # BB#0:
206 ; BTVER2-NEXT: blsiq (%rsi), %rcx # sched: [?:0.000000e+00]
207 ; BTVER2-NEXT: blsiq %rdi, %rax # sched: [?:0.000000e+00]
208 ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
209 ; BTVER2-NEXT: retq # sched: [4:1.00]
210 %1 = load i64, i64 *%a1
211 %2 = sub i64 0, %1
212 %3 = sub i64 0, %a0
213 %4 = and i64 %1, %2
214 %5 = and i64 %a0, %3
215 %6 = add i64 %4, %5
216 ret i64 %6
217 }
218
219 define i32 @test_blsmsk_i32(i32 %a0, i32 *%a1) {
220 ; GENERIC-LABEL: test_blsmsk_i32:
221 ; GENERIC: # BB#0:
222 ; GENERIC-NEXT: blsmskl (%rsi), %ecx
223 ; GENERIC-NEXT: blsmskl %edi, %eax
224 ; GENERIC-NEXT: addl %ecx, %eax
225 ; GENERIC-NEXT: retq
226 ;
227 ; HASWELL-LABEL: test_blsmsk_i32:
228 ; HASWELL: # BB#0:
229 ; HASWELL-NEXT: blsmskl (%rsi), %ecx # sched: [4:0.50]
230 ; HASWELL-NEXT: blsmskl %edi, %eax # sched: [1:0.50]
231 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
232 ; HASWELL-NEXT: retq # sched: [1:1.00]
233 ;
234 ; BTVER2-LABEL: test_blsmsk_i32:
235 ; BTVER2: # BB#0:
236 ; BTVER2-NEXT: blsmskl (%rsi), %ecx # sched: [?:0.000000e+00]
237 ; BTVER2-NEXT: blsmskl %edi, %eax # sched: [?:0.000000e+00]
238 ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
239 ; BTVER2-NEXT: retq # sched: [4:1.00]
240 %1 = load i32, i32 *%a1
241 %2 = sub i32 %1, 1
242 %3 = sub i32 %a0, 1
243 %4 = xor i32 %1, %2
244 %5 = xor i32 %a0, %3
245 %6 = add i32 %4, %5
246 ret i32 %6
247 }
248
249 define i64 @test_blsmsk_i64(i64 %a0, i64 *%a1) {
250 ; GENERIC-LABEL: test_blsmsk_i64:
251 ; GENERIC: # BB#0:
252 ; GENERIC-NEXT: blsmskq (%rsi), %rcx
253 ; GENERIC-NEXT: blsmskq %rdi, %rax
254 ; GENERIC-NEXT: addq %rcx, %rax
255 ; GENERIC-NEXT: retq
256 ;
257 ; HASWELL-LABEL: test_blsmsk_i64:
258 ; HASWELL: # BB#0:
259 ; HASWELL-NEXT: blsmskq (%rsi), %rcx # sched: [4:0.50]
260 ; HASWELL-NEXT: blsmskq %rdi, %rax # sched: [1:0.50]
261 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
262 ; HASWELL-NEXT: retq # sched: [1:1.00]
263 ;
264 ; BTVER2-LABEL: test_blsmsk_i64:
265 ; BTVER2: # BB#0:
266 ; BTVER2-NEXT: blsmskq (%rsi), %rcx # sched: [?:0.000000e+00]
267 ; BTVER2-NEXT: blsmskq %rdi, %rax # sched: [?:0.000000e+00]
268 ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
269 ; BTVER2-NEXT: retq # sched: [4:1.00]
270 %1 = load i64, i64 *%a1
271 %2 = sub i64 %1, 1
272 %3 = sub i64 %a0, 1
273 %4 = xor i64 %1, %2
274 %5 = xor i64 %a0, %3
275 %6 = add i64 %4, %5
276 ret i64 %6
277 }
278
279 define i32 @test_blsr_i32(i32 %a0, i32 *%a1) {
280 ; GENERIC-LABEL: test_blsr_i32:
281 ; GENERIC: # BB#0:
282 ; GENERIC-NEXT: blsrl (%rsi), %ecx
283 ; GENERIC-NEXT: blsrl %edi, %eax
284 ; GENERIC-NEXT: addl %ecx, %eax
285 ; GENERIC-NEXT: retq
286 ;
287 ; HASWELL-LABEL: test_blsr_i32:
288 ; HASWELL: # BB#0:
289 ; HASWELL-NEXT: blsrl (%rsi), %ecx # sched: [4:0.50]
290 ; HASWELL-NEXT: blsrl %edi, %eax # sched: [1:0.50]
291 ; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
292 ; HASWELL-NEXT: retq # sched: [1:1.00]
293 ;
294 ; BTVER2-LABEL: test_blsr_i32:
295 ; BTVER2: # BB#0:
296 ; BTVER2-NEXT: blsrl (%rsi), %ecx # sched: [?:0.000000e+00]
297 ; BTVER2-NEXT: blsrl %edi, %eax # sched: [?:0.000000e+00]
298 ; BTVER2-NEXT: addl %ecx, %eax # sched: [1:0.50]
299 ; BTVER2-NEXT: retq # sched: [4:1.00]
300 %1 = load i32, i32 *%a1
301 %2 = sub i32 %1, 1
302 %3 = sub i32 %a0, 1
303 %4 = and i32 %1, %2
304 %5 = and i32 %a0, %3
305 %6 = add i32 %4, %5
306 ret i32 %6
307 }
308
309 define i64 @test_blsr_i64(i64 %a0, i64 *%a1) {
310 ; GENERIC-LABEL: test_blsr_i64:
311 ; GENERIC: # BB#0:
312 ; GENERIC-NEXT: blsrq (%rsi), %rcx
313 ; GENERIC-NEXT: blsrq %rdi, %rax
314 ; GENERIC-NEXT: addq %rcx, %rax
315 ; GENERIC-NEXT: retq
316 ;
317 ; HASWELL-LABEL: test_blsr_i64:
318 ; HASWELL: # BB#0:
319 ; HASWELL-NEXT: blsrq (%rsi), %rcx # sched: [4:0.50]
320 ; HASWELL-NEXT: blsrq %rdi, %rax # sched: [1:0.50]
321 ; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
322 ; HASWELL-NEXT: retq # sched: [1:1.00]
323 ;
324 ; BTVER2-LABEL: test_blsr_i64:
325 ; BTVER2: # BB#0:
326 ; BTVER2-NEXT: blsrq (%rsi), %rcx # sched: [?:0.000000e+00]
327 ; BTVER2-NEXT: blsrq %rdi, %rax # sched: [?:0.000000e+00]
328 ; BTVER2-NEXT: addq %rcx, %rax # sched: [1:0.50]
329 ; BTVER2-NEXT: retq # sched: [4:1.00]
330 %1 = load i64, i64 *%a1
331 %2 = sub i64 %1, 1
332 %3 = sub i64 %a0, 1
333 %4 = and i64 %1, %2
334 %5 = and i64 %a0, %3
335 %6 = add i64 %4, %5
336 ret i64 %6
337 }
338
339 define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) {
340 ; GENERIC-LABEL: test_cttz_i16:
341 ; GENERIC: # BB#0:
342 ; GENERIC-NEXT: tzcntw (%rsi), %cx
343 ; GENERIC-NEXT: tzcntw %di, %ax
344 ; GENERIC-NEXT: orl %ecx, %eax
345 ; GENERIC-NEXT: # kill: %AX %AX %EAX
346 ; GENERIC-NEXT: retq
347 ;
348 ; HASWELL-LABEL: test_cttz_i16:
349 ; HASWELL: # BB#0:
350 ; HASWELL-NEXT: tzcntw (%rsi), %cx # sched: [7:1.00]
351 ; HASWELL-NEXT: tzcntw %di, %ax # sched: [3:1.00]
352 ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
353 ; HASWELL-NEXT: # kill: %AX %AX %EAX
354 ; HASWELL-NEXT: retq # sched: [1:1.00]
355 ;
356 ; BTVER2-LABEL: test_cttz_i16:
357 ; BTVER2: # BB#0:
358 ; BTVER2-NEXT: tzcntw (%rsi), %cx # sched: [?:0.000000e+00]
359 ; BTVER2-NEXT: tzcntw %di, %ax # sched: [?:0.000000e+00]
360 ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
361 ; BTVER2-NEXT: # kill: %AX %AX %EAX
362 ; BTVER2-NEXT: retq # sched: [4:1.00]
363 %1 = load i16, i16 *%a1
364 %2 = tail call i16 @llvm.cttz.i16( i16 %1, i1 false )
365 %3 = tail call i16 @llvm.cttz.i16( i16 %a0, i1 false )
366 %4 = or i16 %2, %3
367 ret i16 %4
368 }
369 declare i16 @llvm.cttz.i16(i16, i1)
370
371 define i32 @test_cttz_i32(i32 %a0, i32 *%a1) {
372 ; GENERIC-LABEL: test_cttz_i32:
373 ; GENERIC: # BB#0:
374 ; GENERIC-NEXT: tzcntl (%rsi), %ecx
375 ; GENERIC-NEXT: tzcntl %edi, %eax
376 ; GENERIC-NEXT: orl %ecx, %eax
377 ; GENERIC-NEXT: retq
378 ;
379 ; HASWELL-LABEL: test_cttz_i32:
380 ; HASWELL: # BB#0:
381 ; HASWELL-NEXT: tzcntl (%rsi), %ecx # sched: [7:1.00]
382 ; HASWELL-NEXT: tzcntl %edi, %eax # sched: [3:1.00]
383 ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
384 ; HASWELL-NEXT: retq # sched: [1:1.00]
385 ;
386 ; BTVER2-LABEL: test_cttz_i32:
387 ; BTVER2: # BB#0:
388 ; BTVER2-NEXT: tzcntl (%rsi), %ecx # sched: [?:0.000000e+00]
389 ; BTVER2-NEXT: tzcntl %edi, %eax # sched: [?:0.000000e+00]
390 ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
391 ; BTVER2-NEXT: retq # sched: [4:1.00]
392 %1 = load i32, i32 *%a1
393 %2 = tail call i32 @llvm.cttz.i32( i32 %1, i1 false )
394 %3 = tail call i32 @llvm.cttz.i32( i32 %a0, i1 false )
395 %4 = or i32 %2, %3
396 ret i32 %4
397 }
398 declare i32 @llvm.cttz.i32(i32, i1)
399
400 define i64 @test_cttz_i64(i64 %a0, i64 *%a1) {
401 ; GENERIC-LABEL: test_cttz_i64:
402 ; GENERIC: # BB#0:
403 ; GENERIC-NEXT: tzcntq (%rsi), %rcx
404 ; GENERIC-NEXT: tzcntq %rdi, %rax
405 ; GENERIC-NEXT: orq %rcx, %rax
406 ; GENERIC-NEXT: retq
407 ;
408 ; HASWELL-LABEL: test_cttz_i64:
409 ; HASWELL: # BB#0:
410 ; HASWELL-NEXT: tzcntq (%rsi), %rcx # sched: [7:1.00]
411 ; HASWELL-NEXT: tzcntq %rdi, %rax # sched: [3:1.00]
412 ; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
413 ; HASWELL-NEXT: retq # sched: [1:1.00]
414 ;
415 ; BTVER2-LABEL: test_cttz_i64:
416 ; BTVER2: # BB#0:
417 ; BTVER2-NEXT: tzcntq (%rsi), %rcx # sched: [?:0.000000e+00]
418 ; BTVER2-NEXT: tzcntq %rdi, %rax # sched: [?:0.000000e+00]
419 ; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
420 ; BTVER2-NEXT: retq # sched: [4:1.00]
421 %1 = load i64, i64 *%a1
422 %2 = tail call i64 @llvm.cttz.i64( i64 %1, i1 false )
423 %3 = tail call i64 @llvm.cttz.i64( i64 %a0, i1 false )
424 %4 = or i64 %2, %3
425 ret i64 %4
426 }
427 declare i64 @llvm.cttz.i64(i64, i1)