llvm.org GIT mirror llvm / 621d157
Fix a sub-register indice propagation bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49832 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
2 changed file(s) with 47 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
456456 MachineOperand &O = I.getOperand();
457457 MachineInstr *UseMI = &*I;
458458 ++I;
459 unsigned OldSubIdx = O.getSubReg();
459460 if (DstIsPhys) {
460 unsigned UseSubIdx = O.getSubReg();
461461 unsigned UseDstReg = DstReg;
462 if (UseSubIdx)
463 UseDstReg = tri_->getSubReg(DstReg, UseSubIdx);
462 if (OldSubIdx)
463 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
464464 O.setReg(UseDstReg);
465465 O.setSubReg(0);
466466 } else {
467 unsigned OldSubIdx = O.getSubReg();
468467 // Sub-register indexes goes from small to large. e.g.
469468 // RAX: 0 -> AL, 1 -> AH, 2 -> AX, 3 -> EAX
470469 // EAX: 0 -> AL, 1 -> AH, 2 -> AX
848847 if (SrcIsPhys && isExtSubReg) {
849848 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
850849 // coalesced with AX.
851 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
850 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
851 assert(!DstSubIdx || DstSubIdx == SubIdx);
852 if (DstSubIdx != SubIdx)
853 // r1024<2> = EXTRACT_SUBREG EAX, 0. Then r1024 has already been
854 // coalesced to an INSERT_SUBREG so the subreg indices cancel out.
855 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
852856 SubIdx = 0;
853857 } else if (DstIsPhys && isInsSubReg) {
854858 // EAX = INSERT_SUBREG EAX, r1024, 0
859 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
860 assert(!SrcSubIdx || SrcSubIdx == SubIdx);
861 if (SrcSubIdx != SubIdx)
862 // EAX = INSERT_SUBREG EAX, r1024<2>, 0 Then r1024 has already been
863 // coalesced to an EXTRACT_SUBREG so the subreg indices cancel out.
855864 DstReg = tri_->getSubReg(DstReg, SubIdx);
856865 SubIdx = 0;
857866 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
0 ; RUN: llvm-as < %s | llc -march=x86
1
2 define void @Hubba(i8* %saveunder, i32 %firstBlob, i32 %select) nounwind {
3 entry:
4 br i1 false, label %bb53.us, label %bb53
5 bb53.us: ; preds = %bb94.us, %bb53.us, %entry
6 switch i8 1, label %bb71.us [
7 i8 0, label %bb53.us
8 i8 1, label %bb94.us
9 ]
10 bb94.us: ; preds = %bb71.us, %bb53.us
11 %result.0.us = phi i32 [ %tmp93.us, %bb71.us ], [ 0, %bb53.us ] ; [#uses=2]
12 %tmp101.us = lshr i32 %result.0.us, 3 ; [#uses=1]
13 %result.0163.us = trunc i32 %result.0.us to i16 ; [#uses=2]
14 shl i16 %result.0163.us, 7 ; :0 [#uses=1]
15 %tmp106.us = and i16 %0, -1024 ; [#uses=1]
16 shl i16 %result.0163.us, 2 ; :1 [#uses=1]
17 %tmp109.us = and i16 %1, -32 ; [#uses=1]
18 %tmp111112.us = trunc i32 %tmp101.us to i16 ; [#uses=1]
19 %tmp110.us = or i16 %tmp109.us, %tmp111112.us ; [#uses=1]
20 %tmp113.us = or i16 %tmp110.us, %tmp106.us ; [#uses=1]
21 store i16 %tmp113.us, i16* null, align 2
22 br label %bb53.us
23 bb71.us: ; preds = %bb53.us
24 %tmp80.us = load i8* null, align 1 ; [#uses=1]
25 %tmp8081.us = zext i8 %tmp80.us to i32 ; [#uses=1]
26 %tmp87.us = mul i32 %tmp8081.us, 0 ; [#uses=1]
27 %tmp92.us = add i32 0, %tmp87.us ; [#uses=1]
28 %tmp93.us = udiv i32 %tmp92.us, 255 ; [#uses=1]
29 br label %bb94.us
30 bb53: ; preds = %entry
31 ret void
32 }