llvm.org GIT mirror llvm / 61f1e3d
Move pass configuration out of pass constructors: BranchFolderPass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150095 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
7 changed file(s) with 39 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
4141 bool Initialized; // Flagged after all passes are configured.
4242
4343 // Target Pass Options
44 // Targets provide a default setting, user flags override.
4445 //
4546 bool DisableVerify;
47
48 /// Default setting for -enable-tail-merge on this target.
49 bool EnableTailMerge;
4650
4751 public:
4852 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
6670
6771 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
6872
69 void setDisableVerify(bool disable) { DisableVerify = disable; }
73 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
74
75 bool getEnableTailMerge() const { return EnableTailMerge; }
76 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
7077
7178 /// Add common target configurable passes that perform LLVM IR to IR
7279 /// transforms following machine independent optimization.
116123 virtual bool addPostRegAlloc() {
117124 return false;
118125 }
119
120 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
121 /// on this target. User flag overrides.
122 virtual bool getEnableTailMergeDefault() const { return true; }
123126
124127 /// addPreSched2 - This method may be implemented by targets that want to
125128 /// run passes after prolog-epilog insertion and before the second instruction
273276 /// optimizations to delete branches to branches, eliminate branches to
274277 /// successor blocks (creating fall throughs), and eliminating branches over
275278 /// branches.
276 FunctionPass *createBranchFoldingPass(bool DefaultEnableTailMerge);
279 extern char &BranchFolderPassID;
277280
278281 /// TailDuplicate Pass - Duplicate blocks with unconditional branches
279282 /// into tails of their predecessors.
7070 void initializeBlockExtractorPassPass(PassRegistry&);
7171 void initializeBlockFrequencyInfoPass(PassRegistry&);
7272 void initializeBlockPlacementPass(PassRegistry&);
73 void initializeBranchFolderPassPass(PassRegistry&);
7374 void initializeBranchProbabilityInfoPass(PassRegistry&);
7475 void initializeBreakCriticalEdgesPass(PassRegistry&);
7576 void initializeCFGOnlyPrinterPass(PassRegistry&);
6060
6161 namespace {
6262 /// BranchFolderPass - Wrap branch folder in a machine function pass.
63 class BranchFolderPass : public MachineFunctionPass,
64 public BranchFolder {
63 class BranchFolderPass : public MachineFunctionPass {
6564 public:
6665 static char ID;
67 explicit BranchFolderPass(bool defaultEnableTailMerge)
68 : MachineFunctionPass(ID), BranchFolder(defaultEnableTailMerge, true) {}
66 explicit BranchFolderPass(): MachineFunctionPass(ID) {}
6967
7068 virtual bool runOnMachineFunction(MachineFunction &MF);
71 virtual const char *getPassName() const { return "Control Flow Optimizer"; }
69
70 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired();
72 MachineFunctionPass::getAnalysisUsage(AU);
73 }
7274 };
7375 }
7476
7577 char BranchFolderPass::ID = 0;
76
77 FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge) {
78 return new BranchFolderPass(DefaultEnableTailMerge);
79 }
78 char &llvm::BranchFolderPassID = BranchFolderPass::ID;
79
80 INITIALIZE_PASS(BranchFolderPass, "branch-folder",
81 "Control Flow Optimizer", false, false)
8082
8183 bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
82 return OptimizeFunction(MF,
83 MF.getTarget().getInstrInfo(),
84 MF.getTarget().getRegisterInfo(),
85 getAnalysisIfAvailable());
84 TargetPassConfig *PassConfig = &getAnalysis();
85 BranchFolder Folder(PassConfig->getEnableTailMerge(), /*CommonHoist=*/true);
86 return Folder.OptimizeFunction(MF,
87 MF.getTarget().getInstrInfo(),
88 MF.getTarget().getRegisterInfo(),
89 getAnalysisIfAvailable());
8690 }
8791
8892
1818
1919 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
2020 void llvm::initializeCodeGen(PassRegistry &Registry) {
21 initializeBranchFolderPassPass(Registry);
2122 initializeCalculateSpillWeightsPass(Registry);
2223 initializeDeadMachineInstructionElimPass(Registry);
2324 initializeGCModuleInfoPass(Registry);
8282 // Out of line virtual method.
8383 TargetPassConfig::~TargetPassConfig() {}
8484
85 // Out of line constructor provides default values for pass options and
86 // registers all common codegen passes.
8587 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
8688 : ImmutablePass(ID), TM(tm), PM(pm), Initialized(false),
8789 DisableVerify(false),
256258
257259 // Branch folding must be run after regalloc and prolog/epilog insertion.
258260 if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
259 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
261 addPass(BranchFolderPassID);
260262 printNoVerify("After BranchFolding");
261263 }
262264
358358
359359 // Branch folding must be run after regalloc and prolog/epilog insertion.
360360 if (getOptLevel() != CodeGenOpt::None) {
361 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
361 addPass(BranchFolderPassID);
362362 printNoVerify("After BranchFolding");
363363 }
364364
7777 }
7878
7979 virtual bool addInstSelector();
80 virtual bool getEnableTailMergeDefault() const;
8180 virtual bool addPreEmitPass();
8281 };
8382 } // namespace
8483
8584 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
86 return new PPCPassConfig(this, PM);
85 TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
86
87 // Override this for PowerPC. Tail merging happily breaks up instruction issue
88 // groups, which typically degrades performance.
89 PassConfig->setEnableTailMerge(false);
90
91 return PassConfig;
8792 }
8893
8994 bool PPCPassConfig::addInstSelector() {
9196 PM.add(createPPCISelDag(getPPCTargetMachine()));
9297 return false;
9398 }
94
95 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
96 /// groups, which typically degrades performance.
97 bool PPCPassConfig::getEnableTailMergeDefault() const { return false; }
9899
99100 bool PPCPassConfig::addPreEmitPass() {
100101 // Must run branch selection immediately preceding the asm printer.