llvm.org GIT mirror llvm / 61de82d
Use BitVector instead of vector<bool> which can be extremely slow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34302 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
6 changed file(s) with 12 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
2121
2222 #include "llvm/CodeGen/MachineFunctionPass.h"
2323 #include "llvm/CodeGen/LiveInterval.h"
24 #include "llvm/ADT/BitVector.h"
2425 #include "llvm/ADT/IndexedMap.h"
2526
2627 namespace llvm {
5354 typedef IndexedMap Reg2RegMap;
5455 Reg2RegMap r2rMap_;
5556
56 std::vector allocatableRegs_;
57 BitVector allocatableRegs_;
5758
5859 public:
5960 struct CopyRec {
2929 #define LLVM_CODEGEN_LIVEVARIABLES_H
3030
3131 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/ADT/BitVector.h"
3233 #include
3334
3435 namespace llvm {
7475 /// through. This is a bit set which uses the basic block number as an
7576 /// index.
7677 ///
77 std::vector AliveBlocks;
78 BitVector AliveBlocks;
7879
7980 /// Kills - List of MachineInstruction's which are the last use of this
8081 /// virtual register (kill it) in their basic block.
110111 /// are actually register allocatable by the target machine. We can not track
111112 /// liveness for values that are not in this set.
112113 ///
113 std::vector AllocatablePhysicalRegisters;
114 BitVector AllocatablePhysicalRegisters;
114115
115116 private: // Intermediate data structures
116117 const MRegisterInfo *RegInfo;
2929 class MachineMove;
3030 class TargetRegisterClass;
3131 class CalleeSavedInfo;
32 class BitVector;
3233
3334 /// TargetRegisterDesc - This record contains all of the information known about
3435 /// a particular register. The AliasSet field (if not null) contains a pointer
239240
240241 /// getAllocatableSet - Returns a bitset indexed by register number
241242 /// indicating if a register is allocatable or not.
242 std::vector getAllocatableSet(MachineFunction &MF) const;
243 BitVector getAllocatableSet(MachineFunction &MF) const;
243244
244245 const TargetRegisterDesc &operator[](unsigned RegNo) const {
245246 assert(RegNo < NumRegs &&
460460 // If the kill happens after the definition, we have an intra-block
461461 // live range.
462462 if (killIdx > defIndex) {
463 assert(vi.AliveBlocks.empty() &&
463 assert(vi.AliveBlocks.none() &&
464464 "Shouldn't be alive across any blocks!");
465465 LiveRange LR(defIndex, killIdx, ValNum);
466466 interval.addRange(LR);
788788 // is allocatable. To handle this, we mark all unallocatable registers as
789789 // being pinned down, permanently.
790790 {
791 std::vector Allocable = RegInfo->getAllocatableSet(Fn);
791 BitVector Allocable = RegInfo->getAllocatableSet(Fn);
792792 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
793793 if (!Allocable[i])
794794 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1313 #include "llvm/Target/TargetMachine.h"
1414 #include "llvm/Target/MRegisterInfo.h"
1515 #include "llvm/Target/TargetFrameInfo.h"
16
1716 #include "llvm/CodeGen/MachineFunction.h"
1817 #include "llvm/CodeGen/MachineFrameInfo.h"
1918 #include "llvm/CodeGen/MachineLocation.h"
19 #include "llvm/ADT/BitVector.h"
2020
2121 using namespace llvm;
2222
3333
3434 MRegisterInfo::~MRegisterInfo() {}
3535
36 std::vector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
37 std::vector Allocatable(NumRegs);
36 BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
37 BitVector Allocatable(NumRegs);
3838 for (MRegisterInfo::regclass_iterator I = regclass_begin(),
3939 E = regclass_end(); I != E; ++I) {
4040 const TargetRegisterClass *RC = *I;