llvm.org GIT mirror llvm / 61d9c86
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: leal (,%rcx,8), %rcx It should be leal (,%rcx,8), %ecx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41735 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
2 changed file(s) with 64 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
209209 }
210210 case X86::SHL16ri: {
211211 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
212 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
213 // the flags produced by a shift yet, so this is safe.
214 unsigned Dest = MI->getOperand(0).getReg();
215 unsigned Src = MI->getOperand(1).getReg();
216 unsigned ShAmt = MI->getOperand(2).getImm();
217 if (ShAmt == 0 || ShAmt >= 4) return 0;
212 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
213 // the flags produced by a shift yet, so this is safe.
214 unsigned Dest = MI->getOperand(0).getReg();
215 unsigned Src = MI->getOperand(1).getReg();
216 unsigned ShAmt = MI->getOperand(2).getImm();
217 if (ShAmt == 0 || ShAmt >= 4) return 0;
218218
219219 if (DisableLEA16) {
220220 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
221221 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
222 unsigned Opc, leaInReg, leaOutReg;
223 MVT::ValueType leaVT;
224 if (TM.getSubtarget().is64Bit()) {
225 Opc = X86::LEA64_32r;
226 leaVT = MVT::i64;
227 leaInReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
228 leaOutReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
229 } else {
230 Opc = X86::LEA32r;
231 leaVT = MVT::i32;
232 leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
233 leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
234 }
222 unsigned Opc = TM.getSubtarget().is64Bit()
223 ? X86::LEA64_32r : X86::LEA32r;
224 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
225 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
235226
236 MachineInstr *Ins = NULL, *Ext = NULL;
237
238 Ins = BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
227 MachineInstr *Ins =
228 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
239229 Ins->copyKillDeadInfo(MI);
240230
241231 NewMI = BuildMI(get(Opc), leaOutReg)
242232 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
243233
244 Ext = BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
234 MachineInstr *Ext =
235 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
245236 Ext->copyKillDeadInfo(MI);
246237
247238 MFI->insert(MBBI, Ins); // Insert the insert_subreg
249240 LV.addVirtualRegisterKilled(leaInReg, NewMI);
250241 MFI->insert(MBBI, NewMI); // Insert the new inst
251242 LV.addVirtualRegisterKilled(leaOutReg, Ext);
252 MFI->insert(MBBI, Ext); // Insert the extract_subreg
253
243 MFI->insert(MBBI, Ext); // Insert the extract_subreg
254244 return Ext;
255245 } else {
256246 NewMI = BuildMI(get(X86::LEA16r), Dest)
0 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -x86-asm-syntax=intel | not grep {lea\[\[:space:\]\]R}
1
2 %struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
3 %struct.AGenericManager = type <{ i8 }>
4 %struct.ComponentInstanceRecord = type opaque
5 %struct.ComponentParameters = type { [1 x i64] }
6
7 define i32 @_ZN12AGenericCall10MapIDPtrAtEsRP23ComponentInstanceRecord(%struct.AGenericCall* %this, i16 signext %param, %struct.ComponentInstanceRecord** %instance) {
8 entry:
9 %tmp4 = icmp slt i16 %param, 0 ; [#uses=1]
10 br i1 %tmp4, label %cond_true, label %cond_next
11
12 cond_true: ; preds = %entry
13 %tmp1415 = shl i16 %param, 3 ; [#uses=1]
14 %tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
15 %tmp18 = load %struct.ComponentParameters** %tmp17, align 8 ; <%struct.ComponentParameters*> [#uses=1]
16 %tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8* ; [#uses=1]
17 %tmp212223 = sext i16 %tmp1415 to i64 ; [#uses=1]
18 %tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223 ; [#uses=1]
19 %tmp2425 = bitcast i8* %tmp24 to i64* ; [#uses=1]
20 %tmp28 = load i64* %tmp2425, align 8 ; [#uses=1]
21 %tmp2829 = inttoptr i64 %tmp28 to i32* ; [#uses=1]
22 %tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2 ; [#uses=1]
23 store i32* %tmp2829, i32** %tmp31, align 8
24 br label %cond_next
25
26 cond_next: ; preds = %cond_true, %entry
27 %tmp4243 = shl i16 %param, 3 ; [#uses=1]
28 %tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
29 %tmp47 = load %struct.ComponentParameters** %tmp46, align 8 ; <%struct.ComponentParameters*> [#uses=1]
30 %tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8* ; [#uses=1]
31 %tmp505152 = sext i16 %tmp4243 to i64 ; [#uses=1]
32 %tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152 ; [#uses=1]
33 %tmp5354 = bitcast i8* %tmp53 to i64* ; [#uses=1]
34 %tmp58 = load i64* %tmp5354, align 8 ; [#uses=1]
35 %tmp59 = icmp eq i64 %tmp58, 0 ; [#uses=1]
36 br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
37
38 cond_true63: ; preds = %cond_next
39 %tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0 ; <%struct.AGenericManager**> [#uses=1]
40 %tmp66 = load %struct.AGenericManager** %tmp65, align 8 ; <%struct.AGenericManager*> [#uses=1]
41 %tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance ) ; [#uses=1]
42 ret i32 %tmp69
43
44 UnifiedReturnBlock: ; preds = %cond_next
45 ret i32 undef
46 }
47
48 declare i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord(%struct.AGenericManager*, %struct.ComponentInstanceRecord**)