llvm.org GIT mirror llvm / 6186de5
[ARM] Add Virtualization subtarget feature and more build attributes in this area Add a Virtualization ARM subtarget feature along with adding proper build attribute emission for Tag_Virtualization_use (encodes Virtualization and TrustZone) and Tag_MPextension_use. Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to something that is more maintainable. This changes the focus of this testcase away from testing CPU defaults (which is tested elsewhere), onto specifically testing that attributes are encoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8 Bradley Smith 6 years ago
8 changed file(s) with 167 addition(s) and 269 deletion(s). Raw diff Collapse all Expand all
118118 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
119119 "Supports Multiprocessing extension">;
120120
121 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
122 def FeatureVirtualization : SubtargetFeature<"virtualization",
123 "HasVirtualization", "true",
124 "Supports Virtualization extension",
125 [FeatureHWDiv, FeatureHWDivARM]>;
126
121127 // M-series ISA
122128 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
123129 "Is microcontroller profile ('M' series)">;
158164 [HasV6T2Ops, FeaturePerfMon]>;
159165 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
160166 "Support ARM v8 instructions",
161 [HasV7Ops]>;
167 [HasV7Ops, FeatureVirtualization,
168 FeatureMP]>;
162169
163170 //===----------------------------------------------------------------------===//
164171 // ARM Processors supported.
197204 [FeatureT2XtPk, FeatureVFP4,
198205 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
199206 FeatureAvoidPartialCPSR,
200 FeatureTrustZone]>;
207 FeatureTrustZone, FeatureVirtualization]>;
201208
202209 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
203210 "Cortex-A53 ARM processors",
204 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
211 [FeatureHWDiv, FeatureHWDivARM,
205212 FeatureTrustZone, FeatureT2XtPk,
206213 FeatureCrypto, FeatureCRC]>;
207214
208215 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
209216 "Cortex-A57 ARM processors",
210 [FeatureMP, FeatureHWDiv, FeatureHWDivARM,
217 [FeatureHWDiv, FeatureHWDivARM,
211218 FeatureTrustZone, FeatureT2XtPk,
212219 FeatureCrypto, FeatureCRC]>;
213220
702702
703703 // FIXME: Should we signal R9 usage?
704704
705 if (Subtarget->hasMPExtension())
706 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
707
705708 if (Subtarget->hasDivide()) {
706709 // Check if hardware divide is only available in thumb2 or ARM as well.
707710 ATS.emitAttribute(ARMBuildAttrs::DIV_use,
708711 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
709712 ARMBuildAttrs::AllowDIVIfExists);
710713 }
714
715 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
716 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
717 ARMBuildAttrs::AllowTZVirtualization);
718 else if (Subtarget->hasTrustZone())
719 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
720 ARMBuildAttrs::AllowTZ);
721 else if (Subtarget->hasVirtualization())
722 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
723 ARMBuildAttrs::AllowVirtualization);
711724
712725 ATS.finishAttributeSection();
713726 }
143143 BaseAAPCS = 0,
144144 HardFPAAPCS = 1,
145145
146 // Tag_MPextension_use, (=42), uleb128
147 AllowMP = 1, // Allow use of MP extensions
148
146149 // Tag_DIV_use, (=44), uleb128
147150 AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no info exists.
148151 DisallowDIV = 1, // Hardware divide explicitly disallowed
149 AllowDIVExt = 2 // Allow hardware divide as optional architecture extension above
152 AllowDIVExt = 2, // Allow hardware divide as optional architecture extension above
150153 // the base arch specified by Tag_CPU_arch and Tag_CPU_arch_profile.
154
155 // Tag_Virtualization_use, (=68), uleb128
156 AllowTZ = 1,
157 AllowVirtualization = 2,
158 AllowTZVirtualization = 3
151159 };
152160
153161 } // namespace ARMBuildAttrs
107107 AvoidMOVsShifterOperand = false;
108108 HasRAS = false;
109109 HasMPExtension = false;
110 HasVirtualization = false;
110111 FPOnlySP = false;
111112 HasPerfMon = false;
112113 HasTrustZone = false;
149149 /// extension (ARMv7 only).
150150 bool HasMPExtension;
151151
152 /// HasVirtualization - True if the subtarget supports the Virtualization
153 /// extension.
154 bool HasVirtualization;
155
152156 /// FPOnlySP - If true, the floating point unit only supports single
153157 /// precision.
154158 bool FPOnlySP;
259263 bool hasNEON() const { return HasNEON; }
260264 bool hasCrypto() const { return HasCrypto; }
261265 bool hasCRC() const { return HasCRC; }
266 bool hasVirtualization() const { return HasVirtualization; }
262267 bool useNEONForSinglePrecisionFP() const {
263268 return hasNEON() && UseNEONForSinglePrecisionFP; }
264269
1313 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
1414 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
1515 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
16 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP
1617 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
1718 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
1819 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
2728 ; V6: .eabi_attribute 25, 1
2829 ; V6-NOT: .eabi_attribute 27
2930 ; V6-NOT: .eabi_attribute 28
31 ; V6-NOT: .eabi_attribute 42
32 ; V6-NOT: .eabi_attribute 68
3033
3134 ; V6M: .eabi_attribute 6, 12
3235 ; V6M: .eabi_attribute 7, 77
3639 ; V6M: .eabi_attribute 25, 1
3740 ; V6M-NOT: .eabi_attribute 27
3841 ; V6M-NOT: .eabi_attribute 28
42 ; V6M-NOT: .eabi_attribute 42
43 ; V6M-NOT: .eabi_attribute 68
3944
4045 ; ARM1156T2F-S: .cpu arm1156t2f-s
4146 ; ARM1156T2F-S: .eabi_attribute 6, 8
4954 ; ARM1156T2F-S: .eabi_attribute 25, 1
5055 ; ARM1156T2F-S-NOT: .eabi_attribute 27
5156 ; ARM1156T2F-S-NOT: .eabi_attribute 28
57 ; ARM1156T2F-S-NOT: .eabi_attribute 42
58 ; ARM1156T2F-S-NOT: .eabi_attribute 68
5259
5360 ; V7M: .eabi_attribute 6, 10
5461 ; V7M: .eabi_attribute 7, 77
5865 ; V7M: .eabi_attribute 25, 1
5966 ; V7M-NOT: .eabi_attribute 27
6067 ; V7M-NOT: .eabi_attribute 28
68 ; V7M-NOT: .eabi_attribute 42
6169 ; V7M: .eabi_attribute 44, 0
70 ; V7M-NOT: .eabi_attribute 68
6271
6372 ; V7: .syntax unified
6473 ; V7: .eabi_attribute 6, 10
6978 ; V7: .eabi_attribute 25, 1
7079 ; V7-NOT: .eabi_attribute 27
7180 ; V7-NOT: .eabi_attribute 28
81 ; V7-NOT: .eabi_attribute 42
82 ; V7-NOT: .eabi_attribute 68
7283
7384 ; V8: .syntax unified
7485 ; V8: .eabi_attribute 6, 14
108119 ; CORTEX-A9-SOFT: .eabi_attribute 25, 1
109120 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
110121 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
122 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 42
123 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1
111124
112125 ; CORTEX-A9-HARD: .cpu cortex-a9
113126 ; CORTEX-A9-HARD: .eabi_attribute 6, 10
122135 ; CORTEX-A9-HARD: .eabi_attribute 25, 1
123136 ; CORTEX-A9-HARD-NOT: .eabi_attribute 27
124137 ; CORTEX-A9-HARD: .eabi_attribute 28, 1
138 ; CORTEX-A9-HARD-NOT: .eabi_attribute 42
139 ; CORTEX-A9-HARD: .eabi_attribute 68, 1
140
141 ; CORTEX-A9-MP: .cpu cortex-a9-mp
142 ; CORTEX-A9-MP: .eabi_attribute 6, 10
143 ; CORTEX-A9-MP: .eabi_attribute 7, 65
144 ; CORTEX-A9-MP: .eabi_attribute 8, 1
145 ; CORTEX-A9-MP: .eabi_attribute 9, 2
146 ; CORTEX-A9-MP: .fpu neon
147 ; CORTEX-A9-MP: .eabi_attribute 20, 1
148 ; CORTEX-A9-MP: .eabi_attribute 21, 1
149 ; CORTEX-A9-MP: .eabi_attribute 23, 3
150 ; CORTEX-A9-MP: .eabi_attribute 24, 1
151 ; CORTEX-A9-MP: .eabi_attribute 25, 1
152 ; CORTEX-A9-NOT: .eabi_attribute 27
153 ; CORTEX-A9-NOT: .eabi_attribute 28
154 ; CORTEX-A9-MP: .eabi_attribute 42, 1
155 ; CORTEX-A9-MP: .eabi_attribute 68, 1
125156
126157 ; CORTEX-A15: .cpu cortex-a15
127158 ; CORTEX-A15: .eabi_attribute 6, 10
134165 ; CORTEX-A15: .eabi_attribute 23, 3
135166 ; CORTEX-A15: .eabi_attribute 24, 1
136167 ; CORTEX-A15: .eabi_attribute 25, 1
168 ; CORTEX-A15: .eabi_attribute 42, 1
137169 ; CORTEX-A15: .eabi_attribute 44, 2
138170 ; CORTEX-A15-NOT: .eabi_attribute 27
139171 ; CORTEX-A15-NOT: .eabi_attribute 28
172 ; CORTEX-A15: .eabi_attribute 68, 3
140173
141174 ; CORTEX-M0: .cpu cortex-m0
142175 ; CORTEX-M0: .eabi_attribute 6, 12
147180 ; CORTEX-M0: .eabi_attribute 25, 1
148181 ; CORTEX-M0-NOT: .eabi_attribute 27
149182 ; CORTEX-M0-NOT: .eabi_attribute 28
183 ; CORTEX-M0-NOT: .eabi_attribute 42
184 ; CORTEX-M0-NOT: .eabi_attribute 68
150185
151186 ; CORTEX-M4-SOFT: .cpu cortex-m4
152187 ; CORTEX-M4-SOFT: .eabi_attribute 6, 13
161196 ; CORTEX-M4-SOFT: .eabi_attribute 25, 1
162197 ; CORTEX-M4-SOFT: .eabi_attribute 27, 1
163198 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
199 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
164200 ; CORTEX-M4-SOFT: .eabi_attribute 44, 0
201 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
165202
166203 ; CORTEX-M4-HARD: .cpu cortex-m4
167204 ; CORTEX-M4-HARD: .eabi_attribute 6, 13
176213 ; CORTEX-M4-HARD: .eabi_attribute 25, 1
177214 ; CORTEX-M4-HARD: .eabi_attribute 27, 1
178215 ; CORTEX-M4-HARD: .eabi_attribute 28, 1
216 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42
179217 ; CORTEX-M4-HARD: .eabi_attribute 44, 0
218 ; CORTEX-M4-HRAD-NOT: .eabi_attribute 68
180219
181220 ; CORTEX-R5: .cpu cortex-r5
182221 ; CORTEX-R5: .eabi_attribute 6, 10
183222 ; CORTEX-R5: .eabi_attribute 7, 82
184 ; CORTEX-R5: .eabi_attribute 8, 1
223 ; CORTEX-R5: .eabi_attribute 8, 1
185224 ; CORTEX-R5: .eabi_attribute 9, 2
186225 ; CORTEX-R5: .fpu vfpv3-d16
187226 ; CORTEX-R5: .eabi_attribute 20, 1
191230 ; CORTEX-R5: .eabi_attribute 25, 1
192231 ; CORTEX-R5: .eabi_attribute 27, 1
193232 ; CORTEX-R5-NOT: .eabi_attribute 28
233 ; CORTEX-R5-NOT: .eabi_attribute 42
194234 ; CORTEX-R5: .eabi_attribute 44, 2
235 ; CORTEX-R5-NOT: .eabi_attribute 68
195236
196237 ; CORTEX-A53: .cpu cortex-a53
197238 ; CORTEX-A53: .eabi_attribute 6, 14
204245 ; CORTEX-A53: .eabi_attribute 25, 1
205246 ; CORTEX-A53-NOT: .eabi_attribute 27
206247 ; CORTEX-A53-NOT: .eabi_attribute 28
248 ; CORTEX-A53: .eabi_attribute 42, 1
207249 ; CORTEX-A53: .eabi_attribute 44, 2
250 ; CORTEX-A53: .eabi_attribute 68, 3
208251
209252 ; CORTEX-A57: .cpu cortex-a57
210253 ; CORTEX-A57: .eabi_attribute 6, 14
217260 ; CORTEX-A57: .eabi_attribute 25, 1
218261 ; CORTEX-A57-NOT: .eabi_attribute 27
219262 ; CORTEX-A57-NOT: .eabi_attribute 28
263 ; CORTEX-A57: .eabi_attribute 42, 1
220264 ; CORTEX-A57: .eabi_attribute 44, 2
265 ; CORTEX-A57: .eabi_attribute 68, 3
221266
222267 define i32 @f(i64 %z) {
223268 ret i32 0
+0
-263
test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll less more
None ; This tests that the expected ARM attributes are emitted.
1
2 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -filetype=obj -o - \
3 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=BASIC
4 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \
5 ; RUN: -mattr=-neon,-vfp3,+vfp2 -arm-reserve-r9 -filetype=obj -o - \
6 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A8
7 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -filetype=obj \
8 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V7
9 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -filetype=obj \
10 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8
11 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -filetype=obj \
12 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=Vt8
13 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
14 ; RUN: -mattr=-neon,-crypto -filetype=obj \
15 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-FPARMv8
16 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
17 ; RUN: -mattr=-fp-armv8,-crypto -filetype=obj \
18 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-NEON
19 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi \
20 ; RUN: -mattr=-crypto -filetype=obj \
21 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=V8-FPARMv8-NEON
22 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -filetype=obj \
23 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A9
24 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -filetype=obj \
25 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-A15
26 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -filetype=obj \
27 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-M0
28 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -filetype=obj \
29 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-M4
30 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -filetype=obj \
31 ; RUN: | llvm-readobj -s -sd | FileCheck %s --check-prefix=CORTEX-R5
32
33 ; BASIC: Section {
34 ; BASIC: Name: .ARM.attributes
35 ; BASIC-NEXT: Type: SHT_ARM_ATTRIBUTES
36 ; BASIC-NEXT: Flags [ (0x0)
37 ; BASIC-NEXT: ]
38 ; BASIC-NEXT: Address: 0x0
39 ; BASIC-NEXT: Offset: 0x3C
40 ; BASIC-NEXT: Size: 30
41 ; BASIC-NEXT: Link: 0
42 ; BASIC-NEXT: Info: 0
43 ; BASIC-NEXT: AddressAlignment: 1
44 ; BASIC-NEXT: EntrySize: 0
45 ; BASIC-NEXT: SectionData (
46 ; BASIC-NEXT: 0000: 411D0000 00616561 62690001 13000000
47 ; BASIC-NEXT: 0010: 06010801 14011501 17031801 1901
48 ; BASIC-NEXT: )
49
50 ; CORTEX-A8: Name: .ARM.attributes
51 ; CORTEX-A8-NEXT: Type: SHT_ARM_ATTRIBUTES
52 ; CORTEX-A8-NEXT: Flags [ (0x0)
53 ; CORTEX-A8-NEXT: ]
54 ; CORTEX-A8-NEXT: Address: 0x0
55 ; CORTEX-A8-NEXT: Offset: 0x3C
56 ; CORTEX-A8-NEXT: Size: 47
57 ; CORTEX-A8-NEXT: Link: 0
58 ; CORTEX-A8-NEXT: Info: 0
59 ; CORTEX-A8-NEXT: AddressAlignment: 1
60 ; CORTEX-A8-NEXT: EntrySize: 0
61 ; CORTEX-A8-NEXT: SectionData (
62 ; CORTEX-A8-NEXT: 0000: 412E0000 00616561 62690001 24000000
63 ; CORTEX-A8-NEXT: 0010: 05434F52 5445582D 41380006 0A074108
64 ; CORTEX-A8-NEXT: 0020: 0109020A 02140115 01170318 011901
65 ; CORTEX-A8-NEXT: )
66
67 ; V7: Name: .ARM.attributes
68 ; V7-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
69 ; V7-NEXT: Flags [ (0x0)
70 ; V7-NEXT: ]
71 ; V7-NEXT: Address: 0x0
72 ; V7-NEXT: Offset: 0x3C
73 ; V7-NEXT: Size: 36
74 ; V7-NEXT: Link: 0
75 ; V7-NEXT: Info: 0
76 ; V7-NEXT: AddressAlignment: 1
77 ; V7-NEXT: EntrySize: 0
78 ; V7-NEXT: SectionData (
79 ; V7-NEXT: 0000: 41230000 00616561 62690001 19000000
80 ; V7-NEXT: 0010: 060A0801 09020A03 0C011401 15011703
81 ; V7-NEXT: 0020: 18011901
82 ; V7-NEXT: )
83
84 ; V8: Name: .ARM.attributes
85 ; V8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
86 ; V8-NEXT: Flags [ (0x0)
87 ; V8-NEXT: ]
88 ; V8-NEXT: Address: 0x0
89 ; V8-NEXT: Offset: 0x3C
90 ; V8-NEXT: Size: 38
91 ; V8-NEXT: Link: 0
92 ; V8-NEXT: Info: 0
93 ; V8-NEXT: AddressAlignment: 1
94 ; V8-NEXT: EntrySize: 0
95 ; V8-NEXT: SectionData (
96 ; V8-NEXT: 0000: 41250000 00616561 62690001 1B000000
97 ; V8-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
98 ; V8-NEXT: 0020: 18011901 2C02
99 ; V8-NEXT: )
100
101 ; Vt8: Name: .ARM.attributes
102 ; Vt8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
103 ; Vt8-NEXT: Flags [ (0x0)
104 ; Vt8-NEXT: ]
105 ; Vt8-NEXT: Address: 0x0
106 ; Vt8-NEXT: Offset: 0x38
107 ; Vt8-NEXT: Size: 38
108 ; Vt8-NEXT: Link: 0
109 ; Vt8-NEXT: Info: 0
110 ; Vt8-NEXT: AddressAlignment: 1
111 ; Vt8-NEXT: EntrySize: 0
112 ; Vt8-NEXT: SectionData (
113 ; Vt8-NEXT: 0000: 41250000 00616561 62690001 1B000000
114 ; Vt8-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
115 ; Vt8-NEXT: 0020: 18011901 2C02
116 ; Vt8-NEXT: )
117
118
119 ; V8-FPARMv8: Name: .ARM.attributes
120 ; V8-FPARMv8-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
121 ; V8-FPARMv8-NEXT: Flags [ (0x0)
122 ; V8-FPARMv8-NEXT: ]
123 ; V8-FPARMv8-NEXT: Address: 0x0
124 ; V8-FPARMv8-NEXT: Offset: 0x3C
125 ; V8-FPARMv8-NEXT: Size: 36
126 ; V8-FPARMv8-NEXT: Link: 0
127 ; V8-FPARMv8-NEXT: Info: 0
128 ; V8-FPARMv8-NEXT: AddressAlignment: 1
129 ; V8-FPARMv8-NEXT: EntrySize: 0
130 ; V8-FPARMv8-NEXT: SectionData (
131 ; V8-FPARMv8-NEXT: 0000: 41230000 00616561 62690001 19000000
132 ; V8-FPARMv8-NEXT: 0010: 060E0801 09020A07 14011501 17031801
133 ; V8-FPARMv8-NEXT: 0020: 19012C02
134 ; V8-FPARMv8-NEXT: )
135
136
137 ; V8-NEON: Name: .ARM.attributes
138 ; V8-NEON-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
139 ; V8-NEON-NEXT: Flags [ (0x0)
140 ; V8-NEON-NEXT: ]
141 ; V8-NEON-NEXT: Address: 0x0
142 ; V8-NEON-NEXT: Offset: 0x3C
143 ; V8-NEON-NEXT: Size: 38
144 ; V8-NEON-NEXT: Link: 0
145 ; V8-NEON-NEXT: Info: 0
146 ; V8-NEON-NEXT: AddressAlignment: 1
147 ; V8-NEON-NEXT: EntrySize: 0
148 ; V8-NEON-NEXT: SectionData (
149 ; V8-NEON-NEXT: 0000: 41250000 00616561 62690001 1B000000
150 ; V8-NEON-NEXT: 0010: 060E0801 09020A05 0C031401 15011703
151 ; V8-NEON-NEXT: 0020: 18011901 2C02
152 ; V8-NEON-NEXT: )
153
154 ; V8-FPARMv8-NEON: Name: .ARM.attributes
155 ; V8-FPARMv8-NEON-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
156 ; V8-FPARMv8-NEON-NEXT: Flags [ (0x0)
157 ; V8-FPARMv8-NEON-NEXT: ]
158 ; V8-FPARMv8-NEON-NEXT: Address: 0x0
159 ; V8-FPARMv8-NEON-NEXT: Offset: 0x3C
160 ; V8-FPARMv8-NEON-NEXT: Size: 38
161 ; V8-FPARMv8-NEON-NEXT: Link: 0
162 ; V8-FPARMv8-NEON-NEXT: Info: 0
163 ; V8-FPARMv8-NEON-NEXT: AddressAlignment: 1
164 ; V8-FPARMv8-NEON-NEXT: EntrySize: 0
165 ; V8-FPARMv8-NEON-NEXT: SectionData (
166 ; V8-FPARMv8-NEON-NEXT: 0000: 41250000 00616561 62690001 1B000000
167 ; V8-FPARMv8-NEON-NEXT: 0010: 060E0801 09020A07 0C031401 15011703
168 ; V8-FPARMv8-NEON-NEXT: 0020: 18011901 2C02
169 ; V8-FPARMv8-NEON-NEXT: )
170
171 ; CORTEX-A9: Name: .ARM.attributes
172 ; CORTEX-A9-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
173 ; CORTEX-A9-NEXT: Flags [ (0x0)
174 ; CORTEX-A9-NEXT: ]
175 ; CORTEX-A9-NEXT: Address: 0x0
176 ; CORTEX-A9-NEXT: Offset: 0x3C
177 ; CORTEX-A9-NEXT: Size: 49
178 ; CORTEX-A9-NEXT: Link: 0
179 ; CORTEX-A9-NEXT: Info: 0
180 ; CORTEX-A9-NEXT: AddressAlignment: 1
181 ; CORTEX-A9-NEXT: EntrySize: 0
182 ; CORTEX-A9-NEXT: SectionData (
183 ; CORTEX-A9-NEXT: 0000: 41300000 00616561 62690001 26000000
184 ; CORTEX-A9-NEXT: 0010: 05434F52 5445582D 41390006 0A074108
185 ; CORTEX-A9-NEXT: 0020: 0109020A 030C0114 01150117 03180119
186 ; CORTEX-A9-NEXT: 0030: 01
187 ; CORTEX-A9-NEXT: )
188
189 ; CORTEX-A15: Name: .ARM.attributes
190 ; CORTEX-A15-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
191 ; CORTEX-A15-NEXT: Flags [ (0x0)
192 ; CORTEX-A15-NEXT: ]
193 ; CORTEX-A15-NEXT: Address: 0x0
194 ; CORTEX-A15-NEXT: Offset: 0x3C
195 ; CORTEX-A15-NEXT: Size: 52
196 ; CORTEX-A15-NEXT: Link: 0
197 ; CORTEX-A15-NEXT: Info: 0
198 ; CORTEX-A15-NEXT: AddressAlignment: 1
199 ; CORTEX-A15-NEXT: EntrySize: 0
200 ; CORTEX-A15-NEXT: SectionData (
201 ; CORTEX-A15-NEXT: 0000: 41330000 00616561 62690001 29000000
202 ; CORTEX-A15-NEXT: 0010: 05434F52 5445582D 41313500 060A0741
203 ; CORTEX-A15-NEXT: 0020: 08010902 0A050C02 14011501 17031801
204 ; CORTEX-A15-NEXT: 0030: 19012C02
205 ; CORTEX-A15-NEXT: )
206
207 ; CORTEX-M0: Name: .ARM.attributes
208 ; CORTEX-M0-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
209 ; CORTEX-M0-NEXT: Flags [ (0x0)
210 ; CORTEX-M0-NEXT: ]
211 ; CORTEX-M0-NEXT: Address: 0x0
212 ; CORTEX-M0-NEXT: Offset: 0x38
213 ; CORTEX-M0-NEXT: Size: 45
214 ; CORTEX-M0-NEXT: Link: 0
215 ; CORTEX-M0-NEXT: Info: 0
216 ; CORTEX-M0-NEXT: AddressAlignment: 1
217 ; CORTEX-M0-NEXT: EntrySize: 0
218 ; CORTEX-M0-NEXT: SectionData (
219 ; CORTEX-M0-NEXT: 0000: 412C0000 00616561 62690001 22000000
220 ; CORTEX-M0-NEXT: 0010: 05434F52 5445582D 4D300006 0C074D08
221 ; CORTEX-M0-NEXT: 0020: 00090114 01150117 03180119 01
222 ; CORTEX-M0-NEXT: )
223
224 ; CORTEX-M4: Name: .ARM.attributes
225 ; CORTEX-M4-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
226 ; CORTEX-M4-NEXT: Flags [ (0x0)
227 ; CORTEX-M4-NEXT: ]
228 ; CORTEX-M4-NEXT: Address: 0x0
229 ; CORTEX-M4-NEXT: Offset: 0x38
230 ; CORTEX-M4-NEXT: Size: 51
231 ; CORTEX-M4-NEXT: Link: 0
232 ; CORTEX-M4-NEXT: Info: 0
233 ; CORTEX-M4-NEXT: AddressAlignment: 1
234 ; CORTEX-M4-NEXT: EntrySize: 0
235 ; CORTEX-M4-NEXT: SectionData (
236 ; CORTEX-M4-NEXT: 0000: 41320000 00616561 62690001 28000000
237 ; CORTEX-M4-NEXT: 0010: 05434F52 5445582D 4D340006 0D074D08
238 ; CORTEX-M4-NEXT: 0020: 0009020A 06140115 01170318 0119011B
239 ; CORTEX-M4-NEXT: 0030: 012C00
240 ; CORTEX-M4-NEXT: )
241
242 ; CORTEX-R5: Name: .ARM.attributes
243 ; CORTEX-R5-NEXT: Type: SHT_ARM_ATTRIBUTES (0x70000003)
244 ; CORTEX-R5-NEXT: Flags [ (0x0)
245 ; CORTEX-R5-NEXT: ]
246 ; CORTEX-R5-NEXT: Address: 0x0
247 ; CORTEX-R5-NEXT: Offset: 0x3C
248 ; CORTEX-R5-NEXT: Size: 51
249 ; CORTEX-R5-NEXT: Link: 0
250 ; CORTEX-R5-NEXT: Info: 0
251 ; CORTEX-R5-NEXT: AddressAlignment: 1
252 ; CORTEX-R5-NEXT: EntrySize: 0
253 ; CORTEX-R5-NEXT: SectionData (
254 ; CORTEX-R5-NEXT: 0000: 41320000 00616561 62690001 28000000
255 ; CORTEX-R5-NEXT: 0010: 05434F52 5445582D 52350006 0A075208
256 ; CORTEX-R5-NEXT: 0020: 0109020A 04140115 01170318 0119011B
257 ; CORTEX-R5-NEXT: 0030: 012C02
258 ; CORTEX-R5-NEXT: )
259
260 define i32 @f(i64 %z) {
261 ret i32 0
262 }
0 // This tests that ARM attributes are properly encoded.
1
2 // RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \
3 // RUN: | llvm-readobj -s -sd | FileCheck %s
4
5 // Tag_CPU_name (=5)
6 .cpu Cortex-A8
7
8 // Tag_CPU_arch (=6)
9 .eabi_attribute 6, 10
10
11 // Tag_arch_profile (=7)
12 .eabi_attribute 7, 'A'
13
14 // Tag_ARM_ISA_use (=8)
15 .eabi_attribute 8, 1
16
17 // Tag_THUMB_ISA_use (=9)
18 .eabi_attribute 9, 2
19
20 // Tag_FP_arch (=10)
21 .fpu vfpv3
22
23 // Tag_Advanced_SIMD_arch (=12)
24 .eabi_attribute 12, 2
25
26 // Tag_ABI_FP_denormal (=20)
27 .eabi_attribute 20, 1
28
29 // Tag_ABI_FP_exceptions (=21)
30 .eabi_attribute 21, 1
31
32 // Tag_ABI_FP_number_model (=23)
33 .eabi_attribute 23, 1
34
35 // Tag_ABI_align_needed (=24)
36 .eabi_attribute 24, 1
37
38 // Tag_ABI_align_preserved (=25)
39 .eabi_attribute 25, 1
40
41 // Tag_ABI_HardFP_use (=27)
42 .eabi_attribute 27, 0
43
44 // Tag_ABI_VFP_args (=28)
45 .eabi_attribute 28, 1
46
47 // Tag_MPextension_use (=42)
48 .eabi_attribute 42, 1
49
50 // Tag_DIV_use (=44)
51 .eabi_attribute 44, 2
52
53 // Tag_Virtualization_use (=68)
54 .eabi_attribute 68, 3
55
56 // Check that values > 128 are encoded properly
57 .eabi_attribute 110, 160
58
59 // Check that tags > 128 are encoded properly
60 .eabi_attribute 129, 1
61 .eabi_attribute 250, 1
62
63 // CHECK: Section {
64 // CHECK: Name: .ARM.attributes
65 // CHECK-NEXT: Type: SHT_ARM_ATTRIBUTES
66 // CHECK-NEXT: Flags [ (0x0)
67 // CHECK-NEXT: ]
68 // CHECK-NEXT: Address: 0x0
69 // CHECK-NEXT: Offset: 0x34
70 // CHECK-NEXT: Size: 68
71 // CHECK-NEXT: Link: 0
72 // CHECK-NEXT: Info: 0
73 // CHECK-NEXT: AddressAlignment: 1
74 // CHECK-NEXT: EntrySize: 0
75 // CHECK-NEXT: SectionData (
76 // CHECK-NEXT: 0000: 41430000 00616561 62690001 39000000
77 // CHECK-NEXT: 0010: 05434F52 5445582D 41380006 0A074108
78 // CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119
79 // CHECK-NEXT: 0030: 011B001C 012A012C 0244036E A0018101
80 // CHECK-NEXT: 0040: 01FA0101
81 // CHECK-NEXT: )