llvm.org GIT mirror llvm / 6183f78
Add a parameter to getCopyToParts and getCopyFromParts to specify whether endian swapping should be done, and update the code to use it. This fixes some register ordering issues on big-endian systems, such as PowerPC, introduced by the recent illegal by-val arguments changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37921 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
3 changed file(s) with 230 addition(s) and 198 deletion(s). Raw diff Collapse all Expand all
611611 }
612612 };
613613 } // end namespace llvm
614
615
616 /// getCopyFromParts - Create a value that contains the
617 /// specified legal parts combined into the value they represent.
618 static SDOperand getCopyFromParts(SelectionDAG &DAG,
619 const SDOperand *Parts,
620 unsigned NumParts,
621 MVT::ValueType PartVT,
622 MVT::ValueType ValueVT,
623 bool EndianOrder,
624 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
625 if (!MVT::isVector(ValueVT) || NumParts == 1) {
626 SDOperand Val = Parts[0];
627
628 // If the value was expanded, copy from the top part.
629 if (NumParts > 1) {
630 assert(NumParts == 2 &&
631 "Cannot expand to more than 2 elts yet!");
632 SDOperand Hi = Parts[1];
633 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
634 std::swap(Val, Hi);
635 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
636 }
637
638 // Otherwise, if the value was promoted or extended, truncate it to the
639 // appropriate type.
640 if (PartVT == ValueVT)
641 return Val;
642
643 if (MVT::isVector(PartVT)) {
644 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
645 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
646 }
647
648 if (MVT::isInteger(PartVT) &&
649 MVT::isInteger(ValueVT)) {
650 if (ValueVT < PartVT) {
651 // For a truncate, see if we have any information to
652 // indicate whether the truncated bits will always be
653 // zero or sign-extension.
654 if (AssertOp != ISD::DELETED_NODE)
655 Val = DAG.getNode(AssertOp, PartVT, Val,
656 DAG.getValueType(ValueVT));
657 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
658 } else {
659 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
660 }
661 }
662
663 if (MVT::isFloatingPoint(PartVT) &&
664 MVT::isFloatingPoint(ValueVT))
665 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
666
667 if (MVT::getSizeInBits(PartVT) ==
668 MVT::getSizeInBits(ValueVT))
669 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
670
671 assert(0 && "Unknown mismatch!");
672 }
673
674 // Handle a multi-element vector.
675 MVT::ValueType IntermediateVT, RegisterVT;
676 unsigned NumIntermediates;
677 unsigned NumRegs =
678 DAG.getTargetLoweringInfo()
679 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
680 RegisterVT);
681
682 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
683 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
684 assert(RegisterVT == Parts[0].getValueType() &&
685 "Part type doesn't match part!");
686
687 // Assemble the parts into intermediate operands.
688 SmallVector Ops(NumIntermediates);
689 if (NumIntermediates == NumParts) {
690 // If the register was not expanded, truncate or copy the value,
691 // as appropriate.
692 for (unsigned i = 0; i != NumParts; ++i)
693 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
694 PartVT, IntermediateVT, EndianOrder);
695 } else if (NumParts > 0) {
696 // If the intermediate type was expanded, build the intermediate operands
697 // from the parts.
698 assert(NumIntermediates % NumParts == 0 &&
699 "Must expand into a divisible number of parts!");
700 unsigned Factor = NumIntermediates / NumParts;
701 for (unsigned i = 0; i != NumIntermediates; ++i)
702 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
703 PartVT, IntermediateVT, EndianOrder);
704 }
705
706 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
707 // operands.
708 return DAG.getNode(MVT::isVector(IntermediateVT) ?
709 ISD::CONCAT_VECTORS :
710 ISD::BUILD_VECTOR,
711 ValueVT, &Ops[0], NumParts);
712 }
713
714 /// getCopyToParts - Create a series of nodes that contain the
715 /// specified value split into legal parts.
716 static void getCopyToParts(SelectionDAG &DAG,
717 SDOperand Val,
718 SDOperand *Parts,
719 unsigned NumParts,
720 MVT::ValueType PartVT,
721 bool EndianOrder) {
722 MVT::ValueType ValueVT = Val.getValueType();
723
724 if (!MVT::isVector(ValueVT) || NumParts == 1) {
725 // If the value was expanded, copy from the parts.
726 if (NumParts > 1) {
727 for (unsigned i = 0; i != NumParts; ++i)
728 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
729 DAG.getConstant(i, MVT::i32));
730 if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
731 std::reverse(Parts, Parts + NumParts);
732 return;
733 }
734
735 // If there is a single part and the types differ, this must be
736 // a promotion.
737 if (PartVT != ValueVT) {
738 if (MVT::isVector(PartVT)) {
739 assert(MVT::isVector(ValueVT) &&
740 "Not a vector-vector cast?");
741 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
742 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
743 if (PartVT < ValueVT)
744 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
745 else
746 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
747 } else if (MVT::isFloatingPoint(PartVT) &&
748 MVT::isFloatingPoint(ValueVT)) {
749 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
750 } else if (MVT::getSizeInBits(PartVT) ==
751 MVT::getSizeInBits(ValueVT)) {
752 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
753 } else {
754 assert(0 && "Unknown mismatch!");
755 }
756 }
757 Parts[0] = Val;
758 return;
759 }
760
761 // Handle a multi-element vector.
762 MVT::ValueType IntermediateVT, RegisterVT;
763 unsigned NumIntermediates;
764 unsigned NumRegs =
765 DAG.getTargetLoweringInfo()
766 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
767 RegisterVT);
768 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
769
770 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
771 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
772
773 // Split the vector into intermediate operands.
774 SmallVector Ops(NumIntermediates);
775 for (unsigned i = 0; i != NumIntermediates; ++i)
776 if (MVT::isVector(IntermediateVT))
777 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
778 IntermediateVT, Val,
779 DAG.getConstant(i * (NumElements / NumIntermediates),
780 MVT::i32));
781 else
782 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
783 IntermediateVT, Val,
784 DAG.getConstant(i, MVT::i32));
785
786 // Split the intermediate operands into legal parts.
787 if (NumParts == NumIntermediates) {
788 // If the register was not expanded, promote or copy the value,
789 // as appropriate.
790 for (unsigned i = 0; i != NumParts; ++i)
791 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT, EndianOrder);
792 } else if (NumParts > 0) {
793 // If the intermediate type was expanded, split each the value into
794 // legal parts.
795 assert(NumParts % NumIntermediates == 0 &&
796 "Must expand into a divisible number of parts!");
797 unsigned Factor = NumParts / NumIntermediates;
798 for (unsigned i = 0; i != NumIntermediates; ++i)
799 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT, EndianOrder);
800 }
801 }
802
614803
615804 SDOperand SelectionDAGLowering::getValue(const Value *V) {
616805 SDOperand &N = NodeMap[V];
712901 SDOperand RetOp = getValue(I.getOperand(i));
713902
714903 // If this is an integer return value, we need to promote it ourselves to
715 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
716 // than sign/zero.
904 // the full width of a register, since getCopyToParts and Legalize will use
905 // ANY_EXTEND rather than sign/zero.
717906 // FIXME: C calling convention requires the return type to be promoted to
718907 // at least 32-bit. But this is not necessary for non-C calling conventions.
719908 if (MVT::isInteger(RetOp.getValueType()) &&
731920 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
732921 ExtendKind = ISD::ZERO_EXTEND;
733922 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
734 }
735 NewValues.push_back(RetOp);
736 NewValues.push_back(DAG.getConstant(false, MVT::i32));
923 NewValues.push_back(RetOp);
924 NewValues.push_back(DAG.getConstant(false, MVT::i32));
925 } else {
926 MVT::ValueType VT = RetOp.getValueType();
927 unsigned NumParts = TLI.getNumRegisters(VT);
928 MVT::ValueType PartVT = TLI.getRegisterType(VT);
929 SmallVector Parts(NumParts);
930 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, true);
931 for (unsigned i = 0; i < NumParts; ++i) {
932 NewValues.push_back(Parts[i]);
933 NewValues.push_back(DAG.getConstant(false, MVT::i32));
934 }
935 }
737936 }
738937 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
739938 &NewValues[0], NewValues.size()));
27782977 }
27792978
27802979
2781 /// getCopyFromParts - Create a value that contains the
2782 /// specified legal parts combined into the value they represent.
2783 static SDOperand getCopyFromParts(SelectionDAG &DAG,
2784 const SDOperand *Parts,
2785 unsigned NumParts,
2786 MVT::ValueType PartVT,
2787 MVT::ValueType ValueVT,
2788 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
2789 if (!MVT::isVector(ValueVT) || NumParts == 1) {
2790 SDOperand Val = Parts[0];
2791
2792 // If the value was expanded, copy from the top part.
2793 if (NumParts > 1) {
2794 assert(NumParts == 2 &&
2795 "Cannot expand to more than 2 elts yet!");
2796 SDOperand Hi = Parts[1];
2797 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2798 }
2799
2800 // Otherwise, if the value was promoted or extended, truncate it to the
2801 // appropriate type.
2802 if (PartVT == ValueVT)
2803 return Val;
2804
2805 if (MVT::isVector(PartVT)) {
2806 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
2807 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
2808 }
2809
2810 if (MVT::isInteger(PartVT) &&
2811 MVT::isInteger(ValueVT)) {
2812 if (ValueVT < PartVT) {
2813 // For a truncate, see if we have any information to
2814 // indicate whether the truncated bits will always be
2815 // zero or sign-extension.
2816 if (AssertOp != ISD::DELETED_NODE)
2817 Val = DAG.getNode(AssertOp, PartVT, Val,
2818 DAG.getValueType(ValueVT));
2819 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2820 } else {
2821 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2822 }
2823 }
2824
2825 if (MVT::isFloatingPoint(PartVT) &&
2826 MVT::isFloatingPoint(ValueVT))
2827 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2828
2829 if (MVT::getSizeInBits(PartVT) ==
2830 MVT::getSizeInBits(ValueVT))
2831 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
2832
2833 assert(0 && "Unknown mismatch!");
2834 }
2835
2836 // Handle a multi-element vector.
2837 MVT::ValueType IntermediateVT, RegisterVT;
2838 unsigned NumIntermediates;
2839 unsigned NumRegs =
2840 DAG.getTargetLoweringInfo()
2841 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
2842 RegisterVT);
2843
2844 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
2845 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
2846 assert(RegisterVT == Parts[0].getValueType() &&
2847 "Part type doesn't match part!");
2848
2849 // Assemble the parts into intermediate operands.
2850 SmallVector Ops(NumIntermediates);
2851 if (NumIntermediates == NumParts) {
2852 // If the register was not expanded, truncate or copy the value,
2853 // as appropriate.
2854 for (unsigned i = 0; i != NumParts; ++i)
2855 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, PartVT, IntermediateVT);
2856 } else if (NumParts > 0) {
2857 // If the intermediate type was expanded, build the intermediate operands
2858 // from the parts.
2859 assert(NumIntermediates % NumParts == 0 &&
2860 "Must expand into a divisible number of parts!");
2861 unsigned Factor = NumIntermediates / NumParts;
2862 for (unsigned i = 0; i != NumIntermediates; ++i)
2863 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
2864 PartVT, IntermediateVT);
2865 }
2866
2867 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
2868 // operands.
2869 return DAG.getNode(MVT::isVector(IntermediateVT) ?
2870 ISD::CONCAT_VECTORS :
2871 ISD::BUILD_VECTOR,
2872 ValueVT, &Ops[0], NumParts);
2873 }
2874
2875 /// getCopyToParts - Create a series of nodes that contain the
2876 /// specified value split into legal parts.
2877 static void getCopyToParts(SelectionDAG &DAG,
2878 SDOperand Val,
2879 SDOperand *Parts,
2880 unsigned NumParts,
2881 MVT::ValueType PartVT) {
2882 MVT::ValueType ValueVT = Val.getValueType();
2883
2884 if (!MVT::isVector(ValueVT) || NumParts == 1) {
2885 // If the value was expanded, copy from the parts.
2886 if (NumParts > 1) {
2887 for (unsigned i = 0; i != NumParts; ++i)
2888 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
2889 DAG.getConstant(i, MVT::i32));
2890 return;
2891 }
2892
2893 // If there is a single part and the types differ, this must be
2894 // a promotion.
2895 if (PartVT != ValueVT) {
2896 if (MVT::isVector(PartVT)) {
2897 assert(MVT::isVector(ValueVT) &&
2898 "Not a vector-vector cast?");
2899 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
2900 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
2901 if (PartVT < ValueVT)
2902 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
2903 else
2904 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
2905 } else if (MVT::isFloatingPoint(PartVT) &&
2906 MVT::isFloatingPoint(ValueVT)) {
2907 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
2908 } else if (MVT::getSizeInBits(PartVT) ==
2909 MVT::getSizeInBits(ValueVT)) {
2910 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
2911 } else {
2912 assert(0 && "Unknown mismatch!");
2913 }
2914 }
2915 Parts[0] = Val;
2916 return;
2917 }
2918
2919 // Handle a multi-element vector.
2920 MVT::ValueType IntermediateVT, RegisterVT;
2921 unsigned NumIntermediates;
2922 unsigned NumRegs =
2923 DAG.getTargetLoweringInfo()
2924 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
2925 RegisterVT);
2926 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
2927
2928 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
2929 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
2930
2931 // Split the vector into intermediate operands.
2932 SmallVector Ops(NumIntermediates);
2933 for (unsigned i = 0; i != NumIntermediates; ++i)
2934 if (MVT::isVector(IntermediateVT))
2935 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
2936 IntermediateVT, Val,
2937 DAG.getConstant(i * (NumElements / NumIntermediates),
2938 MVT::i32));
2939 else
2940 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2941 IntermediateVT, Val,
2942 DAG.getConstant(i, MVT::i32));
2943
2944 // Split the intermediate operands into legal parts.
2945 if (NumParts == NumIntermediates) {
2946 // If the register was not expanded, promote or copy the value,
2947 // as appropriate.
2948 for (unsigned i = 0; i != NumParts; ++i)
2949 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
2950 } else if (NumParts > 0) {
2951 // If the intermediate type was expanded, split each the value into
2952 // legal parts.
2953 assert(NumParts % NumIntermediates == 0 &&
2954 "Must expand into a divisible number of parts!");
2955 unsigned Factor = NumParts / NumIntermediates;
2956 for (unsigned i = 0; i != NumIntermediates; ++i)
2957 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
2958 }
2959 }
2960
2961
29622980 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
29632981 /// this value and returns the result as a ValueVT value. This uses
29642982 /// Chain/Flag as the input and updates them for the output Chain/Flag.
29652983 /// If the Flag pointer is NULL, no flag is used.
29662984 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
29672985 SDOperand &Chain, SDOperand *Flag)const{
2968 // Get the list of registers, in the appropriate order.
2986 // Get the list of registers.
29692987 std::vector R(Regs);
2970 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2971 std::reverse(R.begin(), R.end());
29722988
29732989 // Copy the legal parts from the registers.
29742990 unsigned NumParts = Regs.size();
29843000 }
29853001
29863002 // Assemble the legal parts into the final value.
2987 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3003 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT, true);
29883004 }
29893005
29903006 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
29933009 /// If the Flag pointer is NULL, no flag is used.
29943010 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
29953011 SDOperand &Chain, SDOperand *Flag) const {
2996 // Get the list of registers, in the appropriate order.
3012 // Get the list of registers.
29973013 std::vector R(Regs);
2998 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2999 std::reverse(R.begin(), R.end());
30003014
30013015 // Get the list of the values's legal parts.
30023016 unsigned NumParts = Regs.size();
30033017 SmallVector Parts(NumParts);
3004 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3018 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT, true);
30053019
30063020 // Copy the parts into the registers.
30073021 for (unsigned i = 0; i != NumParts; ++i) {
38783892 SmallVector Parts(NumParts);
38793893 for (unsigned j = 0; j != NumParts; ++j)
38803894 Parts[j] = SDOperand(Result, i++);
3881 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
3895 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, true));
38823896 break;
38833897 }
38843898 }
39503964 MVT::ValueType PartVT = getRegisterType(VT);
39513965 unsigned NumParts = getNumRegisters(VT);
39523966 SmallVector Parts(NumParts);
3953 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
3967 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, true);
39543968 for (unsigned i = 0; i != NumParts; ++i) {
39553969 // if it isn't first piece, alignment must be 1
39563970 unsigned MyFlags = Flags;
39904004 SmallVector Results(NumRegs);
39914005 for (unsigned i = 0; i != NumRegs; ++i)
39924006 Results[i] = Res.getValue(i);
3993 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4007 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, false, AssertOp);
39944008 }
39954009
39964010 return std::make_pair(Res, Chain);
42804294 SmallVector Chains(NumRegs);
42814295
42824296 // Copy the value by legal parts into sequential virtual registers.
4283 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4297 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT, false);
42844298 for (unsigned i = 0; i != NumRegs; ++i)
42854299 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
42864300 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
0 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {addc 4, 4, 6}
1 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {adde 3, 3, 5}
2
3 define i64 @foo(i64 %x, i64 %y) {
4 %z = add i64 %x, %y
5 ret i64 %z
6 }
0 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {li 6, 3}
1 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {li 4, 2}
2 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {li 3, 0}
3 ; RUN: llvm-as < %s | llc -march=ppc32 | grep {mr 5, 3}
4
5 declare void @bar(i64 %x, i64 %y)
6
7 define void @foo() {
8 call void @bar(i64 2, i64 3)
9 ret void
10 }