llvm.org GIT mirror llvm / 61637f3
R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg) TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237132 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
3 changed file(s) with 11 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
139139 const TargetRegisterClass *RC
140140 = TargetRegisterInfo::isVirtualRegister(Reg) ?
141141 MRI.getRegClass(Reg) :
142 TRI->getRegClass(Reg);
142 TRI->getPhysRegClass(Reg);
143143
144144 RC = TRI->getSubRegClass(RC, SubReg);
145145 for (MachineRegisterInfo::use_instr_iterator
182182 unsigned SrcReg = Copy.getOperand(1).getReg();
183183 unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
184184
185 const TargetRegisterClass *DstRC
186 = TargetRegisterInfo::isVirtualRegister(DstReg) ?
187 MRI.getRegClass(DstReg) :
188 TRI->getRegClass(DstReg);
185 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) {
186 // If the destination register is a physical register there isn't really
187 // much we can do to fix this.
188 return false;
189 }
190
191 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
189192
190193 const TargetRegisterClass *SrcRC;
191194
215215 const TargetRegisterClass *UseRC
216216 = TargetRegisterInfo::isVirtualRegister(UseReg) ?
217217 MRI.getRegClass(UseReg) :
218 TRI.getRegClass(UseReg);
218 TRI.getPhysRegClass(UseReg);
219219
220220 Imm = APInt(64, OpToFold.getImm());
221221
239239 const TargetRegisterClass *DestRC
240240 = TargetRegisterInfo::isVirtualRegister(DestReg) ?
241241 MRI.getRegClass(DestReg) :
242 TRI.getRegClass(DestReg);
242 TRI.getPhysRegClass(DestReg);
243243
244244 unsigned MovOp = TII->getMovOpcode(DestRC);
245245 if (MovOp == AMDGPU::COPY)
346346 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
347347
348348 static const TargetRegisterClass *BaseClasses[] = {
349 &AMDGPU::M0RegRegClass,
349350 &AMDGPU::VGPR_32RegClass,
350351 &AMDGPU::SReg_32RegClass,
351352 &AMDGPU::VReg_64RegClass,