llvm.org GIT mirror llvm / 6159a00
[ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293229 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
13 changed file(s) with 246 addition(s) and 133 deletion(s). Raw diff Collapse all Expand all
1515 #define LLVM_LIB_TARGET_ARM_ARM_H
1616
1717 #include "llvm/Support/CodeGen.h"
18 #include "ARMBasicBlockInfo.h"
1918 #include
19 #include
2020
2121 namespace llvm {
2222
2323 class ARMAsmPrinter;
2424 class ARMBaseTargetMachine;
25 struct BasicBlockInfo;
2526 class Function;
2627 class FunctionPass;
27 class ImmutablePass;
28 class MachineBasicBlock;
29 class MachineFunction;
2830 class MachineInstr;
2931 class MCInst;
3032 class PassRegistry;
31 class TargetLowering;
32 class TargetMachine;
3333
3434 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
3535 CodeGenOpt::Level OptLevel);
5353 void initializeARMLoadStoreOptPass(PassRegistry &);
5454 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
5555
56 } // end namespace llvm;
56 } // end namespace llvm
5757
58 #endif
58 #endif // LLVM_LIB_TARGET_ARM_ARM_H
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "ARM.h"
1413 #include "ARMBaseInstrInfo.h"
1514 #include "ARMBaseRegisterInfo.h"
1615 #include "ARMConstantPoolValue.h"
1716 #include "ARMFeatures.h"
1817 #include "ARMHazardRecognizer.h"
1918 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
2020 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/SmallVector.h"
2125 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/Triple.h"
2227 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
2329 #include "llvm/CodeGen/MachineConstantPool.h"
2430 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstr.h"
2533 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2734 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/MachineOperand.h"
2836 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
2938 #include "llvm/CodeGen/SelectionDAGNodes.h"
3039 #include "llvm/CodeGen/TargetSchedule.h"
40 #include "llvm/IR/Attributes.h"
3141 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugLoc.h"
3243 #include "llvm/IR/Function.h"
3344 #include "llvm/IR/GlobalValue.h"
3445 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCInstrDesc.h"
47 #include "llvm/MC/MCInstrItineraries.h"
3648 #include "llvm/Support/BranchProbability.h"
49 #include "llvm/Support/Casting.h"
3750 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Compiler.h"
3852 #include "llvm/Support/Debug.h"
3953 #include "llvm/Support/ErrorHandling.h"
4054 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetRegisterInfo.h"
58 #include
59 #include
60 #include
61 #include
62 #include
63 #include
64 #include
4165
4266 using namespace llvm;
4367
300324 // Walk backwards from the end of the basic block until the branch is
301325 // analyzed or we give up.
302326 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
303
304327 // Flag to be raised on unanalyzeable instructions. This is useful in cases
305328 // where we want to clean up on the end of the basic block before we bail
306329 // out.
374397 // analyzed this branch successfully.
375398 return false;
376399 }
377
378400
379401 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
380402 int *BytesRemoved) const {
599621 }
600622
601623 namespace llvm {
624
602625 template <> bool IsCPSRDead(MachineInstr *MI) {
603626 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
604627 const MachineOperand &MO = MI->getOperand(i);
612635 // all definitions of CPSR are dead
613636 return true;
614637 }
615 }
638
639 } // end namespace llvm
616640
617641 /// GetInstSize - Return the size of the specified MachineInstr.
618642 ///
12971321
12981322 // Sort the scratch registers into ascending order.
12991323 const TargetRegisterInfo &TRI = getRegisterInfo();
1300 llvm::SmallVector ScratchRegs;
1324 SmallVector ScratchRegs;
13011325 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
13021326 ScratchRegs.push_back(MI->getOperand(I).getReg());
13031327 std::sort(ScratchRegs.begin(), ScratchRegs.end(),
13141338
13151339 BB->erase(MI);
13161340 }
1317
13181341
13191342 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
13201343 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
18221845 PredReg = MI.getOperand(PIdx+1).getReg();
18231846 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
18241847 }
1825
18261848
18271849 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
18281850 if (Opc == ARM::B)
22462268 unsigned NumBits = 0;
22472269 unsigned Scale = 1;
22482270 switch (AddrMode) {
2249 case ARMII::AddrMode_i12: {
2271 case ARMII::AddrMode_i12:
22502272 ImmIdx = FrameRegIdx + 1;
22512273 InstrOffs = MI.getOperand(ImmIdx).getImm();
22522274 NumBits = 12;
22532275 break;
2254 }
2255 case ARMII::AddrMode2: {
2276 case ARMII::AddrMode2:
22562277 ImmIdx = FrameRegIdx+2;
22572278 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
22582279 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
22592280 InstrOffs *= -1;
22602281 NumBits = 12;
22612282 break;
2262 }
2263 case ARMII::AddrMode3: {
2283 case ARMII::AddrMode3:
22642284 ImmIdx = FrameRegIdx+2;
22652285 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
22662286 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
22672287 InstrOffs *= -1;
22682288 NumBits = 8;
22692289 break;
2270 }
22712290 case ARMII::AddrMode4:
22722291 case ARMII::AddrMode6:
22732292 // Can't fold any offset even if it's zero.
22742293 return false;
2275 case ARMII::AddrMode5: {
2294 case ARMII::AddrMode5:
22762295 ImmIdx = FrameRegIdx+1;
22772296 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
22782297 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
22802299 NumBits = 8;
22812300 Scale = 4;
22822301 break;
2283 }
22842302 default:
22852303 llvm_unreachable("Unsupported addressing mode!");
22862304 }
27982816 switch (UseOpc) {
27992817 default: break;
28002818 case ARM::ADDrr:
2801 case ARM::SUBrr: {
2819 case ARM::SUBrr:
28022820 if (UseOpc == ARM::SUBrr && Commute)
28032821 return false;
28042822
28142832 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
28152833 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
28162834 break;
2817 }
28182835 case ARM::ORRrr:
2819 case ARM::EORrr: {
2836 case ARM::EORrr:
28202837 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
28212838 return false;
28222839 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
28272844 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
28282845 }
28292846 break;
2830 }
28312847 case ARM::t2ADDrr:
2832 case ARM::t2SUBrr: {
2848 case ARM::t2SUBrr:
28332849 if (UseOpc == ARM::t2SUBrr && Commute)
28342850 return false;
28352851
28452861 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
28462862 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
28472863 break;
2848 }
28492864 case ARM::t2ORRrr:
2850 case ARM::t2EORrr: {
2865 case ARM::t2EORrr:
28512866 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
28522867 return false;
28532868 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
28582873 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
28592874 }
28602875 break;
2861 }
28622876 }
28632877 }
28642878 }
34843498 case ARM::t2LDMDB:
34853499 case ARM::t2LDMIA_UPD:
34863500 case ARM::t2LDMDB_UPD:
3487 LdmBypass = 1;
3501 LdmBypass = true;
34883502 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
34893503 break;
34903504 }
39593973 case ARM::t2LDRs:
39603974 case ARM::t2LDRBs:
39613975 case ARM::t2LDRHs:
3962 case ARM::t2LDRSHs: {
3976 case ARM::t2LDRSHs:
39633977 // Thumb2 mode: lsl 0-3 only.
39643978 Latency -= 2;
39653979 break;
3966 }
39673980 }
39683981 }
39693982
42934306 ExeVFP = 1,
42944307 ExeNEON = 2
42954308 };
4309
42964310 //
42974311 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
42984312 //
45774591 break;
45784592 }
45794593 }
4580
45814594 }
45824595
45834596 //===----------------------------------------------------------------------===//
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H
1414 #define LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H
1515
16 #include "ARM.h"
17 #include "ARMMachineFunctionInfo.h"
18 using namespace llvm;
16 #include "llvm/Support/MathExtras.h"
17 #include
18 #include
1919
2020 namespace llvm {
2121
4343 ///
4444 /// Because worst case padding is used, the computed offset of an aligned
4545 /// block may not actually be aligned.
46 unsigned Offset;
46 unsigned Offset = 0;
4747
4848 /// Size - Size of the basic block in bytes. If the block contains
4949 /// inline assembly, this is a worst case estimate.
5050 ///
5151 /// The size does not include any alignment padding whether from the
5252 /// beginning of the block, or from an aligned jump table at the end.
53 unsigned Size;
53 unsigned Size = 0;
5454
5555 /// KnownBits - The number of low bits in Offset that are known to be
5656 /// exact. The remaining bits of Offset are an upper bound.
57 uint8_t KnownBits;
57 uint8_t KnownBits = 0;
5858
5959 /// Unalign - When non-zero, the block contains instructions (inline asm)
6060 /// of unknown size. The real size may be smaller than Size bytes by a
6161 /// multiple of 1 << Unalign.
62 uint8_t Unalign;
62 uint8_t Unalign = 0;
6363
6464 /// PostAlign - When non-zero, the block terminator contains a .align
6565 /// directive, so the end of the block is aligned to 1 << PostAlign
6666 /// bytes.
67 uint8_t PostAlign;
67 uint8_t PostAlign = 0;
6868
69 BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0),
70 PostAlign(0) {}
69 BasicBlockInfo() = default;
7170
7271 /// Compute the number of known offset bits internally to this block.
7372 /// This number should be used to predict worst case padding when
106105
107106 } // end namespace llvm
108107
109 #endif
108 #endif // LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H
77 //===----------------------------------------------------------------------===//
88
99 #include "ARM.h"
10 #include "ARMBaseInstrInfo.h"
1011 #include "ARMBasicBlockInfo.h"
12 #include "ARMMachineFunctionInfo.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Target/TargetSubtargetInfo.h"
17 #include
18
1119 using namespace llvm;
1220
1321 namespace llvm {
6876 return BBInfo;
6977 }
7078
71 } // end namespace
79 } // end namespace llvm
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
1617 #include "ARMBasicBlockInfo.h"
1718 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMBaseInfo.h"
1921 #include "Thumb2InstrInfo.h"
20 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/DenseMap.h"
2123 #include "llvm/ADT/SmallSet.h"
2224 #include "llvm/ADT/SmallVector.h"
2325 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
2429 #include "llvm/CodeGen/MachineConstantPool.h"
30 #include "llvm/CodeGen/MachineFunction.h"
2531 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
2633 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
2735 #include "llvm/CodeGen/MachineRegisterInfo.h"
2836 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/MC/MCInstrDesc.h"
2939 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
3041 #include "llvm/Support/Debug.h"
3142 #include "llvm/Support/ErrorHandling.h"
3243 #include "llvm/Support/Format.h"
44 #include "llvm/Support/MathExtras.h"
3345 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
3546 #include
47 #include
48 #include
49 #include
50 #include
51 #include
52 #include
53
3654 using namespace llvm;
3755
3856 #define DEBUG_TYPE "arm-cp-islands"
4866 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
4967 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
5068
51
5269 static cl::opt
5370 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
5471 cl::desc("Adjust basic block layout to better use TB[BH]"));
6380 "equivalent to the TBB/TBH instructions"));
6481
6582 namespace {
83
6684 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
6785 /// requires constant pool entries to be scattered among the instructions
6886 /// inside a function. To do this, it completely ignores the normal LLVM
7593 /// CPE - A constant pool entry that has been placed somewhere, which
7694 /// tracks a list of users.
7795 class ARMConstantIslands : public MachineFunctionPass {
78
7996 std::vector BBInfo;
8097
8198 /// WaterList - A sorted list of basic blocks where islands could be placed
109126 bool NegOk;
110127 bool IsSoImm;
111128 bool KnownAlignment;
129
112130 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
113131 bool neg, bool soimm)
114132 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
115133 KnownAlignment(false) {
116134 HighWaterMark = CPEMI->getParent();
117135 }
136
118137 /// getMaxDisp - Returns the maximum displacement supported by MI.
119138 /// Correct for unknown alignment.
120139 /// Conservatively subtract 2 bytes to handle weird alignment effects.
134153 MachineInstr *CPEMI;
135154 unsigned CPI;
136155 unsigned RefCount;
156
137157 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
138158 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
139159 };
147167 /// The first half of CPEntries contains generic constants, the second half
148168 /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
149169 /// which vector it will be in here.
150 std::vector > CPEntries;
170 std::vector> CPEntries;
151171
152172 /// Maps a JT index to the offset in CPEntries containing copies of that
153173 /// table. The equivalent map for a CONSTPOOL_ENTRY is the identity.
166186 unsigned MaxDisp : 31;
167187 bool isCond : 1;
168188 unsigned UncondBr;
189
169190 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
170191 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
171192 };
194215 bool isThumb1;
195216 bool isThumb2;
196217 bool isPositionIndependentOrROPI;
218
197219 public:
198220 static char ID;
221
199222 ARMConstantIslands() : MachineFunctionPass(ID) {}
200223
201224 bool runOnMachineFunction(MachineFunction &MF) override;
263286 U.getMaxDisp(), U.NegOk, U.IsSoImm);
264287 }
265288 };
289
266290 char ARMConstantIslands::ID = 0;
267 }
291
292 } // end anonymous namespace
268293
269294 /// verify - check BBOffsets, BBSizes, alignment of islands
270295 void ARMConstantIslands::verify() {
306331 << format(" size=%#x\n", BBInfo[J].Size);
307332 }
308333 });
309 }
310
311 /// createARMConstantIslandPass - returns an instance of the constpool
312 /// island pass.
313 FunctionPass *llvm::createARMConstantIslandPass() {
314 return new ARMConstantIslands();
315334 }
316335
317336 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
872891 WaterList.insert(IP, NewBB);
873892 }
874893
875
876894 /// Split the basic block containing MI into two blocks, which are joined by
877895 /// an unconditional branch. Update data structures and renumber blocks to
878896 /// account for this change and returns the newly created block.
17961814 Bits = 11;
17971815 Scale = 2;
17981816 break;
1799 case ARM::t2Bcc: {
1817 case ARM::t2Bcc:
18001818 NewOpc = ARM::tBcc;
18011819 Bits = 8;
18021820 Scale = 2;
18031821 break;
1804 }
18051822 }
18061823 if (NewOpc) {
18071824 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
20902107 continue;
20912108 }
20922109
2093
20942110 // Now safe to delete the load and lsl. The LEA will be removed later.
20952111 CanDeleteLEA = true;
20962112 Shift->eraseFromParent();
22582274 ++NumJTInserted;
22592275 return NewBB;
22602276 }
2277
2278 /// createARMConstantIslandPass - returns an instance of the constpool
2279 /// island pass.
2280 FunctionPass *llvm::createARMConstantIslandPass() {
2281 return new ARMConstantIslands();
2282 }
1818 #include "ARMBaseRegisterInfo.h"
1919 #include "ARMConstantPoolValue.h"
2020 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
2122 #include "MCTargetDesc/ARMAddressingModes.h"
2223 #include "llvm/CodeGen/LivePhysRegs.h"
2324 #include "llvm/CodeGen/MachineFrameInfo.h"
2930 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
3031 #include "llvm/Target/TargetFrameLowering.h"
3132 #include "llvm/Target/TargetRegisterInfo.h"
33
3234 using namespace llvm;
3335
3436 #define DEBUG_TYPE "arm-pseudo"
1515 #include "ARMBaseRegisterInfo.h"
1616 #include "ARMConstantPoolValue.h"
1717 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
1819 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "MCTargetDesc/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
1927 #include "llvm/CodeGen/MachineFrameInfo.h"
2028 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
2130 #include "llvm/CodeGen/MachineInstrBuilder.h"
2231 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineOperand.h"
2333 #include "llvm/CodeGen/MachineRegisterInfo.h"
2434 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/IR/Attributes.h"
2636 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/DebugLoc.h"
2738 #include "llvm/IR/Function.h"
2839 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCDwarf.h"
41 #include "llvm/MC/MCRegisterInfo.h"
42 #include "llvm/Support/CodeGen.h"
2943 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetMachine.h"
3051 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Target/TargetRegisterInfo.h"
53 #include "llvm/Target/TargetSubtargetInfo.h"
54 #include
55 #include
56 #include
57 #include
58 #include
59 #include
60 #include
3161
3262 #define DEBUG_TYPE "arm-frame-lowering"
3363
179209 }
180210
181211 namespace {
212
182213 struct StackAdjustingInsts {
183214 struct InstInfo {
184215 MachineBasicBlock::iterator I;
195226 }
196227
197228 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
198 auto Info = find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
229 auto Info =
230 llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
199231 assert(Info != Insts.end() && "invalid sp adjusting instruction");
200232 Info->SPAdjust += ExtraBytes;
201233 }
218250 }
219251 }
220252 };
221 }
253
254 } // end anonymous namespace
222255
223256 /// Emit an instruction sequence that will align the address in
224257 /// register Reg by zero-ing out the lower bits. For versions of the
839872 // When dynamically realigning the stack, use the frame pointer for
840873 // parameters, and the stack/base pointer for locals.
841874 if (RegInfo->needsStackRealignment(MF)) {
842 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
875 assert(hasFP(MF) && "dynamic stack realignment without a FP!");
843876 if (isFixed) {
844877 FrameReg = RegInfo->getFrameRegister(MF);
845878 Offset = FPOffset;
16911724 SavedRegs.set(ARM::LR);
16921725 LRSpilled = true;
16931726 NumGPRSpills++;
1694 auto LRPos = find(UnspilledCS1GPRs, ARM::LR);
1727 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
16951728 if (LRPos != UnspilledCS1GPRs.end())
16961729 UnspilledCS1GPRs.erase(LRPos);
16971730 }
1698 auto FPPos = find(UnspilledCS1GPRs, FramePtr);
1731 auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);
16991732 if (FPPos != UnspilledCS1GPRs.end())
17001733 UnspilledCS1GPRs.erase(FPPos);
17011734 NumGPRSpills++;
18061839 NumGPRSpills++;
18071840 CS1Spilled = true;
18081841 ExtraCSSpill = true;
1809 UnspilledCS1GPRs.erase(find(UnspilledCS1GPRs, Reg));
1842 UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
18101843 if (Reg == ARM::LR)
18111844 LRSpilled = true;
18121845 }
18191852 SavedRegs.set(ARM::LR);
18201853 NumGPRSpills++;
18211854 SmallVectorImpl::iterator LRPos;
1822 LRPos = find(UnspilledCS1GPRs, (unsigned)ARM::LR);
1855 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
18231856 if (LRPos != UnspilledCS1GPRs.end())
18241857 UnspilledCS1GPRs.erase(LRPos);
18251858
None //===- ARMInstructionSelector ------------------------------------*- C++ -*-==//
0 //===- ARMInstructionSelector -----------------------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
89 /// \file
910 /// This file declares the targeting of the InstructionSelector class for ARM.
11 //
1012 //===----------------------------------------------------------------------===//
1113
1214 #ifndef LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H
1517 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
1618
1719 namespace llvm {
20
1821 class ARMBaseInstrInfo;
1922 class ARMBaseRegisterInfo;
20 class ARMBaseTargetMachine;
2123 class ARMRegisterBankInfo;
2224 class ARMSubtarget;
2325
2628 ARMInstructionSelector(const ARMSubtarget &STI,
2729 const ARMRegisterBankInfo &RBI);
2830
29 virtual bool select(MachineInstr &I) const override;
31 bool select(MachineInstr &I) const override;
3032
3133 private:
3234 const ARMBaseInstrInfo &TII;
3436 const ARMRegisterBankInfo &RBI;
3537 };
3638
37 } // End llvm namespace.
38 #endif
39 } // end namespace llvm
40
41 #endif // LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H
1313
1414 #include "ARM.h"
1515 #include "ARMAsmPrinter.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
1620 #include "MCTargetDesc/ARMBaseInfo.h"
1721 #include "MCTargetDesc/ARMMCExpr.h"
22 #include "llvm/ADT/APFloat.h"
1823 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineOperand.h"
1926 #include "llvm/IR/Constants.h"
20 #include "llvm/IR/Mangler.h"
2127 #include "llvm/MC/MCExpr.h"
2228 #include "llvm/MC/MCInst.h"
2329 #include "llvm/MC/MCContext.h"
2430 #include "llvm/MC/MCInstBuilder.h"
2531 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include
34 #include
35
2636 using namespace llvm;
27
2837
2938 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
3039 const MCSymbol *Symbol) {
7483 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
7584 MO.getMBB()->getSymbol(), OutContext));
7685 break;
77 case MachineOperand::MO_GlobalAddress: {
86 case MachineOperand::MO_GlobalAddress:
7887 MCOp = GetSymbolRef(MO,
7988 GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
8089 break;
81 }
8290 case MachineOperand::MO_ExternalSymbol:
8391 MCOp = GetSymbolRef(MO,
8492 GetExternalSymbolSymbol(MO.getSymbolName()));
77 //===----------------------------------------------------------------------===//
88
99 #include "ARMMachineFunctionInfo.h"
10 #include "ARMSubtarget.h"
1011
1112 using namespace llvm;
1213
1415
1516 ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
1617 : isThumb(MF.getSubtarget().isThumb()),
17 hasThumb2(MF.getSubtarget().hasThumb2()),
18 StByValParamsPadding(0), ArgRegsSaveSize(0), ReturnRegsCount(0),
19 HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false),
20 FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
21 GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), PICLabelUId(0),
22 VarArgsFrameIndex(0), HasITBlocks(false), ArgumentStackSize(0),
23 IsSplitCSR(false), PromotedGlobalsIncrease(0) {}
18 hasThumb2(MF.getSubtarget().hasThumb2()) {}
1313 #ifndef LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
1414 #define LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
1515
16 #include "ARMSubtarget.h"
1716 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallPtrSet.h"
1818 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include
2121
2222 namespace llvm {
2323
2828
2929 /// isThumb - True if this function is compiled under Thumb mode.
3030 /// Used to initialized Align, so must precede it.
31 bool isThumb;
31 bool isThumb = false;
3232
3333 /// hasThumb2 - True if the target architecture supports Thumb2. Do not use
3434 /// to determine if function is compiled under Thumb mode, for that use
3535 /// 'isThumb'.
36 bool hasThumb2;
36 bool hasThumb2 = false;
3737
3838 /// StByValParamsPadding - For parameter that is split between
3939 /// GPRs and memory; while recovering GPRs part, when
4040 /// StackAlignment > 4, and GPRs-part-size mod StackAlignment != 0,
4141 /// we need to insert gap before parameter start address. It allows to
4242 /// "attach" GPR-part to the part that was passed via stack.
43 unsigned StByValParamsPadding;
43 unsigned StByValParamsPadding = 0;
4444
4545 /// VarArgsRegSaveSize - Size of the register save area for vararg functions.
4646 ///
47 unsigned ArgRegsSaveSize;
47 unsigned ArgRegsSaveSize = 0;
4848
4949 /// ReturnRegsCount - Number of registers used up in the return.
50 unsigned ReturnRegsCount;
50 unsigned ReturnRegsCount = 0;
5151
5252 /// HasStackFrame - True if this function has a stack frame. Set by
5353 /// determineCalleeSaves().
54 bool HasStackFrame;
54 bool HasStackFrame = false;
5555
5656 /// RestoreSPFromFP - True if epilogue should restore SP from FP. Set by
5757 /// emitPrologue.
58 bool RestoreSPFromFP;
58 bool RestoreSPFromFP = false;
5959
6060 /// LRSpilledForFarJump - True if the LR register has been for spilled to
6161 /// enable far jump.
62 bool LRSpilledForFarJump;
62 bool LRSpilledForFarJump = false;
6363
6464 /// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer
6565 /// spill stack offset.
66 unsigned FramePtrSpillOffset;
66 unsigned FramePtrSpillOffset = 0;
6767
6868 /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
6969 /// register spills areas. For Mac OS X:
7676 ///
7777 /// Also see AlignedDPRCSRegs below. Not all D-regs need to go in area 3.
7878 /// Some may be spilled after the stack has been realigned.
79 unsigned GPRCS1Offset;
80 unsigned GPRCS2Offset;
81 unsigned DPRCSOffset;
79 unsigned GPRCS1Offset = 0;
80 unsigned GPRCS2Offset = 0;
81 unsigned DPRCSOffset = 0;
8282
8383 /// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
8484 /// areas.
85 unsigned GPRCS1Size;
86 unsigned GPRCS2Size;
87 unsigned DPRCSAlignGapSize;
88 unsigned DPRCSSize;
85 unsigned GPRCS1Size = 0;
86 unsigned GPRCS2Size = 0;
87 unsigned DPRCSAlignGapSize = 0;
88 unsigned DPRCSSize = 0;
8989
9090 /// NumAlignedDPRCS2Regs - The number of callee-saved DPRs that are saved in
9191 /// the aligned portion of the stack frame. This is always a contiguous
9494 /// We do not keep track of the frame indices used for these registers - they
9595 /// behave like any other frame index in the aligned stack frame. These
9696 /// registers also aren't included in DPRCSSize above.
97 unsigned NumAlignedDPRCS2Regs;
98
99 unsigned PICLabelUId;
97 unsigned NumAlignedDPRCS2Regs = 0;
98
99 unsigned PICLabelUId = 0;
100100
101101 /// VarArgsFrameIndex - FrameIndex for start of varargs area.
102 int VarArgsFrameIndex;
102 int VarArgsFrameIndex = 0;
103103
104104 /// HasITBlocks - True if IT blocks have been inserted.
105 bool HasITBlocks;
105 bool HasITBlocks = false;
106106
107107 /// CPEClones - Track constant pool entries clones created by Constant Island
108108 /// pass.
110110
111111 /// ArgumentStackSize - amount of bytes on stack consumed by the arguments
112112 /// being passed on the stack
113 unsigned ArgumentStackSize;
113 unsigned ArgumentStackSize = 0;
114114
115115 /// CoalescedWeights - mapping of basic blocks to the rolling counter of
116116 /// coalesced weights.
118118
119119 /// True if this function has a subset of CSRs that is handled explicitly via
120120 /// copies.
121 bool IsSplitCSR;
121 bool IsSplitCSR = false;
122122
123123 /// Globals that have had their storage promoted into the constant pool.
124124 SmallPtrSet PromotedGlobals;
125125
126126 /// The amount the literal pool has been increasedby due to promoted globals.
127 int PromotedGlobalsIncrease;
127 int PromotedGlobalsIncrease = 0;
128128
129129 public:
130 ARMFunctionInfo() :
131 isThumb(false),
132 hasThumb2(false),
133 ArgRegsSaveSize(0), ReturnRegsCount(0), HasStackFrame(false),
134 RestoreSPFromFP(false),
135 LRSpilledForFarJump(false),
136 FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
137 GPRCS1Size(0), GPRCS2Size(0), DPRCSAlignGapSize(0), DPRCSSize(0),
138 NumAlignedDPRCS2Regs(0), PICLabelUId(0),
139 VarArgsFrameIndex(0), HasITBlocks(false), IsSplitCSR(false),
140 PromotedGlobalsIncrease(0) {}
130 ARMFunctionInfo() = default;
141131
142132 explicit ARMFunctionInfo(MachineFunction &MF);
143133
249239 PromotedGlobalsIncrease = Sz;
250240 }
251241 };
252 } // End llvm namespace
253
254 #endif
242
243 } // end namespace llvm
244
245 #endif // LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "ARMBaseInstrInfo.h"
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "ARMSubtarget.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
1318 #include "Thumb1FrameLowering.h"
14 #include "ARMMachineFunctionInfo.h"
19 #include "Thumb1InstrInfo.h"
20 #include "ThumbRegisterInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/STLExtras.h"
1525 #include "llvm/CodeGen/LivePhysRegs.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
1627 #include "llvm/CodeGen/MachineFrameInfo.h"
1728 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
1830 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineOperand.h"
1932 #include "llvm/CodeGen/MachineModuleInfo.h"
2033 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/DebugLoc.h"
35 #include "llvm/MC/MCDwarf.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include
41 #include
42 #include
2143
2244 using namespace llvm;
2345
745767 }
746768
747769 // Add the low registers to the PUSH, in ascending order.
748 for (unsigned Reg : reverse(RegsToPush))
770 for (unsigned Reg : llvm::reverse(RegsToPush))
749771 PushMIB.addReg(Reg, RegState::Kill);
750772
751773 // Insert the PUSH instruction after the MOVs.
88
99 #include "ARM.h"
1010 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
1113 #include "Thumb2InstrInfo.h"
1214 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
1316 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
1420 #include "llvm/CodeGen/MachineFunctionPass.h"
1521 #include "llvm/CodeGen/MachineInstr.h"
1622 #include "llvm/CodeGen/MachineInstrBuilder.h"
1723 #include "llvm/CodeGen/MachineInstrBundle.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include
29 #include
30
1831 using namespace llvm;
1932
2033 #define DEBUG_TYPE "thumb2-it"
2336 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
2437
2538 namespace {
39
2640 class Thumb2ITBlockPass : public MachineFunctionPass {
2741 public:
2842 static char ID;
29 Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
3043
3144 bool restrictIT;
3245 const Thumb2InstrInfo *TII;
3346 const TargetRegisterInfo *TRI;
3447 ARMFunctionInfo *AFI;
48
49 Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
3550
3651 bool runOnMachineFunction(MachineFunction &Fn) override;
3752
5166 SmallSet &Uses);
5267 bool InsertITInstructions(MachineBasicBlock &MBB);
5368 };
69
5470 char Thumb2ITBlockPass::ID = 0;
55 }
71
72 } // end anonymous namespace
5673
5774 /// TrackDefUses - Tracking what registers are being defined and used by
5875 /// instructions in the IT block. This also tracks "dependencies", i.e. uses