llvm.org GIT mirror llvm / 6130f66
Refactor code. Remove duplicated functions that basically do the same thing as findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47927 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
16 changed file(s) with 178 addition(s) and 195 deletion(s). Raw diff Collapse all Expand all
129129 private: // Intermediate data structures
130130 MachineFunction *MF;
131131
132 const TargetRegisterInfo *RegInfo;
132 const TargetRegisterInfo *TRI;
133133
134134 // PhysRegInfo - Keep track of which instruction was the last def/use of a
135135 // physical register. This is a purely local property, because all physical
174174
175175 virtual bool runOnMachineFunction(MachineFunction &MF);
176176
177 /// KillsRegister - Return true if the specified instruction kills the
178 /// specified register.
179 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
180
181177 /// RegisterDefIsDead - Return true if the specified instruction defines the
182178 /// specified register, but that definition is dead.
183179 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
184180
185 /// ModifiesRegister - Return true if the specified instruction modifies the
186 /// specified register.
187 bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
188
189181 //===--------------------------------------------------------------------===//
190182 // API to update live variable information
191183
201193 /// not found.
202194 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
203195 bool AddIfNotFound = false) {
204 if (MI->addRegisterKilled(IncomingReg, RegInfo, AddIfNotFound))
196 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
205197 getVarInfo(IncomingReg).Kills.push_back(MI);
206198 }
207199
238230 /// AddIfNotFound is true, add a implicit operand if it's not found.
239231 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
240232 bool AddIfNotFound = false) {
241 if (MI->addRegisterDead(IncomingReg, RegInfo, AddIfNotFound))
233 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
242234 getVarInfo(IncomingReg).Kills.push_back(MI);
243235 }
244236
137137 ///
138138 bool isDebugLabel() const;
139139
140 /// readsRegister - Return true if the MachineInstr reads the specified
141 /// register. If TargetRegisterInfo is passed, then it also checks if there
142 /// is a read of a super-register.
143 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
144 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
145 }
146
147 /// killsRegister - Return true if the MachineInstr kills the specified
148 /// register. If TargetRegisterInfo is passed, then it also checks if there is
149 /// a kill of a super-register.
150 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
151 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
152 }
153
154 /// modifiesRegister - Return true if the MachineInstr modifies the
155 /// specified register. If TargetRegisterInfo is passed, then it also checks
156 /// if there is a def of a super-register.
157 bool modifiesRegister(unsigned Reg,
158 const TargetRegisterInfo *TRI = NULL) const {
159 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
160 }
161
162 /// registerDefIsDead - Returns true if the register is dead in this machine
163 /// instruction. If TargetRegisterInfo is passed, then it also checks
164 /// if there is a dead def of a super-register.
165 bool registerDefIsDead(unsigned Reg,
166 const TargetRegisterInfo *TRI = NULL) const {
167 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
168 }
169
140170 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
141171 /// the specific register or -1 if it is not found. It further tightening
142172 /// the search criteria to a use that kills the register if isKill is true.
143 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
144
145 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
146 /// the specific register or NULL if it is not found.
147 MachineOperand *findRegisterDefOperand(unsigned Reg);
173 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
174 const TargetRegisterInfo *TRI = NULL) const;
175
176 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
177 /// a pointer to the MachineOperand rather than an index.
178 MachineOperand *findRegisterUseOperand(unsigned Reg,bool isKill = false,
179 const TargetRegisterInfo *TRI = NULL) {
180 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
181 return (Idx == -1) ? NULL : &getOperand(Idx);
182 }
183
184 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
185 /// the specific register or -1 if it is not found. It further tightening
186 /// the search criteria to a def that is dead the register if isDead is true.
187 /// If TargetRegisterInfo is passed, then it also checks if there is a def of
188 /// a super-register.
189 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
190 const TargetRegisterInfo *TRI = NULL) const;
191
192 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
193 /// a pointer to the MachineOperand rather than an index.
194 MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false,
195 const TargetRegisterInfo *TRI = NULL) {
196 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
197 return (Idx == -1) ? NULL : &getOperand(Idx);
198 }
148199
149200 /// findFirstPredOperandIdx() - Find the index of the first operand in the
150201 /// operand list that is used to represent the predicate. It returns -1 if
126126 }
127127
128128 private:
129 const TargetRegisterInfo *RegInfo;
129 const TargetRegisterInfo *TRI;
130130 const TargetInstrInfo *TII;
131131
132132 /// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
323323
324324 // If this redefinition is dead, we need to add a dummy unit live
325325 // range covering the def slot.
326 if (lv_->RegisterDefIsDead(mi, interval.reg))
326 if (mi->registerDefIsDead(interval.reg, tri_))
327327 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
328328
329329 DOUT << " RESULT: ";
398398 // If it is not used after definition, it is considered dead at
399399 // the instruction defining it. Hence its interval is:
400400 // [defSlot(def), defSlot(def)+1)
401 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
401 if (mi->registerDefIsDead(interval.reg, tri_)) {
402402 DOUT << " dead";
403403 end = getDefIndex(start) + 1;
404404 goto exit;
409409 // [defSlot(def), useSlot(kill)+1)
410410 while (++mi != MBB->end()) {
411411 baseIndex += InstrSlots::NUM;
412 if (lv_->KillsRegister(mi, interval.reg)) {
412 if (mi->killsRegister(interval.reg, tri_)) {
413413 DOUT << " killed";
414414 end = getUseIndex(baseIndex) + 1;
415415 goto exit;
416 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
416 } else if (mi->modifiesRegister(interval.reg, tri_)) {
417417 // Another instruction redefines the register before it is ever read.
418418 // Then the register is essentially dead at the instruction that defines
419419 // it. Hence its interval is:
458458 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI);
459459 // Def of a register also defines its sub-registers.
460460 for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
461 // Avoid processing some defs more than once.
462 if (!MI->findRegisterDefOperand(*AS))
461 // If MI also modifies the sub-register explicitly, avoid processing it
462 // more than once. Do not pass in TRI here so it checks for exact match.
463 if (!MI->modifiesRegister(*AS))
463464 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
464465 }
465466 }
476477 unsigned start = baseIndex;
477478 unsigned end = start;
478479 while (mi != MBB->end()) {
479 if (lv_->KillsRegister(mi, interval.reg)) {
480 if (mi->killsRegister(interval.reg, tri_)) {
480481 DOUT << " killed";
481482 end = getUseIndex(baseIndex) + 1;
482483 goto exit;
483 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
484 } else if (mi->modifiesRegister(interval.reg, tri_)) {
484485 // Another instruction redefines the register before it is ever read.
485486 // Then the register is essentially dead at the instruction that defines
486487 // it. Hence its interval is:
841842 if (!vrm.isReMaterialized(Reg))
842843 continue;
843844 MachineInstr *ReMatMI = vrm.getReMaterializedMI(Reg);
844 int OpIdx = ReMatMI->findRegisterUseOperandIdx(li.reg);
845 if (OpIdx != -1)
846 ReMatMI->getOperand(OpIdx).setReg(NewVReg);
845 MachineOperand *UseMO = ReMatMI->findRegisterUseOperand(li.reg);
846 if (UseMO)
847 UseMO->setReg(NewVReg);
847848 }
848849 }
849850
16041605 LiveRange *LR = &LI->ranges[LI->ranges.size()-1];
16051606 unsigned LastUseIdx = getBaseIndex(LR->end);
16061607 MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
1607 int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
1608 int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false);
16081609 assert(UseIdx != -1);
16091610 if (LastUse->getOperand(UseIdx).isImplicit() ||
16101611 LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){
7575 return VI;
7676 }
7777
78 /// KillsRegister - Returns true if the machine instruction kills the specified
79 /// register.
80 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
81 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
82 const MachineOperand &MO = MI->getOperand(i);
83 if (MO.isRegister() && MO.isKill()) {
84 unsigned MOReg = MO.getReg();
85 if (MOReg == Reg ||
86 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
87 TargetRegisterInfo::isPhysicalRegister(Reg) &&
88 RegInfo->isSubRegister(MOReg, Reg)))
89 return true;
90 }
91 }
92 return false;
93 }
94
95 /// RegisterDefIsDead - Returns true if the register is dead in this machine
96 /// instruction.
97 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
98 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
99 const MachineOperand &MO = MI->getOperand(i);
100 if (MO.isRegister() && MO.isDead()) {
101 unsigned MOReg = MO.getReg();
102 if ((MOReg == Reg) ||
103 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
104 TargetRegisterInfo::isPhysicalRegister(Reg) &&
105 RegInfo->isSubRegister(MOReg, Reg)))
106 return true;
107 }
108 }
109 return false;
110 }
111
112 /// ModifiesRegister - Returns true if the machine instruction modifies the
113 /// register.
114 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
115 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
116 const MachineOperand &MO = MI->getOperand(i);
117 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
118 return true;
119 }
120 return false;
121 }
122
12378 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
12479 MachineBasicBlock *DefBlock,
12580 MachineBasicBlock *MBB,
231186 !PhysRegUsed[Reg]) {
232187 MachineInstr *Def = PhysRegInfo[Reg];
233188
234 if (!Def->findRegisterDefOperand(Reg))
189 if (!Def->modifiesRegister(Reg))
235190 Def->addOperand(MachineOperand::CreateReg(Reg,
236191 true /*IsDef*/,
237192 true /*IsImp*/));
243198 PhysRegUsed[Reg] = true;
244199
245200 // Now reset the use information for the sub-registers.
246 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
201 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
247202 unsigned SubReg = *SubRegs; ++SubRegs) {
248203 PhysRegPartUse[SubReg] = NULL;
249204 PhysRegInfo[SubReg] = MI;
250205 PhysRegUsed[SubReg] = true;
251206 }
252207
253 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
208 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
254209 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
255210 // Remember the partial use of this super-register if it was previously
256211 // defined.
260215 // No need to go up more levels. A def of a register also sets its sub-
261216 // registers. So if PhysRegInfo[SuperReg] is NULL, it means SuperReg's
262217 // super-registers are not previously defined.
263 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
218 for (const unsigned *SSRegs = TRI->getSuperRegisters(SuperReg);
264219 unsigned SSReg = *SSRegs; ++SSRegs)
265220 if (PhysRegInfo[SSReg] != NULL) {
266221 HasPrevDef = true;
280235 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
281236 SmallSet &SubKills) {
282237 if (SubKills.count(Reg) == 0) {
283 MI->addRegisterKilled(Reg, RegInfo, true);
238 MI->addRegisterKilled(Reg, TRI, true);
284239 return;
285240 }
286241
287 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
242 for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
288243 unsigned SubReg = *SubRegs; ++SubRegs)
289244 addRegisterKills(SubReg, MI, SubKills);
290245 }
299254 /// SubKills is filled with the set of sub-registers that are killed elsewhere.
300255 bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
301256 SmallSet &SubKills) {
302 const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
257 const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
303258
304259 for (; unsigned SubReg = *SubRegs; ++SubRegs) {
305260 const MachineInstr *LastRef = PhysRegInfo[SubReg];
329284
330285 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
331286 // This machine instruction kills this register.
332 RefMI->addRegisterKilled(Reg, RegInfo, true);
287 RefMI->addRegisterKilled(Reg, TRI, true);
333288 return true;
334289 }
335290
336291 // Some sub-registers are killed by another machine instruction.
337 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
292 for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
338293 unsigned SubReg = *SubRegs; ++SubRegs)
339294 addRegisterKills(SubReg, RefMI, SubKills);
340295
347302 if (PhysRegUsed[Reg]) {
348303 if (!HandlePhysRegKill(Reg, LastRef)) {
349304 if (PhysRegPartUse[Reg])
350 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
305 PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true);
351306 }
352307 } else if (PhysRegPartUse[Reg]) {
353308 // Add implicit use / kill to last partial use.
354 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
309 PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true);
355310 } else if (LastRef != MI) {
356311 // Defined, but not used. However, watch out for cases where a super-reg
357312 // is also defined on the same MI.
358 LastRef->addRegisterDead(Reg, RegInfo);
359 }
360 }
361
362 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
313 LastRef->addRegisterDead(Reg, TRI);
314 }
315 }
316
317 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
363318 unsigned SubReg = *SubRegs; ++SubRegs) {
364319 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
365320 if (PhysRegUsed[SubReg]) {
366321 if (!HandlePhysRegKill(SubReg, LastRef)) {
367322 if (PhysRegPartUse[SubReg])
368 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
323 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true);
369324 }
370325 } else if (PhysRegPartUse[SubReg]) {
371326 // Add implicit use / kill to last use of a sub-register.
372 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
327 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true);
373328 } else if (LastRef != MI) {
374329 // This must be a def of the subreg on the same MI.
375 LastRef->addRegisterDead(SubReg, RegInfo);
330 LastRef->addRegisterDead(SubReg, TRI);
376331 }
377332 }
378333 }
379334
380335 if (MI) {
381 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
336 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
382337 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
383338 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
384339 // The larger register is previously defined. Now a smaller part is
403358 PhysRegPartDef[Reg].clear();
404359 PhysRegPartUse[Reg] = NULL;
405360
406 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
361 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
407362 unsigned SubReg = *SubRegs; ++SubRegs) {
408363 PhysRegInfo[SubReg] = MI;
409364 PhysRegUsed[SubReg] = false;
415370
416371 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
417372 MF = &mf;
418 RegInfo = MF->getTarget().getRegisterInfo();
373 TRI = MF->getTarget().getRegisterInfo();
419374 MachineRegisterInfo& MRI = mf.getRegInfo();
420 assert(RegInfo && "Target doesn't have register information?");
421
422 ReservedRegisters = RegInfo->getReservedRegs(mf);
423
424 unsigned NumRegs = RegInfo->getNumRegs();
375
376 ReservedRegisters = TRI->getReservedRegs(mf);
377
378 unsigned NumRegs = TRI->getNumRegs();
425379 PhysRegInfo = new MachineInstr*[NumRegs];
426380 PhysRegUsed = new bool[NumRegs];
427381 PhysRegPartUse = new MachineInstr*[NumRegs];
532486 HandlePhysRegUse(*I, Ret);
533487
534488 // Add live-out registers as implicit uses.
535 if (Ret->findRegisterUseOperandIdx(*I) == -1)
489 if (!Ret->readsRegister(*I))
536490 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
537491 }
538492 }
561515 VirtRegInfo[i]
562516 .Kills[j]->addRegisterDead(i +
563517 TargetRegisterInfo::FirstVirtualRegister,
564 RegInfo);
518 TRI);
565519 else
566520 VirtRegInfo[i]
567521 .Kills[j]->addRegisterKilled(i +
568522 TargetRegisterInfo::FirstVirtualRegister,
569 RegInfo);
523 TRI);
570524
571525 // Check to make sure there are no unreachable blocks in the MC CFG for the
572526 // function. If so, it is due to a bug in the instruction selector or some
531531 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
532532 /// the specific register or -1 if it is not found. It further tightening
533533 /// the search criteria to a use that kills the register if isKill is true.
534 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
534 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
535 const TargetRegisterInfo *TRI) const {
535536 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
536537 const MachineOperand &MO = getOperand(i);
537 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
538 if (!MO.isRegister() || !MO.isUse())
539 continue;
540 unsigned MOReg = MO.getReg();
541 if (!MOReg)
542 continue;
543 if (MOReg == Reg ||
544 (TRI &&
545 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
546 TargetRegisterInfo::isPhysicalRegister(Reg) &&
547 TRI->isSubRegister(MOReg, Reg)))
538548 if (!isKill || MO.isKill())
539549 return i;
540550 }
541551 return -1;
542552 }
543553
544 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
545 /// the specific register or NULL if it is not found.
546 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
554 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
555 /// the specific register or -1 if it is not found. It further tightening
556 /// the search criteria to a def that is dead the register if isDead is true.
557 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
558 const TargetRegisterInfo *TRI) const {
547559 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
548 MachineOperand &MO = getOperand(i);
549 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
550 return &MO;
551 }
552 return NULL;
560 const MachineOperand &MO = getOperand(i);
561 if (!MO.isRegister() || !MO.isDef())
562 continue;
563 unsigned MOReg = MO.getReg();
564 if (MOReg == Reg ||
565 (TRI &&
566 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
567 TargetRegisterInfo::isPhysicalRegister(Reg) &&
568 TRI->isSubRegister(MOReg, Reg)))
569 if (!isDead || MO.isDead())
570 return i;
571 }
572 return -1;
553573 }
554574
555575 /// findFirstPredOperandIdx() - Find the index of the first operand in the
160160 LV->removeVirtualRegistersKilled(MPhi);
161161
162162 // If the result is dead, update LV.
163 if (LV->RegisterDefIsDead(MPhi, DestReg)) {
163 if (MPhi->registerDefIsDead(DestReg)) {
164164 LV->addVirtualRegisterDead(DestReg, PHICopy);
165165 LV->removeVirtualRegistersDead(MPhi);
166166 }
305305 // If the instruction reads the register that's spilled, (e.g. this can
306306 // happen if it is a move to a physical register), then the spill
307307 // instruction is not a kill.
308 bool isKill = !(I != MBB.end() &&
309 I->findRegisterUseOperandIdx(PhysReg) != -1);
308 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
310309 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
311310 ++NumStores; // Update statistics
312311 }
2828 void RegScavenger::setUsed(unsigned Reg) {
2929 RegsAvailable.reset(Reg);
3030
31 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
31 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
3232 unsigned SubReg = *SubRegs; ++SubRegs)
3333 RegsAvailable.reset(SubReg);
3434 }
3737 void RegScavenger::setUnused(unsigned Reg) {
3838 RegsAvailable.set(Reg);
3939
40 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
4141 unsigned SubReg = *SubRegs; ++SubRegs)
4242 RegsAvailable.set(SubReg);
4343 }
4646 const MachineFunction &MF = *mbb->getParent();
4747 const TargetMachine &TM = MF.getTarget();
4848 TII = TM.getInstrInfo();
49 RegInfo = TM.getRegisterInfo();
50
51 assert((NumPhysRegs == 0 || NumPhysRegs == RegInfo->getNumRegs()) &&
49 TRI = TM.getRegisterInfo();
50
51 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
5252 "Target changed?");
5353
5454 if (!MBB) {
55 NumPhysRegs = RegInfo->getNumRegs();
55 NumPhysRegs = TRI->getNumRegs();
5656 RegsAvailable.resize(NumPhysRegs);
5757
5858 // Create reserved registers bitvector.
59 ReservedRegs = RegInfo->getReservedRegs(MF);
59 ReservedRegs = TRI->getReservedRegs(MF);
6060
6161 // Create callee-saved registers bitvector.
6262 CalleeSavedRegs.resize(NumPhysRegs);
63 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
63 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
6464 if (CSRegs != NULL)
6565 for (unsigned i = 0; CSRegs[i]; ++i)
6666 CalleeSavedRegs.set(CSRegs[i]);
9292 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
9393 ScavengingFrameIndex, ScavengedRC);
9494 MachineBasicBlock::iterator II = prior(MBBI);
95 RegInfo->eliminateFrameIndex(II, 0, this);
95 TRI->eliminateFrameIndex(II, 0, this);
9696 setUsed(ScavengedReg);
9797 ScavengedReg = 0;
9898 ScavengedRC = NULL;
137137 if (MO.isKill() && !isReserved(Reg)) {
138138 ChangedRegs.set(Reg);
139139
140 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
140 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
141141 unsigned SubReg = *SubRegs; ++SubRegs)
142142 ChangedRegs.set(SubReg);
143143 }
209209 ChangedRegs.set(Reg);
210210
211211 // Set the sub-registers as "used".
212 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
212 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
213213 unsigned SubReg = *SubRegs; ++SubRegs)
214214 ChangedRegs.set(SubReg);
215215 }
266266 /// calcDistanceToUse - Calculate the distance to the first use of the
267267 /// specified register.
268268 static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
269 MachineBasicBlock::iterator I, unsigned Reg) {
269 MachineBasicBlock::iterator I, unsigned Reg,
270 const TargetRegisterInfo *TRI) {
270271 unsigned Dist = 0;
271272 I = next(I);
272273 while (I != MBB->end()) {
273274 Dist++;
274 if (I->findRegisterUseOperandIdx(Reg) != -1)
275 if (I->readsRegister(Reg, TRI))
275276 return Dist;
276277 I = next(I);
277278 }
301302 unsigned MaxDist = 0;
302303 int Reg = Candidates.find_first();
303304 while (Reg != -1) {
304 unsigned Dist = calcDistanceToUse(MBB, I, Reg);
305 unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
305306 if (Dist >= MaxDist) {
306307 MaxDist = Dist;
307308 SReg = Reg;
314315 TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
315316 ScavengingFrameIndex, ScavengedRC);
316317 MachineBasicBlock::iterator II = prior(I);
317 RegInfo->eliminateFrameIndex(II, SPAdj, this);
318 TRI->eliminateFrameIndex(II, SPAdj, this);
318319 }
319320
320321 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
321322 MachineBasicBlock::iterator II = prior(I);
322 RegInfo->eliminateFrameIndex(II, SPAdj, this);
323 TRI->eliminateFrameIndex(II, SPAdj, this);
323324 ScavengedReg = SReg;
324325 ScavengedRC = RC;
325326
306306 MBB->insert(DefMI, NewMI);
307307 MBB->erase(DefMI);
308308 }
309 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg);
309 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
310310 NewMI->getOperand(OpIdx).setIsKill();
311311
312312 // Update uses of IntA of the specific Val# with IntB.
587587
588588 // Check if it is necessary to propagate "isDead" property before intervals
589589 // are joined.
590 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
590 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
591591 bool isDead = mopd->isDead();
592592 bool isShorten = false;
593593 unsigned SrcStart = 0, RemoveStart = 0;
616616 RemoveEnd = SrcEnd;
617617 } else {
618618 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
619 if (SrcMI) {
620 MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
621 if (mops)
622 // A dead def should have a single cycle interval.
623 ++RemoveStart;
624 }
619 if (SrcMI && SrcMI->modifiesRegister(SrcReg, tri_))
620 // A dead def should have a single cycle interval.
621 ++RemoveStart;
625622 }
626623 }
627624 }
671668 } else {
672669 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
673670 if (SrcMI) {
674 MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
675 if (mops)
676 mops->setIsDead();
671 int DeadIdx = SrcMI->findRegisterDefOperandIdx(SrcReg, false, tri_);
672 if (DeadIdx != -1)
673 SrcMI->getOperand(DeadIdx).setIsDead();
677674 }
678675 }
679676 }
14601457 }
14611458
14621459
1463 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1464 /// register. It returns NULL if the def is not found.
1465 /// FIXME: Move to MachineInstr.
1466 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI,
1467 unsigned Reg) const {
1468 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1469 MachineOperand &MO = MI->getOperand(i);
1470 if (MO.isRegister() && MO.isDef() &&
1471 tri_->regsOverlap(MO.getReg(), Reg))
1472 return &MO;
1473 }
1474 return NULL;
1475 }
1476
14771460 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
14781461 /// due to live range lengthening as the result of coalescing.
14791462 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
15471530 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) {
15481531 // remove from def list
15491532 LiveInterval &RegInt = li_->getOrCreateInterval(srcReg);
1550 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1533 MachineOperand *MO = mii->findRegisterDefOperand(dstReg, false);
15511534 // If def of this move instruction is dead, remove its live range from
15521535 // the dstination register's live interval.
15531536 if (MO->isDead()) {
205205 MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
206206 unsigned &LastUseIdx) const;
207207
208 /// findDefOperand - Returns the MachineOperand that is a def of the specific
209 /// register. It returns NULL if the def is not found.
210 MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg) const;
211
212208 void printRegName(unsigned reg) const;
213209 };
214210
350350 break;
351351 }
352352 // Store KillInsts if they match up with the definition
353 } else if (LV.KillsRegister(curr, a)) {
353 } else if (curr->killsRegister(a)) {
354354 if (def == MRI->getVRegDef(a)) {
355355 kill = curr;
356 } else if (LV.KillsRegister(curr, b)) {
356 } else if (curr->killsRegister(b)) {
357357 if (def == MRI->getVRegDef(b)) {
358358 kill = curr;
359359 }
372372 break;
373373 }
374374 // Save KillInsts of First
375 } else if (LV.KillsRegister(curr, a)) {
375 } else if (curr->killsRegister(a)) {
376376 kill = curr;
377377 }
378378 // Symmetric with the above
385385 interference = false;
386386 break;
387387 }
388 } else if (LV.KillsRegister(curr, b)) {
388 } else if (curr->killsRegister(b)) {
389389 kill = curr;
390390 }
391391 }
138138 // rearrange the code to make it so. Making it the killing user will
139139 // allow us to coalesce A and B together, eliminating the copy we are
140140 // about to insert.
141 if (!LV.KillsRegister(mi, regB)) {
141 if (!mi->killsRegister(regB)) {
142142 // If this instruction is commutative, check to see if C dies. If
143143 // so, swap the B and C operands. This makes the live ranges of A
144144 // and C joinable.
147147 assert(mi->getOperand(3-si).isRegister() &&
148148 "Not a proper commutative instruction!");
149149 unsigned regC = mi->getOperand(3-si).getReg();
150 if (LV.KillsRegister(mi, regC)) {
150 if (mi->killsRegister(regC)) {
151151 DOUT << "2addr: COMMUTING : " << *mi;
152152 MachineInstr *NewMI = TII.commuteInstruction(mi);
153153 if (NewMI == 0) {
861861 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
862862 if (DeadStore && (MR & VirtRegMap::isModRef)) {
863863 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
864 if (!PhysReg ||
865 DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
864 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
866865 continue;
867866 UnfoldPR = PhysReg;
868867 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
907906 assert(NewMIs.size() == 1);
908907 MachineInstr *NewMI = NewMIs.back();
909908 NewMIs.clear();
910 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg);
909 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
911910 assert(Idx != -1);
912911 SmallVector Ops;
913912 Ops.push_back(Idx);
14091408 // the physreg.
14101409 if (PhysReg &&
14111410 !TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
1412 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
1411 DeadStore->killsRegister(PhysReg) &&
14131412 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
14141413 MBB.insert(MII, NewMIs[0]);
14151414 NewStore = NewMIs[1];
293293 for (unsigned j = 0; j < 2; ++j) {
294294 // Look at the two new MI's in reverse order.
295295 MachineInstr *NewMI = NewMIs[j];
296 int NIdx = NewMI->findRegisterUseOperandIdx(Reg);
297 if (NIdx == -1)
296 if (!NewMI->readsRegister(Reg))
298297 continue;
299298 LV.addVirtualRegisterKilled(Reg, NewMI);
300299 if (VI.removeKill(MI))
152152 }
153153
154154 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
155
156 /// KillsRegister - Return true if the specified instruction kills (is the last
157 /// use of) the specified register. Note that this routine does not check for
158 /// kills of subregisters.
159 static bool KillsRegister(MachineInstr *MI, unsigned Reg) {
160 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
161 MachineOperand &MO = MI->getOperand(i);
162 if (MO.isRegister() && MO.isKill() && MO.getReg() == Reg)
163 return true;
164 }
165 return false;
166 }
167155
168156 /// getFPReg - Return the X86::FPx register number for the specified operand.
169157 /// For example, this returns 3 for X86::FP3.
609597
610598 // Is this the last use of the source register?
611599 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
612 bool KillsSrc = KillsRegister(MI, X86::FP0+Reg);
600 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
613601
614602 // FISTP64m is strange because there isn't a non-popping versions.
615603 // If we have one _and_ we don't want to pop the operand, duplicate the value
668656
669657 // Is this the last use of the source register?
670658 unsigned Reg = getFPReg(MI->getOperand(1));
671 bool KillsSrc = KillsRegister(MI, X86::FP0+Reg);
659 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
672660
673661 if (KillsSrc) {
674662 // If this is the last use of the source register, just make sure it's on
777765 unsigned Dest = getFPReg(MI->getOperand(0));
778766 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
779767 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
780 bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0);
781 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
768 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
769 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
782770
783771 unsigned TOS = getStackEntry(0);
784772
874862 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
875863 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
876864 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
877 bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0);
878 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
865 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
866 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
879867
880868 // Make sure the first operand is on the top of stack, the other one can be
881869 // anywhere.
900888
901889 unsigned Op0 = getFPReg(MI->getOperand(0));
902890 unsigned Op1 = getFPReg(MI->getOperand(2));
903 bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1);
891 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
904892
905893 // The first operand *must* be on the top of the stack.
906894 moveToTop(Op0, I);
957945 unsigned SrcReg = getFPReg(MI->getOperand(1));
958946 unsigned DestReg = getFPReg(MI->getOperand(0));
959947
960 if (KillsRegister(MI, X86::FP0+SrcReg)) {
948 if (MI->killsRegister(X86::FP0+SrcReg)) {
961949 // If the input operand is killed, we can just change the owner of the
962950 // incoming stack slot into the result.
963951 unsigned Slot = getSlot(SrcReg);