llvm.org GIT mirror llvm / 60d8767
Truncate the immediate in logical operation to the register width And continue to produce an error if the 32 most significant bits are not all ones or zeros. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212520 91177308-0d34-0410-b5e6-96231b3b80d8 Arnaud A. de Grandmaison 6 years ago
3 changed file(s) with 39 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
618618 const MCConstantExpr *MCE = dyn_cast(getImm());
619619 if (!MCE)
620620 return false;
621 return AArch64_AM::isLogicalImmediate(MCE->getValue(), 32);
621 int64_t Val = MCE->getValue();
622 if (Val >> 32 != 0 && Val >> 32 != ~0LL)
623 return false;
624 Val &= 0xFFFFFFFF;
625 return AArch64_AM::isLogicalImmediate(Val, 32);
622626 }
623627 bool isLogicalImm64() const {
624628 if (!isImm())
13591363 assert(N == 1 && "Invalid number of operands!");
13601364 const MCConstantExpr *MCE = dyn_cast(getImm());
13611365 assert(MCE && "Invalid logical immediate operand!");
1362 uint64_t encoding = AArch64_AM::encodeLogicalImmediate(MCE->getValue(), 32);
1366 uint64_t encoding =
1367 AArch64_AM::encodeLogicalImmediate(MCE->getValue() & 0xFFFFFFFF, 32);
13631368 Inst.addOperand(MCOperand::CreateImm(encoding));
13641369 }
13651370
726726 // CHECK-ERROR-NEXT: error: invalid operand for instruction
727727 // CHECK-ERROR-NEXT: ngcs x2, sp
728728 // CHECK-ERROR-NEXT: ^
729
730 //------------------------------------------------------------------------------
731 // Logical (immediates)
732 //------------------------------------------------------------------------------
733
734 and w2, w3, #4294967296
735 eor w2, w3, #4294967296
736 orr w2, w3, #4294967296
737 ands w2, w3, #4294967296
738 // CHECK-ERROR: error: expected compatible register or logical immediate
739 // CHECK-ERROR-NEXT: and w2, w3, #4294967296
740 // CHECK-ERROR-NEXT: ^
741 // CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
742 // CHECK-ERROR-NEXT: eor w2, w3, #4294967296
743 // CHECK-ERROR-NEXT: ^
744 // CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
745 // CHECK-ERROR-NEXT: orr w2, w3, #4294967296
746 // CHECK-ERROR-NEXT: ^
747 // CHECK-ERROR-NEXT: error: expected compatible register or logical immediate
748 // CHECK-ERROR-NEXT: ands w2, w3, #4294967296
749 // CHECK-ERROR-NEXT: ^
729750
730751 //------------------------------------------------------------------------------
731752 // Bitfield
32433243 mov x10, #0xaaaaaaaaaaaaaaaa
32443244 // CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32]
32453245 // CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
3246
3247 // The Imm field of logicalImm operations has to be truncated to the
3248 // register width, i.e. 32 bits
3249 and w2, w3, #-3
3250 orr w0, w1, #~2
3251 eor w16, w17, #-7
3252 ands w19, w20, #~15
3253 // CHECK: and w2, w3, #0xfffffffd // encoding: [0x62,0x78,0x1e,0x12]
3254 // CHECK: orr w0, w1, #0xfffffffd // encoding: [0x20,0x78,0x1e,0x32]
3255 // CHECK: eor w16, w17, #0xfffffff9 // encoding: [0x30,0x76,0x1d,0x52]
3256 // CHECK: ands w19, w20, #0xfffffff0 // encoding: [0x93,0x6e,0x1c,0x72]
32463257
32473258 //------------------------------------------------------------------------------
32483259 // Logical (shifted register)