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ARM 'vzip.32 Dd, Dm' is a pseudo-instruction. While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
3 changed file(s) with 7 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
28242824 case MVT::v8i8: Opc = ARM::VZIPd8; break;
28252825 case MVT::v4i16: Opc = ARM::VZIPd16; break;
28262826 case MVT::v2f32:
2827 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2827 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2828 case MVT::v2i32: Opc = ARM::VTRNd32; break;
28282829 case MVT::v16i8: Opc = ARM::VZIPq8; break;
28292830 case MVT::v8i16: Opc = ARM::VZIPq16; break;
28302831 case MVT::v4f32:
53875387
53885388 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
53895389 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5390 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5390 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5391 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5392 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
53915393
53925394 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
53935395 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5858 vzip.8 q9, q8
5959 vzip.16 q9, q8
6060 vzip.32 q9, q8
61 vzip.32 d2, d3
6162
6263 @ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3]
6364 @ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3]
6970 @ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3]
7071 @ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3]
7172 @ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3]
73 @ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3]
7274
7375
7476 @ VTRN alternate size suffices