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Merging r243636: ------------------------------------------------------------------------ r243636 | vkalintiris | 2015-07-30 04:51:44 -0700 (Thu, 30 Jul 2015) | 34 lines [mips][FastISel] Apply only zero-extension to constants prior to their materialization. Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243648 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
3 changed file(s) with 15 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
289289 return 0;
290290 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
291291 const ConstantInt *CI = cast(C);
292 int64_t Imm;
293 if ((VT != MVT::i1) && CI->isNegative())
294 Imm = CI->getSExtValue();
295 else
296 Imm = CI->getZExtValue();
297 return materialize32BitInt(Imm, RC);
292 return materialize32BitInt(CI->getZExtValue(), RC);
298293 }
299294
300295 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
282282 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
283283 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
284284 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
285 ; CHECK-DAG: addiu $[[CONST_Neg89:[0-9]+]], $zero, -89
286 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]]
285 ; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167
286 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]]
287287 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
288288 ; CHECK: .end andUc1
289289 ret void
344344 ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]])
345345 ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
346346 ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
347 ; CHECK-DAG: addiu $[[CONST_neg18:[0-9]+]], $zero, -18
348 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]]
347 ; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238
348 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]]
349349 ; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
350350 ; CHECK: .end orUc1
351351 ret void
468468 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
469469 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
470470 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
471 ; CHECK-DAG: addiu $[[CONST_Neg4185:[0-9]+]], $zero, -4185
472 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]]
471 ; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351
472 ; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]]
473473 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
474474 ; CHECK: .end andUs1
475475 ret void
519519 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
520520 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
521521 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
522 ; CHECK-DAG: addiu $[[CONST_neg4591:[0-9]+]], $zero, -4591
523 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]]
522 ; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945
523 ; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]]
524524 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
525525 ; CHECK: .end orUs1
526526 ret void
582582 ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
583583 ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
584584 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
585 ; CHECK-DAG: addiu $[[CONST_Neg5512:[0-9]+]], $zero, -5512
586 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]]
585 ; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024
586 ; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]]
587587 ; CHECK: sh $[[RES]], 0($[[US_ADDR]])
588588 ; CHECK: .end xorUs1
589589 ret void
2121 entry:
2222 store i32 -32768, i32* @ijk, align 4
2323 ; CHECK: .ent si2_2
24 ; CHECK: addiu $[[REG1:[0-9]+]], $zero, -32768
25 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
26 ; CHECK: sw $[[REG1]], 0($[[REG2]])
24 ; CHECK: lui $[[REG1:[0-9]+]], 65535
25 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
26 ; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}})
27 ; CHECK: sw $[[REG2]], 0($[[REG3]])
2728 ret void
2829 }
2930