llvm.org GIT mirror llvm / 6035518
Have MachineFunction cache a pointer to the subtarget to make lookups shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
136 changed file(s) with 492 addition(s) and 740 deletion(s). Raw diff Collapse all Expand all
3838 class MCContext;
3939 class Pass;
4040 class TargetMachine;
41 class TargetSubtargetInfo;
4142 class TargetRegisterClass;
4243 struct MachinePointerInfo;
4344
7576 class MachineFunction {
7677 const Function *Fn;
7778 const TargetMachine &Target;
79 const TargetSubtargetInfo *STI;
7880 MCContext &Ctx;
7981 MachineModuleInfo &MMI;
8082 GCModuleInfo *GMI;
161163 /// getTarget - Return the target machine this machine code is compiled with
162164 ///
163165 const TargetMachine &getTarget() const { return Target; }
166
167 /// getSubtarget - Return the subtarget for which this machine code is being
168 /// compiled.
169 const TargetSubtargetInfo &getSubtarget() const { return *STI; }
170 void setSubtarget(TargetSubtargetInfo *ST) { STI = ST; }
164171
165172 /// getRegInfo - Return information about the registers currently in use.
166173 ///
1919 #include "llvm/ADT/StringMap.h"
2020 #include "llvm/ADT/ilist.h"
2121 #include "llvm/CodeGen/DAGCombine.h"
22 #include "llvm/CodeGen/MachineFunction.h"
2223 #include "llvm/CodeGen/SelectionDAGNodes.h"
2324 #include "llvm/Support/RecyclingAllocator.h"
2425 #include "llvm/Target/TargetMachine.h"
275276
276277 MachineFunction &getMachineFunction() const { return *MF; }
277278 const TargetMachine &getTarget() const { return TM; }
279 const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
278280 const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
279281 const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; }
280282 LLVMContext *getContext() const {return Context; }
114114 MachineFunction &MFi, const RegisterClassInfo &RCI,
115115 TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
116116 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
117 TII(MF.getTarget().getSubtargetImpl()->getInstrInfo()),
118 TRI(MF.getTarget().getSubtargetImpl()->getRegisterInfo()),
119 RegClassInfo(RCI), State(nullptr) {
117 TII(MF.getSubtarget().getInstrInfo()),
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
119 State(nullptr) {
120120 /* Collect a bitset of all registers that are only broken if they
121121 are on the critical path. */
122122 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
11201120 /// by the current function to the current output stream.
11211121 ///
11221122 void AsmPrinter::EmitJumpTableInfo() {
1123 const DataLayout *DL = MF->getTarget().getSubtargetImpl()->getDataLayout();
1123 const DataLayout *DL = MF->getSubtarget().getDataLayout();
11241124 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
11251125 if (!MJTI) return;
11261126 if (MJTI->getEntryKind() == MachineJumpTableInfo::EK_Inline) return;
9292 bool EnableTailMerge = !MF.getTarget().requiresStructuredCFG() &&
9393 PassConfig->getEnableTailMerge();
9494 BranchFolder Folder(EnableTailMerge, /*CommonHoist=*/true);
95 return Folder.OptimizeFunction(
96 MF, MF.getTarget().getSubtargetImpl()->getInstrInfo(),
97 MF.getTarget().getSubtargetImpl()->getRegisterInfo(),
98 getAnalysisIfAvailable());
95 return Folder.OptimizeFunction(MF, MF.getSubtarget().getInstrInfo(),
96 MF.getSubtarget().getRegisterInfo(),
97 getAnalysisIfAvailable());
9998 }
10099
101100
9595 void
9696 VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) {
9797 MachineRegisterInfo &mri = MF.getRegInfo();
98 const TargetRegisterInfo &tri =
99 *MF.getTarget().getSubtargetImpl()->getRegisterInfo();
98 const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
10099 MachineBasicBlock *mbb = nullptr;
101100 MachineLoop *loop = nullptr;
102101 bool isExiting = false;
187186 // it is a preferred candidate for spilling.
188187 // FIXME: this gets much more complicated once we support non-trivial
189188 // re-materialization.
190 if (isRematerializable(li, LIS,
191 *MF.getTarget().getSubtargetImpl()->getInstrInfo()))
189 if (isRematerializable(li, LIS, *MF.getSubtarget().getInstrInfo()))
192190 totalWeight *= 0.5F;
193191
194192 li.weight = normalize(totalWeight, li.getSize());
3030 CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
3131 const RegisterClassInfo &RCI)
3232 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
33 TII(MF.getTarget().getSubtargetImpl()->getInstrInfo()),
34 TRI(MF.getTarget().getSubtargetImpl()->getRegisterInfo()),
35 RegClassInfo(RCI), Classes(TRI->getNumRegs(), nullptr),
36 KillIndices(TRI->getNumRegs(), 0), DefIndices(TRI->getNumRegs(), 0),
37 KeepRegs(TRI->getNumRegs(), false) {}
33 TII(MF.getSubtarget().getInstrInfo()),
34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
35 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
36 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
3837
3938 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
4039 }
9191
9292 bool AnyChanges = false;
9393 MRI = &MF.getRegInfo();
94 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
95 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
94 TRI = MF.getSubtarget().getRegisterInfo();
95 TII = MF.getSubtarget().getInstrInfo();
9696
9797 // Loop over all instructions in all blocks, from bottom to top, so that it's
9898 // more likely that chains of dependent but ultimately dead instructions will
152152 public:
153153 /// runOnMachineFunction - Initialize per-function data structures.
154154 void runOnMachineFunction(MachineFunction &MF) {
155 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
156 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
155 TII = MF.getSubtarget().getInstrInfo();
156 TRI = MF.getSubtarget().getRegisterInfo();
157157 MRI = &MF.getRegInfo();
158158 LiveRegUnits.clear();
159159 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
781781 .enableEarlyIfConversion())
782782 return false;
783783
784 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
785 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
784 TII = MF.getSubtarget().getInstrInfo();
785 TRI = MF.getSubtarget().getRegisterInfo();
786786 SchedModel =
787787 MF.getTarget().getSubtarget().getSchedModel();
788788 MRI = &MF.getRegInfo();
5353 MCSymbol *ErlangGC::InsertLabel(MachineBasicBlock &MBB,
5454 MachineBasicBlock::iterator MI,
5555 DebugLoc DL) const {
56 const TargetInstrInfo *TII =
57 MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
56 const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
5857 MCSymbol *Label = MBB.getParent()->getContext().CreateTempSymbol();
5958 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
6059 return Label;
714714
715715 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
716716 MF = &mf;
717 TII = MF->getTarget().getSubtargetImpl()->getInstrInfo();
718 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
717 TII = MF->getSubtarget().getInstrInfo();
718 TRI = MF->getSubtarget().getRegisterInfo();
719719 LiveRegs = nullptr;
720720 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
721721
4646
4747 bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) {
4848 bool Changed = false;
49 const TargetLowering *TLI =
50 MF.getTarget().getSubtargetImpl()->getTargetLowering();
49 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
5150
5251 // Iterate through each instruction in the function, looking for pseudos.
5352 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
183183 DEBUG(dbgs() << "Machine Function\n"
184184 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
185185 << "********** Function: " << MF.getName() << '\n');
186 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
187 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
186 TRI = MF.getSubtarget().getRegisterInfo();
187 TII = MF.getSubtarget().getInstrInfo();
188188
189189 bool MadeChange = false;
190190
268268 INITIALIZE_PASS_END(IfConverter, "if-converter", "If Converter", false, false)
269269
270270 bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
271 TLI = MF.getTarget().getSubtargetImpl()->getTargetLowering();
272 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
273 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
271 TLI = MF.getSubtarget().getTargetLowering();
272 TII = MF.getSubtarget().getInstrInfo();
273 TRI = MF.getSubtarget().getRegisterInfo();
274274 MBPI = &getAnalysis();
275275 MRI = &MF.getRegInfo();
276276
286286 if (!PreRegAlloc) {
287287 // Tail merge tend to expose more if-conversion opportunities.
288288 BranchFolder BF(true, false);
289 BFChange = BF.OptimizeFunction(
290 MF, TII, MF.getTarget().getSubtargetImpl()->getRegisterInfo(),
291 getAnalysisIfAvailable());
289 BFChange = BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
290 getAnalysisIfAvailable());
292291 }
293292
294293 DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
420419
421420 if (MadeChange && IfCvtBranchFold) {
422421 BranchFolder BF(false, false);
423 BF.OptimizeFunction(MF, TII,
424 MF.getTarget().getSubtargetImpl()->getRegisterInfo(),
422 BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
425423 getAnalysisIfAvailable());
426424 }
427425
145145 MDT(pass.getAnalysis()),
146146 Loops(pass.getAnalysis()), VRM(vrm),
147147 MFI(*mf.getFrameInfo()), MRI(mf.getRegInfo()),
148 TII(*mf.getTarget().getSubtargetImpl()->getInstrInfo()),
149 TRI(*mf.getTarget().getSubtargetImpl()->getRegisterInfo()),
148 TII(*mf.getSubtarget().getInstrInfo()),
149 TRI(*mf.getSubtarget().getRegisterInfo()),
150150 MBFI(pass.getAnalysis()) {}
151151
152152 void spill(LiveRangeEdit &) override;
698698 MF = &mf;
699699 LIS = &pass.getAnalysis();
700700 MDT = &pass.getAnalysis();
701 TRI = mf.getTarget().getSubtargetImpl()->getRegisterInfo();
701 TRI = mf.getSubtarget().getRegisterInfo();
702702 LS.initialize(mf);
703703 DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
704704 << mf.getName() << " **********\n");
993993 DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n");
994994 if (!MF)
995995 return;
996 const TargetInstrInfo *TII =
997 MF->getTarget().getSubtargetImpl()->getInstrInfo();
996 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
998997 for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
999998 DEBUG(userValues[i]->print(dbgs(), &MF->getTarget()));
1000999 userValues[i]->rewriteLocations(*VRM, *TRI);
4747 }
4848
4949 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
50 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
50 TRI = MF.getSubtarget().getRegisterInfo();
5151 MRI = &MF.getRegInfo();
5252 LIS = &getAnalysis();
5353 VRM = &getAnalysis();
4949 }
5050
5151 bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
52 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
52 TRI = MF.getSubtarget().getRegisterInfo();
5353 // FIXME: No analysis is being done right now. We are relying on the
5454 // register allocators to provide the information.
5555 return false;
499499 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
500500 MF = &mf;
501501 MRI = &mf.getRegInfo();
502 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
502 TRI = MF->getSubtarget().getRegisterInfo();
503503
504504 unsigned NumRegs = TRI->getNumRegs();
505505 PhysRegDef = new MachineInstr*[NumRegs];
102102
103103 bool LocalStackSlotPass::runOnMachineFunction(MachineFunction &MF) {
104104 MachineFrameInfo *MFI = MF.getFrameInfo();
105 const TargetRegisterInfo *TRI =
106 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
105 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
107106 unsigned LocalObjectCount = MFI->getObjectIndexEnd();
108107
109108 // If the target doesn't want/need this pass, or if there are no locals
184183 void LocalStackSlotPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
185184 // Loop over all of the stack objects, assigning sequential addresses...
186185 MachineFrameInfo *MFI = Fn.getFrameInfo();
187 const TargetFrameLowering &TFI =
188 *Fn.getTarget().getSubtargetImpl()->getFrameLowering();
186 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
189187 bool StackGrowsDown =
190188 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
191189 int64_t Offset = 0;
274272 bool UsedBaseReg = false;
275273
276274 MachineFrameInfo *MFI = Fn.getFrameInfo();
277 const TargetRegisterInfo *TRI =
278 Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
279 const TargetFrameLowering &TFI =
280 *Fn.getTarget().getSubtargetImpl()->getFrameLowering();
275 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
276 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
281277 bool StackGrowsDown =
282278 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
283279
291291
292292 OS << '\n';
293293
294 const TargetRegisterInfo *TRI =
295 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
294 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
296295 if (!livein_empty()) {
297296 if (Indexes) OS << '\t';
298297 OS << " Live Ins:";
361360 bool LiveIn = isLiveIn(PhysReg);
362361 iterator I = SkipPHIsAndLabels(begin()), E = end();
363362 MachineRegisterInfo &MRI = getParent()->getRegInfo();
364 const TargetInstrInfo &TII =
365 *getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
363 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
366364
367365 // Look for an existing copy.
368366 if (LiveIn)
393391 }
394392
395393 void MachineBasicBlock::updateTerminator() {
396 const TargetInstrInfo *TII =
397 getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
394 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
398395 // A block with no successors has no concerns with fall-through edges.
399396 if (this->succ_empty()) return;
400397
649646 // Analyze the branches, if any, at the end of the block.
650647 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
651648 SmallVector Cond;
652 const TargetInstrInfo *TII =
653 getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
649 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
654650 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
655651 // If we couldn't analyze the branch, examine the last instruction.
656652 // If the block doesn't end in a known control barrier, assume fallthrough
695691
696692 // We may need to update this's terminator, but we can't do that if
697693 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
698 const TargetInstrInfo *TII =
699 MF->getTarget().getSubtargetImpl()->getInstrInfo();
694 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
700695 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
701696 SmallVector Cond;
702697 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
801796 NMBB->addSuccessor(Succ);
802797 if (!NMBB->isLayoutSuccessor(Succ)) {
803798 Cond.clear();
804 MF->getTarget().getSubtargetImpl()->getInstrInfo()->InsertBranch(
805 *NMBB, Succ, nullptr, Cond, dl);
799 MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
800 dl);
806801
807802 if (Indexes) {
808803 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
830825 NMBB->addLiveIn(*I);
831826
832827 // Update LiveVariables.
833 const TargetRegisterInfo *TRI =
834 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
828 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
835829 if (LV) {
836830 // Restore kills of virtual registers that were killed by the terminators.
837831 while (!KilledRegs.empty()) {
11111111 MBPI = &getAnalysis();
11121112 MBFI = &getAnalysis();
11131113 MLI = &getAnalysis();
1114 TII = F.getTarget().getSubtargetImpl()->getInstrInfo();
1115 TLI = F.getTarget().getSubtargetImpl()->getTargetLowering();
1114 TII = F.getSubtarget().getInstrInfo();
1115 TLI = F.getSubtarget().getTargetLowering();
11161116 assert(BlockToChain.empty());
11171117
11181118 buildCFGChains(F);
663663 if (skipOptnoneFunction(*MF.getFunction()))
664664 return false;
665665
666 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
667 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
666 TII = MF.getSubtarget().getInstrInfo();
667 TRI = MF.getSubtarget().getRegisterInfo();
668668 MRI = &MF.getRegInfo();
669669 AA = &getAnalysis();
670670 DT = &getAnalysis();
335335
336336 bool Changed = false;
337337
338 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
339 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
338 TRI = MF.getSubtarget().getRegisterInfo();
339 TII = MF.getSubtarget().getInstrInfo();
340340 MRI = &MF.getRegInfo();
341341
342342 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
5353
5454 MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
5555 unsigned FunctionNum, MachineModuleInfo &mmi,
56 GCModuleInfo* gmi)
57 : Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) {
56 GCModuleInfo *gmi)
57 : Fn(F), Target(TM), STI(TM.getSubtargetImpl()), Ctx(mmi.getContext()),
58 MMI(mmi), GMI(gmi) {
5859 if (TM.getSubtargetImpl()->getRegisterInfo())
5960 RegInfo = new (Allocator) MachineRegisterInfo(TM);
6061 else
352353 // Print Constant Pool
353354 ConstantPool->print(OS);
354355
355 const TargetRegisterInfo *TRI =
356 getTarget().getSubtargetImpl()->getRegisterInfo();
356 const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
357357
358358 if (RegInfo && !RegInfo->livein_empty()) {
359359 OS << "Function Live Ins: ";
462462 /// normal 'L' label is returned.
463463 MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
464464 bool isLinkerPrivate) const {
465 const DataLayout *DL = getTarget().getSubtargetImpl()->getDataLayout();
465 const DataLayout *DL = getSubtarget().getDataLayout();
466466 assert(JumpTableInfo && "No jump tables");
467467 assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
468468
477477 /// getPICBaseSymbol - Return a function-local symbol to represent the PIC
478478 /// base.
479479 MCSymbol *MachineFunction::getPICBaseSymbol() const {
480 const DataLayout *DL = getTarget().getSubtargetImpl()->getDataLayout();
480 const DataLayout *DL = getSubtarget().getDataLayout();
481481 return Ctx.GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+
482482 Twine(getFunctionNumber())+"$pb");
483483 }
628628 }
629629
630630 unsigned MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
631 const TargetFrameLowering *TFI =
632 MF.getTarget().getSubtargetImpl()->getFrameLowering();
633 const TargetRegisterInfo *RegInfo =
634 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
631 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
632 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
635633 unsigned MaxAlign = getMaxAlignment();
636634 int Offset = 0;
637635
681679 void MachineFrameInfo::print(const MachineFunction &MF, raw_ostream &OS) const{
682680 if (Objects.empty()) return;
683681
684 const TargetFrameLowering *FI =
685 MF.getTarget().getSubtargetImpl()->getFrameLowering();
682 const TargetFrameLowering *FI = MF.getSubtarget().getFrameLowering();
686683 int ValOffset = (FI ? FI->getOffsetOfLocalArea() : 0);
687684
688685 OS << "Frame Objects:\n";
3939 MachineSSAUpdater::MachineSSAUpdater(MachineFunction &MF,
4040 SmallVectorImpl *NewPHI)
4141 : AV(nullptr), InsertedPHIs(NewPHI) {
42 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
42 TII = MF.getSubtarget().getInstrInfo();
4343 MRI = &MF.getRegInfo();
4444 }
4545
377377
378378 /// Main driver for both MachineScheduler and PostMachineScheduler.
379379 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
380 const TargetInstrInfo *TII =
381 MF->getTarget().getSubtargetImpl()->getInstrInfo();
380 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
382381 bool IsPostRA = Scheduler.isPostRA();
383382
384383 // Visit all machine basic blocks.
5151
5252 bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
5353 MF = &Func;
54 TII = MF->getTarget().getSubtargetImpl()->getInstrInfo();
55 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
54 TII = MF->getSubtarget().getInstrInfo();
55 TRI = MF->getSubtarget().getRegisterInfo();
5656 MRI = &MF->getRegInfo();
5757 Loops = &getAnalysis();
5858 const TargetSubtargetInfo &ST =
6666 return false;
6767
6868 MRI = &Fn.getRegInfo();
69 TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo();
69 TII = Fn.getSubtarget().getInstrInfo();
7070
7171 // Find dead PHI cycles and PHI cycles that can be replaced by a single
7272 // value. InstCombine does these optimizations, but DAG legalization may
240240 // Insert a register to register copy at the top of the current block (but
241241 // after any remaining phi nodes) which copies the new incoming register
242242 // into the phi node destination.
243 const TargetInstrInfo *TII =
244 MF.getTarget().getSubtargetImpl()->getInstrInfo();
243 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
245244 if (isSourceDefinedByImplicitDef(MPhi, MRI))
246245 // If all sources of a PHI node are implicit_def, just emit an
247246 // implicit_def instead of a copy.
266266 if (skipOptnoneFunction(*Fn.getFunction()))
267267 return false;
268268
269 TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo();
269 TII = Fn.getSubtarget().getInstrInfo();
270270 MachineLoopInfo &MLI = getAnalysis();
271271 MachineDominatorTree &MDT = getAnalysis();
272272 AliasAnalysis *AA = &getAnalysis();
138138
139139 bool Changed = false;
140140
141 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
142 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
141 TII = MF.getSubtarget().getInstrInfo();
142 TRI = MF.getSubtarget().getRegisterInfo();
143143 MRI = &MF.getRegInfo();
144144 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
145145 assert(WorkList.empty() && "Inconsistent worklist state");
110110 ///
111111 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
112112 const Function* F = Fn.getFunction();
113 const TargetRegisterInfo *TRI =
114 Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
115 const TargetFrameLowering *TFI =
116 Fn.getTarget().getSubtargetImpl()->getFrameLowering();
113 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
114 const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
117115
118116 assert(!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs");
119117
187185 /// variables for the function's frame information and eliminate call frame
188186 /// pseudo instructions.
189187 void PEI::calculateCallsInformation(MachineFunction &Fn) {
190 const TargetInstrInfo &TII =
191 *Fn.getTarget().getSubtargetImpl()->getInstrInfo();
192 const TargetFrameLowering *TFI =
193 Fn.getTarget().getSubtargetImpl()->getFrameLowering();
188 const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
189 const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
194190 MachineFrameInfo *MFI = Fn.getFrameInfo();
195191
196192 unsigned MaxCallFrameSize = 0;
243239 /// calculateCalleeSavedRegisters - Scan the function for modified callee saved
244240 /// registers.
245241 void PEI::calculateCalleeSavedRegisters(MachineFunction &F) {
246 const TargetRegisterInfo *RegInfo =
247 F.getTarget().getSubtargetImpl()->getRegisterInfo();
248 const TargetFrameLowering *TFI =
249 F.getTarget().getSubtargetImpl()->getFrameLowering();
242 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
243 const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
250244 MachineFrameInfo *MFI = F.getFrameInfo();
251245
252246 // Get the callee saved register list...
343337 if (CSI.empty())
344338 return;
345339
346 const TargetInstrInfo &TII =
347 *Fn.getTarget().getSubtargetImpl()->getInstrInfo();
348 const TargetFrameLowering *TFI =
349 Fn.getTarget().getSubtargetImpl()->getFrameLowering();
350 const TargetRegisterInfo *TRI =
351 Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
340 const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
341 const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
342 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
352343 MachineBasicBlock::iterator I;
353344
354345 // Spill using target interface.
454445 /// abstract stack objects.
455446 ///
456447 void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
457 const TargetFrameLowering &TFI =
458 *Fn.getTarget().getSubtargetImpl()->getFrameLowering();
448 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
459449 StackProtector *SP = &getAnalysis();
460450
461451 bool StackGrowsDown =
525515 // Make sure the special register scavenging spill slot is closest to the
526516 // incoming stack pointer if a frame pointer is required and is closer
527517 // to the incoming rather than the final stack pointer.
528 const TargetRegisterInfo *RegInfo =
529 Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
518 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
530519 bool EarlyScavengingSlots = (TFI.hasFP(Fn) &&
531520 TFI.isFPCloseToIncomingSP() &&
532521 RegInfo->useFPForScavengingIndex(Fn) &&
681670 /// prolog and epilog code to the function.
682671 ///
683672 void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
684 const TargetFrameLowering &TFI =
685 *Fn.getTarget().getSubtargetImpl()->getFrameLowering();
673 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
686674
687675 // Add prologue to the function...
688676 TFI.emitPrologue(Fn);
753741 const TargetMachine &TM = Fn.getTarget();
754742 assert(TM.getSubtargetImpl()->getRegisterInfo() &&
755743 "TM::getRegisterInfo() must be implemented!");
756 const TargetInstrInfo &TII =
757 *Fn.getTarget().getSubtargetImpl()->getInstrInfo();
744 const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
758745 const TargetRegisterInfo &TRI = *TM.getSubtargetImpl()->getRegisterInfo();
759746 const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
760747 bool StackGrowsDown =
188188
189189 LiveIntervals *LIS = const_cast(lis);
190190 MachineRegisterInfo *mri = &mf->getRegInfo();
191 const TargetRegisterInfo *tri =
192 mf->getTarget().getSubtargetImpl()->getRegisterInfo();
191 const TargetRegisterInfo *tri = mf->getSubtarget().getRegisterInfo();
193192
194193 std::unique_ptr p(new PBQPRAProblem());
195194 PBQPRAGraph &g = p->getGraph();
3737 MF = &mf;
3838
3939 // Allocate new array the first time we see a new target.
40 if (MF->getTarget().getSubtargetImpl()->getRegisterInfo() != TRI) {
41 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
40 if (MF->getSubtarget().getRegisterInfo() != TRI) {
41 TRI = MF->getSubtarget().getRegisterInfo();
4242 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
4343 unsigned NumPSets = TRI->getNumRegPressureSets();
4444 PSetLimits.reset(new unsigned[NumPSets]);
184184 reset();
185185
186186 MF = mf;
187 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
187 TRI = MF->getSubtarget().getRegisterInfo();
188188 RCI = rci;
189189 MRI = &MF->getRegInfo();
190190 MBB = mbb;
209209 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
210210 EVT VT = ValueVTs[vti];
211211 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
212 const TargetInstrInfo *TII =
213 MF->getTarget().getSubtargetImpl()->getInstrInfo();
212 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
214213 for (unsigned i = 0; i != NumRegisters; ++i)
215214 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
216215 PHIReg += NumRegisters;
4747
4848 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
4949 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
50 InstrItins(mf.getTarget().getSubtargetImpl()->getInstrItineraryData()) {}
50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
5151
5252 /// Run - perform scheduling.
5353 ///
39463946
39473947 // Don't promote to an alignment that would require dynamic stack
39483948 // realignment.
3949 const TargetRegisterInfo *TRI =
3950 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
3949 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
39513950 if (!TRI->needsStackRealignment(MF))
39523951 while (NewAlign > Align &&
39533952 TLI.getDataLayout()->exceedsNaturalStackAlignment(NewAlign))
860860 AA = &aa;
861861 GFI = gfi;
862862 LibInfo = li;
863 DL = DAG.getTarget().getSubtargetImpl()->getDataLayout();
863 DL = DAG.getSubtarget().getDataLayout();
864864 Context = DAG.getContext();
865865 LPadToCallSiteMap.clear();
866866 }
46004600 return false;
46014601
46024602 MachineFunction &MF = DAG.getMachineFunction();
4603 const TargetInstrInfo *TII =
4604 DAG.getTarget().getSubtargetImpl()->getInstrInfo();
4603 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
46054604
46064605 // Ignore inlined function arguments here.
46074606 DIVariable DV(Variable);
3636 return "<>";
3737 if (isMachineOpcode()) {
3838 if (G)
39 if (const TargetInstrInfo *TII =
40 G->getTarget().getSubtargetImpl()->getInstrInfo())
39 if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
4140 if (getMachineOpcode() < TII->getNumOpcodes())
4241 return TII->getName(getMachineOpcode());
4342 return "<>";
434433 OS << LBB->getName() << " ";
435434 OS << (const void*)BBDN->getBasicBlock() << ">";
436435 } else if (const RegisterSDNode *R = dyn_cast(this)) {
437 OS << ' '
438 << PrintReg(R->getReg(),
439 G ? G->getTarget().getSubtargetImpl()->getRegisterInfo()
440 : nullptr);
436 OS << ' ' << PrintReg(R->getReg(),
437 G ? G->getSubtarget().getRegisterInfo() : nullptr);
441438 } else if (const ExternalSymbolSDNode *ES =
442439 dyn_cast(this)) {
443440 OS << "'" << ES->getSymbol() << "'";
6464 lis = &pass.getAnalysis();
6565 mfi = mf.getFrameInfo();
6666 mri = &mf.getRegInfo();
67 tii = mf.getTarget().getSubtargetImpl()->getInstrInfo();
68 tri = mf.getTarget().getSubtargetImpl()->getRegisterInfo();
67 tii = mf.getSubtarget().getInstrInfo();
68 tri = mf.getSubtarget().getRegisterInfo();
6969 }
7070
7171 /// Add spill ranges for every use/def of the live interval, inserting loads
4242 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
4343 const MachineLoopInfo &mli)
4444 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
45 TII(*MF.getTarget().getSubtargetImpl()->getInstrInfo()), CurLI(nullptr),
45 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
4646 LastSplitPoint(MF.getNumBlockIDs()) {}
4747
4848 void SplitAnalysis::clear() {
6666 DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: "
6767 << _MF.getName() << " **********\n");
6868 MF = &_MF;
69 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
69 TRI = MF->getSubtarget().getRegisterInfo();
7070 ++NumStackMapFuncVisited;
7171
7272 // Skip this function if there are no patchpoints to process.
238238
239239 // Record the stack size of the current function.
240240 const MachineFrameInfo *MFI = AP.MF->getFrameInfo();
241 const TargetRegisterInfo *RegInfo =
242 AP.MF->getTarget().getSubtargetImpl()->getRegisterInfo();
241 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
243242 const bool DynamicFrameSize = MFI->hasVarSizedObjects() ||
244243 RegInfo->needsStackRealignment(*(AP.MF));
245244 FnStackSize[AP.CurrentFnSym] =
422422 });
423423
424424 MFI = MF.getFrameInfo();
425 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
425 TII = MF.getSubtarget().getInstrInfo();
426426 LS = &getAnalysis();
427427 MBFI = &getAnalysis();
428428
135135 if (skipOptnoneFunction(*MF.getFunction()))
136136 return false;
137137
138 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
139 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
138 TII = MF.getSubtarget().getInstrInfo();
139 TRI = MF.getSubtarget().getRegisterInfo();
140140 MRI = &MF.getRegInfo();
141141 MMI = getAnalysisIfAvailable();
142142 MBPI = &getAnalysis();
3434
3535 int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF,
3636 int FI, unsigned &FrameReg) const {
37 const TargetRegisterInfo *RI =
38 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
37 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
3938
4039 // By default, assume all frame indices are referenced via whatever
4140 // getFrameRegister() says. The target can override this if it's doing
499499
500500 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
501501 MachineBasicBlock::iterator Pos = MI;
502 const TargetRegisterInfo *TRI =
503 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
502 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
504503
505504 if (Flags == MachineMemOperand::MOStore)
506505 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
655654 // saves compile time, because it doesn't require every single
656655 // stack slot reference to depend on the instruction that does the
657656 // modification.
658 const TargetLowering &TLI =
659 *MF.getTarget().getSubtargetImpl()->getTargetLowering();
660 const TargetRegisterInfo *TRI =
661 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
657 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
658 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
662659 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
663660 return true;
664661
289289 // for predicated defs.
290290 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
291291 const MachineFunction &MF = *DefMI->getParent()->getParent();
292 const TargetRegisterInfo *TRI =
293 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
292 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
294293 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
295294 return computeInstrLatency(DefMI);
296295
5454
5555 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
5656 MRI = &mf.getRegInfo();
57 TII = mf.getTarget().getSubtargetImpl()->getInstrInfo();
58 TRI = mf.getTarget().getSubtargetImpl()->getRegisterInfo();
57 TII = mf.getSubtarget().getInstrInfo();
58 TRI = mf.getSubtarget().getRegisterInfo();
5959 MF = &mf;
6060
6161 Virt2PhysMap.clear();
190190 /// runOnMachineFunction - Initialize per-function data structures.
191191 void runOnMachineFunction(MachineFunction &MF) {
192192 this->MF = &MF;
193 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
194 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
193 TII = MF.getSubtarget().getInstrInfo();
194 TRI = MF.getSubtarget().getRegisterInfo();
195195 MRI = &MF.getRegInfo();
196196 }
197197
890890 bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
891891 DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
892892 << "********** Function: " << MF.getName() << '\n');
893 TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
894 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
893 TII = MF.getSubtarget().getInstrInfo();
894 TRI = MF.getSubtarget().getRegisterInfo();
895895 SchedModel =
896896 MF.getTarget().getSubtarget().getSchedModel();
897897 MRI = &MF.getRegInfo();
119119 // Scan the function for instructions that have a dead definition of a
120120 // register. Replace that register with the zero register when possible.
121121 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
122 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
122 TRI = MF.getSubtarget().getRegisterInfo();
123123 bool Changed = false;
124124 DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
125125
722722 }
723723
724724 bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
725 TII = static_cast(
726 MF.getTarget().getSubtargetImpl()->getInstrInfo());
725 TII = static_cast(MF.getSubtarget().getInstrInfo());
727726
728727 bool Modified = false;
729728 for (auto &MBB : MF)
8585 const MachineFrameInfo *MFI = MF.getFrameInfo();
8686
8787 #ifndef NDEBUG
88 const TargetRegisterInfo *RegInfo =
89 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
88 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
9089 assert(!RegInfo->needsStackRealignment(MF) &&
9190 "No stack realignment on AArch64!");
9291 #endif
108107 void AArch64FrameLowering::eliminateCallFramePseudoInstr(
109108 MachineFunction &MF, MachineBasicBlock &MBB,
110109 MachineBasicBlock::iterator I) const {
111 const AArch64InstrInfo *TII = static_cast(
112 MF.getTarget().getSubtargetImpl()->getInstrInfo());
110 const AArch64InstrInfo *TII =
111 static_cast(MF.getSubtarget().getInstrInfo());
113112 DebugLoc DL = I->getDebugLoc();
114113 int Opc = I->getOpcode();
115114 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
116115 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
117116
118 const TargetFrameLowering *TFI =
119 MF.getTarget().getSubtargetImpl()->getFrameLowering();
117 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
120118 if (!TFI->hasReservedCallFrame(MF)) {
121119 unsigned Align = getStackAlignment();
122120
159157 MachineFrameInfo *MFI = MF.getFrameInfo();
160158 MachineModuleInfo &MMI = MF.getMMI();
161159 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
162 const TargetInstrInfo *TII =
163 MF.getTarget().getSubtargetImpl()->getInstrInfo();
160 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
164161 DebugLoc DL = MBB.findDebugLoc(MBBI);
165162
166163 // Add callee saved registers to move list.
168165 if (CSI.empty())
169166 return;
170167
171 const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout();
168 const DataLayout *TD = MF.getSubtarget().getDataLayout();
172169 bool HasFP = hasFP(MF);
173170
174171 // Calculate amount of bytes used for return address storing.
207204 const MachineFrameInfo *MFI = MF.getFrameInfo();
208205 const Function *Fn = MF.getFunction();
209206 const AArch64RegisterInfo *RegInfo = static_cast(
210 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
211 const TargetInstrInfo *TII =
212 MF.getTarget().getSubtargetImpl()->getInstrInfo();
207 MF.getSubtarget().getRegisterInfo());
208 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
213209 MachineModuleInfo &MMI = MF.getMMI();
214210 AArch64FunctionInfo *AFI = MF.getInfo();
215211 bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
303299 TII->copyPhysReg(MBB, MBBI, DL, AArch64::X19, AArch64::SP, false);
304300
305301 if (needsFrameMoves) {
306 const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout();
302 const DataLayout *TD = MF.getSubtarget().getDataLayout();
307303 const int StackGrowth = -TD->getPointerSize(0);
308304 unsigned FramePtr = RegInfo->getFrameRegister(MF);
309305
437433 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
438434 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
439435 MachineFrameInfo *MFI = MF.getFrameInfo();
440 const AArch64InstrInfo *TII = static_cast(
441 MF.getTarget().getSubtargetImpl()->getInstrInfo());
436 const AArch64InstrInfo *TII =
437 static_cast(MF.getSubtarget().getInstrInfo());
442438 const AArch64RegisterInfo *RegInfo = static_cast(
443 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
439 MF.getSubtarget().getRegisterInfo());
444440 DebugLoc DL = MBBI->getDebugLoc();
445441 unsigned RetOpcode = MBBI->getOpcode();
446442
551547 bool PreferFP) const {
552548 const MachineFrameInfo *MFI = MF.getFrameInfo();
553549 const AArch64RegisterInfo *RegInfo = static_cast(
554 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
550 MF.getSubtarget().getRegisterInfo());
555551 const AArch64FunctionInfo *AFI = MF.getInfo();
556552 int FPOffset = MFI->getObjectOffset(FI) + 16;
557553 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
620616 const std::vector &CSI,
621617 const TargetRegisterInfo *TRI) const {
622618 MachineFunction &MF = *MBB.getParent();
623 const TargetInstrInfo &TII =
624 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
619 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
625620 unsigned Count = CSI.size();
626621 DebugLoc DL;
627622 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
697692 const std::vector &CSI,
698693 const TargetRegisterInfo *TRI) const {
699694 MachineFunction &MF = *MBB.getParent();
700 const TargetInstrInfo &TII =
701 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
695 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
702696 unsigned Count = CSI.size();
703697 DebugLoc DL;
704698 assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
766760 void AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(
767761 MachineFunction &MF, RegScavenger *RS) const {
768762 const AArch64RegisterInfo *RegInfo = static_cast(
769 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
763 MF.getSubtarget().getRegisterInfo());
770764 AArch64FunctionInfo *AFI = MF.getInfo();
771765 MachineRegisterInfo *MRI = &MF.getRegInfo();
772766 SmallVector UnspilledCSGPRs;
7575
7676 BitVector
7777 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
78 const TargetFrameLowering *TFI =
79 MF.getTarget().getSubtargetImpl()->getFrameLowering();
78 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
8079
8180 // FIXME: avoid re-calculating this every time.
8281 BitVector Reserved(getNumRegs());
105104
106105 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
107106 unsigned Reg) const {
108 const TargetFrameLowering *TFI =
109 MF.getTarget().getSubtargetImpl()->getFrameLowering();
107 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
110108
111109 switch (Reg) {
112110 default:
170168
171169 unsigned
172170 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
173 const TargetFrameLowering *TFI =
174 MF.getTarget().getSubtargetImpl()->getFrameLowering();
171 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
175172
176173 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
177174 }
238235 // Note that the incoming offset is based on the SP value at function entry,
239236 // so it'll be negative.
240237 MachineFunction &MF = *MI->getParent()->getParent();
241 const TargetFrameLowering *TFI =
242 MF.getTarget().getSubtargetImpl()->getFrameLowering();
238 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
243239 MachineFrameInfo *MFI = MF.getFrameInfo();
244240
245241 // Estimate an offset from the frame pointer.
329325 MachineBasicBlock &MBB = *MI.getParent();
330326 MachineFunction &MF = *MBB.getParent();
331327 const AArch64FrameLowering *TFI = static_cast(
332 MF.getTarget().getSubtargetImpl()->getFrameLowering());
328 MF.getSubtarget().getFrameLowering());
333329
334330 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
335331 unsigned FrameReg;
367363
368364 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
369365 MachineFunction &MF) const {
370 const TargetFrameLowering *TFI =
371 MF.getTarget().getSubtargetImpl()->getFrameLowering();
366 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
372367
373368 switch (RC->getID()) {
374369 default:
117117
118118 bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) {
119119 MF = &mf;
120 TII = static_cast(
121 MF->getTarget().getSubtargetImpl()->getInstrInfo());
122 TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo();
120 TII =
121 static_cast(MF->getSubtarget().getInstrInfo());
122 TRI = MF->getSubtarget().getRegisterInfo();
123123 MRI = &MF->getRegInfo();
124124 const TargetSubtargetInfo &ST =
125125 MF->getTarget().getSubtarget();
676676 }
677677
678678 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
679 TII = static_cast(
680 Fn.getTarget().getSubtargetImpl()->getInstrInfo());
681 TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
679 TII = static_cast(Fn.getSubtarget().getInstrInfo());
680 TRI = Fn.getSubtarget().getRegisterInfo();
682681 MRI = &Fn.getRegInfo();
683682 bool Modified = false;
684683
136136 assert(!MO.getSubReg() && "Subregs should be eliminated!");
137137 if(ARM::GPRPairRegClass.contains(Reg)) {
138138 const MachineFunction &MF = *MI->getParent()->getParent();
139 const TargetRegisterInfo *TRI =
140 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
139 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
141140 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
142141 }
143142 O << ARMInstPrinter::getRegisterName(Reg);
230229 case 'y': // Print a VFP single precision register as indexed double.
231230 if (MI->getOperand(OpNum).isReg()) {
232231 unsigned Reg = MI->getOperand(OpNum).getReg();
233 const TargetRegisterInfo *TRI =
234 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
232 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
235233 // Find the 'd' register that has this 's' register as a sub-register,
236234 // and determine the lane number.
237235 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
263261 // inline asm statement.
264262 O << "{";
265263 if (ARM::GPRPairRegClass.contains(RegBegin)) {
266 const TargetRegisterInfo *TRI =
267 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
264 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
268265 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
269266 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
270267 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
320317 const MachineOperand &MO = MI->getOperand(OpNum);
321318 if (!MO.isReg())
322319 return true;
323 const TargetRegisterInfo *TRI =
324 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
320 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
325321 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
326322 ARM::gsub_0 : ARM::gsub_1);
327323 O << ARMInstPrinter::getRegisterName(Reg);
347343 unsigned Reg = MI->getOperand(OpNum).getReg();
348344 if (!ARM::QPRRegClass.contains(Reg))
349345 return true;
350 const TargetRegisterInfo *TRI =
351 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
346 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
352347 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
353348 ARM::dsub_0 : ARM::dsub_1);
354349 O << ARMInstPrinter::getRegisterName(SubReg);
363358 if (!MO.isReg())
364359 return true;
365360 const MachineFunction &MF = *MI->getParent()->getParent();
366 const TargetRegisterInfo *TRI =
367 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
361 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
368362 unsigned Reg = MO.getReg();
369363 if(!ARM::GPRPairRegClass.contains(Reg))
370364 return false;
10341028 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
10351029 ARMTargetStreamer &ATS = static_cast(TS);
10361030 const MachineFunction &MF = *MI->getParent()->getParent();
1037 const TargetRegisterInfo *RegInfo =
1038 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
1031 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
10391032 const ARMFunctionInfo &AFI = *MF.getInfo();
10401033
10411034 unsigned FramePtr = RegInfo->getFrameRegister(MF);
122122
123123 BitVector ARMBaseRegisterInfo::
124124 getReservedRegs(const MachineFunction &MF) const {
125 const TargetFrameLowering *TFI =
126 MF.getTarget().getSubtargetImpl()->getFrameLowering();
125 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
127126
128127 // FIXME: avoid re-calculating this every time.
129128 BitVector Reserved(getNumRegs());
189188 unsigned
190189 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
191190 MachineFunction &MF) const {
192 const TargetFrameLowering *TFI =
193 MF.getTarget().getSubtargetImpl()->getFrameLowering();
191 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
194192
195193 switch (RC->getID()) {
196194 default:
312310 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
313311 const MachineFrameInfo *MFI = MF.getFrameInfo();
314312 const ARMFunctionInfo *AFI = MF.getInfo();
315 const TargetFrameLowering *TFI =
316 MF.getTarget().getSubtargetImpl()->getFrameLowering();
313 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
317314
318315 // When outgoing call frames are so large that we adjust the stack pointer
319316 // around the call, we can no longer use the stack pointer to reach the
395392
396393 unsigned
397394 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
398 const TargetFrameLowering *TFI =
399 MF.getTarget().getSubtargetImpl()->getFrameLowering();
395 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
400396
401397 if (TFI->hasFP(MF))
402398 return FramePtr;
413409 ARMCC::CondCodes Pred,
414410 unsigned PredReg, unsigned MIFlags) const {
415411 MachineFunction &MF = *MBB.getParent();
416 const TargetInstrInfo &TII =
417 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
412 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
418413 MachineConstantPool *ConstantPool = MF.getConstantPool();
419414 const Constant *C =
420415 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
541536 // Note that the incoming offset is based on the SP value at function entry,
542537 // so it'll be negative.
543538 MachineFunction &MF = *MI->getParent()->getParent();
544 const TargetFrameLowering *TFI =
545 MF.getTarget().getSubtargetImpl()->getFrameLowering();
539 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
546540 MachineFrameInfo *MFI = MF.getFrameInfo();
547541 ARMFunctionInfo *AFI = MF.getInfo();
548542
604598
605599 const MachineFunction &MF = *MBB->getParent();
606600 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
607 const TargetInstrInfo &TII =
608 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
601 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
609602 const MCInstrDesc &MCID = TII.get(ADDriOpc);
610603 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
611604
621614 MachineBasicBlock &MBB = *MI.getParent();
622615 MachineFunction &MF = *MBB.getParent();
623616 const ARMBaseInstrInfo &TII =
624 *static_cast(
625 MF.getTarget().getSubtargetImpl()->getInstrInfo());
617 *static_cast(MF.getSubtarget().getInstrInfo());
626618 ARMFunctionInfo *AFI = MF.getInfo();
627619 int Off = Offset; // ARM doesn't need the general 64-bit offsets
628620 unsigned i = 0;
721713 MachineBasicBlock &MBB = *MI.getParent();
722714 MachineFunction &MF = *MBB.getParent();
723715 const ARMBaseInstrInfo &TII =
724 *static_cast(
725 MF.getTarget().getSubtargetImpl()->getInstrInfo());
716 *static_cast(MF.getSubtarget().getInstrInfo());
726717 const ARMFrameLowering *TFI = static_cast(
727 MF.getTarget().getSubtargetImpl()->getFrameLowering());
718 MF.getSubtarget().getFrameLowering());
728719 ARMFunctionInfo *AFI = MF.getInfo();
729720 assert(!AFI->isThumb1OnlyFunction() &&
730721 "This eliminateFrameIndex does not support Thumb1!");
530530 // identity mapping of CPI's to CPE's.
531531 const std::vector &CPs = MCP->getConstants();
532532
533 const DataLayout &TD = *MF->getTarget().getSubtargetImpl()->getDataLayout();
533 const DataLayout &TD = *MF->getSubtarget().getDataLayout();
534534 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
535535 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
536536 assert(Size >= 4 && "Too small constant pool entry");
866866 if (RI.hasBasePointer(MF)) {
867867 int32_t NumBytes = AFI->getFramePtrSpillOffset();
868868 unsigned FramePtr = RI.getFrameRegister(MF);
869 assert(
870 MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF) &&
871 "base pointer without frame pointer?");
869 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
870 "base pointer without frame pointer?");
872871
873872 if (AFI->isThumb2Function()) {
874873 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
4646 /// pointer register. This is true if the function has variable sized allocas
4747 /// or if frame pointer elimination is disabled.
4848 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
49 const TargetRegisterInfo *RegInfo =
50 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
49 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
5150
5251 // iOS requires FP not to be clobbered for backtracing purpose.
5352 if (STI.isTargetIOS())
575574 DebugLoc dl = MBBI->getDebugLoc();
576575 MachineFrameInfo *MFI = MF.getFrameInfo();
577576 ARMFunctionInfo *AFI = MF.getInfo();
578 const TargetRegisterInfo *RegInfo =
579 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
577 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
580578 const ARMBaseInstrInfo &TII =
581 *static_cast(
582 MF.getTarget().getSubtargetImpl()->getInstrInfo());
579 *static_cast(MF.getSubtarget().getInstrInfo());
583580 assert(!AFI->isThumb1OnlyFunction() &&
584581 "This emitEpilogue does not support Thumb1!");
585582 bool isARM = !AFI->isThumbFunction();
724721 int SPAdj) const {
725722 const MachineFrameInfo *MFI = MF.getFrameInfo();
726723 const ARMBaseRegisterInfo *RegInfo = static_cast(
727 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
724 MF.getSubtarget().getRegisterInfo());
728725 const ARMFunctionInfo *AFI = MF.getInfo();
729726 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
730727 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
809806 unsigned NumAlignedDPRCS2Regs,
810807 unsigned MIFlags) const {
811808 MachineFunction &MF = *MBB.getParent();
812 const TargetInstrInfo &TII =
813 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
809 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
814810
815811 DebugLoc DL;
816812 if (MI != MBB.end()) DL = MI->getDebugLoc();
883879 bool(*Func)(unsigned, bool),
884880 unsigned NumAlignedDPRCS2Regs) const {
885881 MachineFunction &MF = *MBB.getParent();
886 const TargetInstrInfo &TII =
887 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
882 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
888883 ARMFunctionInfo *AFI = MF.getInfo();
889884 DebugLoc DL = MI->getDebugLoc();
890885 unsigned RetOpcode = MI->getOpcode();
974969 MachineFunction &MF = *MBB.getParent();
975970 ARMFunctionInfo *AFI = MF.getInfo();
976971 DebugLoc DL = MI->getDebugLoc();
977 const TargetInstrInfo &TII =
978 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
972 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
979973 MachineFrameInfo &MFI = *MF.getFrameInfo();
980974
981975 // Mark the D-register spill slots as properly aligned. Since MFI computes
11341128 MachineFunction &MF = *MBB.getParent();
11351129 ARMFunctionInfo *AFI = MF.getInfo();
11361130 DebugLoc DL = MI->getDebugLoc();
1137 const TargetInstrInfo &TII =
1138 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1131 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
11391132
11401133 // Find the frame index assigned to d8.
11411134 int D8SpillFI = 0;
13581351
13591352 // Aligned spills require stack realignment.
13601353 const ARMBaseRegisterInfo *RegInfo = static_cast(
1361 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1354 MF.getSubtarget().getRegisterInfo());
13621355 if (!RegInfo->canRealignStack(MF))
13631356 return;
13641357
13981391 SmallVector UnspilledCS1GPRs;
13991392 SmallVector UnspilledCS2GPRs;
14001393 const ARMBaseRegisterInfo *RegInfo = static_cast(
1401 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1394 MF.getSubtarget().getRegisterInfo());
14021395 const ARMBaseInstrInfo &TII =
1403 *static_cast(
1404 MF.getTarget().getSubtargetImpl()->getInstrInfo());
1396 *static_cast(MF.getSubtarget().getInstrInfo());
14051397 ARMFunctionInfo *AFI = MF.getInfo();
14061398 MachineFrameInfo *MFI = MF.getFrameInfo();
14071399 MachineRegisterInfo &MRI = MF.getRegInfo();
16421634 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
16431635 MachineBasicBlock::iterator I) const {
16441636 const ARMBaseInstrInfo &TII =
1645 *static_cast(
1646 MF.getTarget().getSubtargetImpl()->getInstrInfo());
1637 *static_cast(MF.getSubtarget().getInstrInfo());
16471638 if (!hasReservedCallFrame(MF)) {
16481639 // If we have alloca, convert as follows:
16491640 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
17611752 MCContext &Context = MMI.getContext();
17621753 const MCRegisterInfo *MRI = Context.getRegisterInfo();
17631754 const ARMBaseInstrInfo &TII =
1764 *static_cast(
1765 MF.getTarget().getSubtargetImpl()->getInstrInfo());
1755 *static_cast(MF.getSubtarget().getInstrInfo());
17661756 ARMFunctionInfo *ARMFI = MF.getInfo();
17671757 DebugLoc DL;
17681758
424424 return true;
425425 if (Use->isMachineOpcode()) {
426426 const ARMBaseInstrInfo *TII = static_cast(
427 CurDAG->getTarget().getSubtargetImpl()->getInstrInfo());
427 CurDAG->getSubtarget().getInstrInfo());
428428
429429 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
430430 if (MCID.mayStore())
17921792 }
17931793
17941794 bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
1795 TD = Fn.getTarget().getSubtargetImpl()->getDataLayout();
1796 TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo();
1797 TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
1795 TD = Fn.getSubtarget().getDataLayout();
1796 TII = Fn.getSubtarget().getInstrInfo();
1797 TRI = Fn.getSubtarget().getRegisterInfo();
17981798 STI = &Fn.getTarget().getSubtarget();
17991799 MRI = &Fn.getRegInfo();
18001800 MF = &Fn;
377377 }
378378
379379 bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) {
380 TII = static_cast(
381 Fn.getTarget().getSubtargetImpl()->getInstrInfo());
382 TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
380 TII = static_cast(Fn.getSubtarget().getInstrInfo());
381 TRI = Fn.getSubtarget().getRegisterInfo();
383382 MRI = &Fn.getRegInfo();
384383 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget();
385384 isLikeA9 = STI->isLikeA9() || STI->isSwift();
5151 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
5252 MachineBasicBlock::iterator I) const {
5353 const Thumb1InstrInfo &TII =
54 *static_cast(
55 MF.getTarget().getSubtargetImpl()->getInstrInfo());
54 *static_cast(MF.getSubtarget().getInstrInfo());
5655 const Thumb1RegisterInfo *RegInfo = static_cast(
57 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
56 MF.getSubtarget().getRegisterInfo());
5857 if (!hasReservedCallFrame(MF)) {
5958 // If we have alloca, convert as follows:
6059 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
9089 MachineModuleInfo &MMI = MF.getMMI();
9190 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
9291 const Thumb1RegisterInfo *RegInfo = static_cast(
93 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
92 MF.getSubtarget().getRegisterInfo());
9493 const Thumb1InstrInfo &TII =
95 *static_cast(
96 MF.getTarget().getSubtargetImpl()->getInstrInfo());
94 *static_cast(MF.getSubtarget().getInstrInfo());
9795
9896 unsigned Align = MF.getTarget()
9997 .getSubtargetImpl()
326324 MachineFrameInfo *MFI = MF.getFrameInfo();
327325 ARMFunctionInfo *AFI = MF.getInfo();
328326 const Thumb1RegisterInfo *RegInfo = static_cast(
329 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
327 MF.getSubtarget().getRegisterInfo());
330328 const Thumb1InstrInfo &TII =
331 *static_cast(
332 MF.getTarget().getSubtargetImpl()->getInstrInfo());
329 *static_cast(MF.getSubtarget().getInstrInfo());
333330
334331 unsigned Align = MF.getTarget()
335332 .getSubtargetImpl()
425422
426423 DebugLoc DL;
427424 MachineFunction &MF = *MBB.getParent();
428 const TargetInstrInfo &TII =
429 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
425 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
430426
431427 if (MI != MBB.end()) DL = MI->getDebugLoc();
432428
465461
466462 MachineFunction &MF = *MBB.getParent();
467463 ARMFunctionInfo *AFI = MF.getInfo();
468 const TargetInstrInfo &TII =
469 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
464 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
470465
471466 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
472467 DebugLoc DL = MI->getDebugLoc();
6666 ARMCC::CondCodes Pred, unsigned PredReg,
6767 unsigned MIFlags) const {
6868 MachineFunction &MF = *MBB.getParent();
69 const TargetInstrInfo &TII =
70 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
69 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
7170 MachineConstantPool *ConstantPool = MF.getConstantPool();
7271 const Constant *C = ConstantInt::get(
7372 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
515514 // off the frame pointer (if, for example, there are alloca() calls in
516515 // the function, the offset will be negative. Use R12 instead since that's
517516 // a call clobbered register that we know won't be used in Thumb1 mode.
518 const TargetInstrInfo &TII =
519 *MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
517 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
520518 DebugLoc DL;
521519 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
522520 .addReg(ARM::R12, RegState::Define)
563561 MachineBasicBlock &MBB = *MI.getParent();
564562 MachineFunction &MF = *MBB.getParent();
565563 const ARMBaseInstrInfo &TII =
566 *static_cast(
567 MF.getTarget().getSubtargetImpl()->getInstrInfo());
564 *static_cast(MF.getSubtarget().getInstrInfo());
568565 ARMFunctionInfo *AFI = MF.getInfo();
569566 DebugLoc dl = MI.getDebugLoc();
570567 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
575572 MF.getFrameInfo()->getStackSize() + SPAdj;
576573
577574 if (MF.getFrameInfo()->hasVarSizedObjects()) {
578 assert(SPAdj == 0 &&
579 MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF) &&
575 assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
580576 "Unexpected");
581577 // There are alloca()'s in this function, must reference off the frame
582578 // pointer or base pointer instead.
3939 ARMCC::CondCodes Pred, unsigned PredReg,
4040 unsigned MIFlags) const {
4141 MachineFunction &MF = *MBB.getParent();
42 const TargetInstrInfo &TII =
43 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
42 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
4443 MachineConstantPool *ConstantPool = MF.getConstantPool();
4544 const Constant *C = ConstantInt::get(
4645 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
416416 bool HasChanged = false;
417417
418418 // Get target info.
419 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
420 TII = static_cast(
421 MF.getTarget().getSubtargetImpl()->getInstrInfo());
419 TRI = MF.getSubtarget().getRegisterInfo();
420 TII = static_cast(MF.getSubtarget().getInstrInfo());
422421
423422 // Combine aggressively (for code size)
424423 ShouldCombineAggressively =
159159 void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
160160 MachineBasicBlock::iterator &MII,
161161 RegScavenger &RS) {
162 const TargetInstrInfo *TII =
163 MF.getTarget().getSubtargetImpl()->getInstrInfo();
162 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
164163 MachineBasicBlock *MBB = MII->getParent();
165164 DebugLoc DL = MII->getDebugLoc();
166165 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
8080 MachineFrameInfo *MFI = MF.getFrameInfo();
8181 MachineBasicBlock::iterator MBBI = MBB.begin();
8282 const HexagonRegisterInfo *QRI = static_cast(
83 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
83 MF.getSubtarget().getRegisterInfo());
8484 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
8585 determineFrameLayout(MF);
8686
117117 // Check for overflow.
118118 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
119119 const int ALLOCFRAME_MAX = 16384;
120 const TargetInstrInfo &TII =
121 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
120 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
122121
123122 if (NumBytes >= ALLOCFRAME_MAX) {
124123 // Emit allocframe(#0).
157156 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
158157 MachineBasicBlock::iterator MBBI_end = MBB.end();
159158
160 const TargetInstrInfo &TII =
161 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
159 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
162160 // Handle EH_RETURN.
163161 if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
164162 assert(MBBI->getOperand(0).isReg() && "Offset should be in register!");
229227 const std::vector &CSI,
230228 const TargetRegisterInfo *TRI) const {
231229 MachineFunction *MF = MBB.getParent();
232 const TargetInstrInfo &TII =
233 *MF->getTarget().getSubtargetImpl()->getInstrInfo();
230 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
234231
235232 if (CSI.empty()) {
236233 return false;
285282 const TargetRegisterInfo *TRI) const {
286283
287284 MachineFunction *MF = MBB.getParent();
288 const TargetInstrInfo &TII =
289 *MF->getTarget().getSubtargetImpl()->getInstrInfo();
285 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
290286
291287 if (CSI.empty()) {
292288 return false;
463463 SmallVector MemOpChains;
464464
465465 const HexagonRegisterInfo *QRI = static_cast(
466 DAG.getTarget().getSubtargetImpl()->getRegisterInfo());
466 DAG.getSubtarget().getRegisterInfo());
467467 SDValue StackPtr =
468468 DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy());
469469
722722 // Check it to be lr
723723 const HexagonRegisterInfo *QRI =
724724 static_cast(
725 DAG.getTarget().getSubtargetImpl()->getRegisterInfo());
725 DAG.getSubtarget().getRegisterInfo());
726726 if (Reg == QRI->getRARegister()) {
727727 FuncInfo->setHasClobberLR(true);
728728 break;
816816 // The Sub result contains the new stack start address, so it
817817 // must be placed in the stack pointer register.
818818 const HexagonRegisterInfo *QRI = static_cast(
819 DAG.getTarget().getSubtargetImpl()->getRegisterInfo());
819 DAG.getSubtarget().getRegisterInfo());
820820 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub);
821821
822822 SDValue Ops[2] = { ArgAdjust, CopyChain };
963963
964964 SDValue
965965 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
966 const TargetRegisterInfo *TRI =
967 DAG.getTarget().getSubtargetImpl()->getRegisterInfo();
966 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
968967 MachineFunction &MF = DAG.getMachineFunction();
969968 MachineFrameInfo *MFI = MF.getFrameInfo();
970969 MFI->setReturnAddressIsTaken(true);
991990 SDValue
992991 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
993992 const HexagonRegisterInfo *TRI = static_cast(
994 DAG.getTarget().getSubtargetImpl()->getRegisterInfo());
993 DAG.getSubtarget().getRegisterInfo());
995994 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
996995 MFI->setFrameAddressIsTaken(true);
997996
361361 LiveVariables &LVs = getAnalysis();
362362 #endif
363363
364 QII = static_cast(
365 MF.getTarget().getSubtargetImpl()->getInstrInfo());
364 QII = static_cast(MF.getSubtarget().getInstrInfo());
366365 QRI = static_cast(
367 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
366 MF.getSubtarget().getRegisterInfo());
368367 MBPI = &getAnalysis();
369368
370369 if (!QRI->Subtarget.hasV4TOps() ||
110110 false, false)
111111
112112 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
113 QII = static_cast(
114 MF.getTarget().getSubtargetImpl()->getInstrInfo());
113 QII = static_cast(MF.getSubtarget().getInstrInfo());
115114 QRI = MF.getTarget().getSubtarget().getRegisterInfo();
116115 MRI = &MF.getRegInfo();
117116
127127 // Addressable stack objects are accessed using neg. offsets from %fp.
128128 MachineFunction &MF = *MI.getParent()->getParent();
129129 const HexagonInstrInfo &TII =
130 *static_cast(
131 MF.getTarget().getSubtargetImpl()->getInstrInfo());
130 *static_cast(MF.getSubtarget().getInstrInfo());
132131 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
133132 MachineFrameInfo &MFI = *MF.getFrameInfo();
134133
135134 unsigned FrameReg = getFrameRegister(MF);
136 const TargetFrameLowering *TFI =
137 MF.getTarget().getSubtargetImpl()->getFrameLowering();
135 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
138136 if (!TFI->hasFP(MF)) {
139137 // We will not reserve space on the stack for the lr and fp registers.
140138 Offset -= 2 * Hexagon_WordSize;
279277
280278 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
281279 &MF) const {
282 const TargetFrameLowering *TFI =
283 MF.getTarget().getSubtargetImpl()->getFrameLowering();
280 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
284281 if (TFI->hasFP(MF)) {
285282 return Hexagon::R30;
286283 }
190190 }
191191
192192 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
193 const TargetInstrInfo *TII =
194 Fn.getTarget().getSubtargetImpl()->getInstrInfo();
193 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
195194 MachineLoopInfo &MLI = getAnalysis();
196195 MachineDominatorTree &MDT = getAnalysis();
197196 const MachineBranchProbabilityInfo *MBPI =
5353 }
5454
5555 bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) {
56 const MSP430InstrInfo *TII = static_cast(
57 Fn.getTarget().getSubtargetImpl()->getInstrInfo());
56 const MSP430InstrInfo *TII =
57 static_cast(Fn.getSubtarget().getInstrInfo());
5858 // Give the blocks of the function a dense, in-order, numbering.
5959 Fn.RenumberBlocks();
6060 BlockSizes.resize(Fn.getNumBlockIDs());
4343 MachineFrameInfo *MFI = MF.getFrameInfo();
4444 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
4545 const MSP430InstrInfo &TII =
46 *static_cast(
47 MF.getTarget().getSubtargetImpl()->getInstrInfo());
46 *static_cast(MF.getSubtarget().getInstrInfo());
4847
4948 MachineBasicBlock::iterator MBBI = MBB.begin();
5049 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
109108 const MachineFrameInfo *MFI = MF.getFrameInfo();
110109 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
111110 const MSP430InstrInfo &TII =
112 *static_cast(
113 MF.getTarget().getSubtargetImpl()->getInstrInfo());
111 *static_cast(MF.getSubtarget().getInstrInfo());
114112
115113 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
116114 unsigned RetOpcode = MBBI->getOpcode();
190188 if (MI != MBB.end()) DL = MI->getDebugLoc();
191189
192190 MachineFunction &MF = *MBB.getParent();
193 const TargetInstrInfo &TII =
194 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
191 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
195192 MSP430MachineFunctionInfo *MFI = MF.getInfo();
196193 MFI->setCalleeSavedFrameSize(CSI.size() * 2);
197194
217214 if (MI != MBB.end()) DL = MI->getDebugLoc();
218215
219216 MachineFunction &MF = *MBB.getParent();
220 const TargetInstrInfo &TII =
221 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
217 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
222218
223219 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
224220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
230226 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
231227 MachineBasicBlock::iterator I) const {
232228 const MSP430InstrInfo &TII =
233 *static_cast(
234 MF.getTarget().getSubtargetImpl()->getInstrInfo());
229 *static_cast(MF.getSubtarget().getInstrInfo());
235230 unsigned StackAlign = getStackAlignment();
236231
237232 if (!hasReservedCallFrame(MF)) {
306306 return 0;
307307 case TargetOpcode::INLINEASM: {
308308 const MachineFunction *MF = MI->getParent()->getParent();
309 const TargetInstrInfo &TII =
310 *MF->getTarget().getSubtargetImpl()->getInstrInfo();
309 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
311310 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
312311 *MF->getTarget().getMCAsmInfo());
313312 }
3636
3737 const MCPhysReg*
3838 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
39 const TargetFrameLowering *TFI =
40 MF->getTarget().getSubtargetImpl()->getFrameLowering();
39 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
4140 const Function* F = MF->getFunction();
4241 static const MCPhysReg CalleeSavedRegs[] = {
4342 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
7372
7473 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
7574 BitVector Reserved(getNumRegs());
76 const TargetFrameLowering *TFI =
77 MF.getTarget().getSubtargetImpl()->getFrameLowering();
75 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
7876
7977 // Mark 4 special registers with subregisters as reserved.
8078 Reserved.set(MSP430::PCB);
110108 MachineInstr &MI = *II;
111109 MachineBasicBlock &MBB = *MI.getParent();
112110 MachineFunction &MF = *MBB.getParent();
113 const TargetFrameLowering *TFI =
114 MF.getTarget().getSubtargetImpl()->getFrameLowering();
111 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
115112 DebugLoc dl = MI.getDebugLoc();
116113 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
117114
133130 // This is actually "load effective address" of the stack slot
134131 // instruction. We have only two-address instructions, thus we need to
135132 // expand it into mov + add
136 const TargetInstrInfo &TII =
137 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
138134
139135 MI.setDesc(TII.get(MSP430::MOV16rr));
140136 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
159155 }
160156
161157 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
162 const TargetFrameLowering *TFI =
163 MF.getTarget().getSubtargetImpl()->getFrameLowering();
158 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
164159
165160 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
166161 }
3535 MachineBasicBlock &MBB = MF.front();
3636 MachineFrameInfo *MFI = MF.getFrameInfo();
3737 const Mips16InstrInfo &TII =
38 *static_cast(
39 MF.getTarget().getSubtargetImpl()->getInstrInfo());
38 *static_cast(MF.getSubtarget().getInstrInfo());
4039 MachineBasicBlock::iterator MBBI = MBB.begin();
4140 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
4241 uint64_t StackSize = MFI->getStackSize();
8483 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
8584 MachineFrameInfo *MFI = MF.getFrameInfo();
8685 const Mips16InstrInfo &TII =
87 *static_cast(
88 MF.getTarget().getSubtargetImpl()->getInstrInfo());
86 *static_cast(MF.getSubtarget().getInstrInfo());
8987 DebugLoc dl = MBBI->getDebugLoc();
9088 uint64_t StackSize = MFI->getStackSize();
9189
155153 Amount = -Amount;
156154
157155 const Mips16InstrInfo &TII =
158 *static_cast(
159 MF.getTarget().getSubtargetImpl()->getInstrInfo());
156 *static_cast(MF.getSubtarget().getInstrInfo());
160157
161158 TII.adjustStackPtr(Mips::SP, Amount, MBB, I);
162159 }
176173 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
177174 RegScavenger *RS) const {
178175 const Mips16InstrInfo &TII =
179 *static_cast(
180 MF.getTarget().getSubtargetImpl()->getInstrInfo());
176 *static_cast(MF.getSubtarget().getInstrInfo());
181177 const MipsRegisterInfo &RI = TII.getRegisterInfo();
182178 const BitVector Reserved = RI.getReservedRegs(MF);
183179 bool SaveS2 = Reserved[Mips::S2];
7171 MachineBasicBlock &MBB = MF.front();
7272 MachineBasicBlock::iterator I = MBB.begin();
7373 MachineRegisterInfo &RegInfo = MF.getRegInfo();
74 const TargetInstrInfo &TII =
75 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
74 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
7675 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
7776 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
7877 const TargetRegisterClass *RC =
103102
104103 MachineBasicBlock &MBB = MF.front();
105104 MachineBasicBlock::iterator I = MBB.begin();
106 const TargetInstrInfo &TII =
107 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
105 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
108106 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
109107 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
110108
6464 const TargetRegisterClass *RC,
6565 unsigned Reg) const {
6666 DebugLoc DL;
67 const TargetInstrInfo &TII =
68 *MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo();
67 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
6968 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
7069 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
7170 return true;
106105 if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
107106 FrameReg = Mips::SP;
108107 else {
109 const TargetFrameLowering *TFI =
110 MF.getTarget().getSubtargetImpl()->getFrameLowering();
108 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
111109 if (TFI->hasFP(MF)) {
112110 FrameReg = Mips::S0;
113111 }
142140 unsigned NewImm;
143141 const Mips16InstrInfo &TII =
144142 *static_cast(
145 MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo());
143 MBB.getParent()->getSubtarget().getInstrInfo());
146144 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
147145 Offset = SignExtend64<16>(NewImm);
148146 IsKill = true;
562562 // identity mapping of CPI's to CPE's.
563563 const std::vector &CPs = MCP->getConstants();
564564
565 const DataLayout &TD = *MF->getTarget().getSubtargetImpl()->getDataLayout();
565 const DataLayout &TD = *MF->getSubtarget().getDataLayout();
566566 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
567567 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
568568 assert(Size >= 4 && "Too small constant pool entry");
9999
100100 uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
101101 const MachineFrameInfo *MFI = MF.getFrameInfo();
102 const TargetRegisterInfo &TRI =
103 *MF.getTarget().getSubtargetImpl()->getRegisterInfo();
102 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
104103
105104 int64_t Offset = 0;
106105
24732473
24742474 MachineFunction &MF = DAG.getMachineFunction();
24752475 MachineFrameInfo *MFI = MF.getFrameInfo();
2476 const TargetFrameLowering *TFL =
2477 MF.getTarget().getSubtargetImpl()->getFrameLowering();
2476 const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
24782477 MipsFunctionInfo *FuncInfo = MF.getInfo();
24792478 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
24802479
129129 static void setCallTargetReg(MachineBasicBlock *MBB,
130130 MachineBasicBlock::iterator I) {
131131 MachineFunction &MF = *MBB->getParent();
132 const TargetInstrInfo &TII =
133 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
132 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134133 unsigned SrcReg = I->getOperand(0).getReg();
135134 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
136135 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
6161 case Mips::GPR32RegClassID:
6262 case Mips::GPR64RegClassID:
6363 case Mips::DSPRRegClassID: {
64 const TargetFrameLowering *TFI =
65 MF.getTarget().getSubtargetImpl()->getFrameLowering();
64 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
6665 return 28 - TFI->hasFP(MF);
6766 }
6867 case Mips::FGR32RegClassID:
161160 Reserved.set(*Reg);
162161 }
163162 // Reserve FP if this function should have a dedicated frame pointer register.
164 if (MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF)) {
163 if (MF.getSubtarget().getFrameLowering()->hasFP(MF)) {
165164 if (Subtarget.inMips16Mode())
166165 Reserved.set(Mips::S0);
167166 else {
250249
251250 unsigned MipsRegisterInfo::
252251 getFrameRegister(const MachineFunction &MF) const {
253 const TargetFrameLowering *TFI =
254 MF.getTarget().getSubtargetImpl()->getFrameLowering();
252 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
255253 bool IsN64 = Subtarget.isABI_N64();
256254
257255 if (Subtarget.inMips16Mode())
146146 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
147147
148148 const MipsSEInstrInfo &TII =
149 *static_cast(
150 MF.getTarget().getSubtargetImpl()->getInstrInfo());
151 const MipsRegisterInfo &RegInfo =
152 *static_cast(
153 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
149 *static_cast(MF.getSubtarget().getInstrInfo());
150 const MipsRegisterInfo &RegInfo = *static_cast(
151 MF.getSubtarget().getRegisterInfo());
154152
155153 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
156154 unsigned VR = MRI.createVirtualRegister(RC);
168166 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
169167
170168 const MipsSEInstrInfo &TII =
171 *static_cast(
172 MF.getTarget().getSubtargetImpl()->getInstrInfo());
173 const MipsRegisterInfo &RegInfo =
174 *static_cast(
175 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
169 *static_cast(MF.getSubtarget().getInstrInfo());
170 const MipsRegisterInfo &RegInfo = *static_cast(
171 MF.getSubtarget().getRegisterInfo());
176172
177173 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
178174 unsigned VR = MRI.createVirtualRegister(RC);
193189 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
194190
195191 const MipsSEInstrInfo &TII =
196 *static_cast(
197 MF.getTarget().getSubtargetImpl()->getInstrInfo());
198 const MipsRegisterInfo &RegInfo =
199 *static_cast(
200 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
192 *static_cast(MF.getSubtarget().getInstrInfo());
193 const MipsRegisterInfo &RegInfo = *static_cast(
194 MF.getSubtarget().getRegisterInfo());
201195
202196 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
203197 unsigned VR0 = MRI.createVirtualRegister(RC);
225219 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
226220
227221 const MipsSEInstrInfo &TII =
228 *static_cast(
229 MF.getTarget().getSubtargetImpl()->getInstrInfo());
230 const MipsRegisterInfo &RegInfo =
231 *static_cast(
232 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
222 *static_cast(MF.getSubtarget().getInstrInfo());
223 const MipsRegisterInfo &RegInfo = *static_cast(
224 MF.getSubtarget().getRegisterInfo());
233225
234226 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
235227 unsigned VR0 = MRI.createVirtualRegister(RC);
262254 // copy dst_hi, $vr1
263255
264256 const MipsSEInstrInfo &TII =
265 *static_cast(
266 MF.getTarget().getSubtargetImpl()->getInstrInfo());
267 const MipsRegisterInfo &RegInfo =
268 *static_cast(
269 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
257 *static_cast(MF.getSubtarget().getInstrInfo());
258 const MipsRegisterInfo &RegInfo = *static_cast(
259 MF.getSubtarget().getRegisterInfo());
270260
271261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
272262 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
421411 MipsFunctionInfo *MipsFI = MF.getInfo();
422412
423413 const MipsSEInstrInfo &TII =
424 *static_cast(
425 MF.getTarget().getSubtargetImpl()->getInstrInfo());
426 const MipsRegisterInfo &RegInfo =
427 *static_cast(
428 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
414 *static_cast(MF.getSubtarget().getInstrInfo());
415 const MipsRegisterInfo &RegInfo = *static_cast(
416 MF.getSubtarget().getRegisterInfo());
429417
430418 MachineBasicBlock::iterator MBBI = MBB.begin();
431419 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
558546 MipsFunctionInfo *MipsFI = MF.getInfo();
559547
560548 const MipsSEInstrInfo &TII =
561 *static_cast(
562 MF.getTarget().getSubtargetImpl()->getInstrInfo());
563 const MipsRegisterInfo &RegInfo =
564 *static_cast(
565 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
549 *static_cast(MF.getSubtarget().getInstrInfo());
550 const MipsRegisterInfo &RegInfo = *static_cast(
551 MF.getSubtarget().getRegisterInfo());
566552
567553 DebugLoc dl = MBBI->getDebugLoc();
568554 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
615601 const TargetRegisterInfo *TRI) const {
616602 MachineFunction *MF = MBB.getParent();
617603 MachineBasicBlock *EntryBlock = MF->begin();
618 const TargetInstrInfo &TII =
619 *MF->getTarget().getSubtargetImpl()->getInstrInfo();
604 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
620605
621606 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
622607 // Add the callee-saved register as live-in. Do not add if the register is
657642 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
658643 MachineBasicBlock::iterator I) const {
659644 const MipsSEInstrInfo &TII =
660 *static_cast(
661 MF.getTarget().getSubtargetImpl()->getInstrInfo());
645 *static_cast(MF.getSubtarget().getInstrInfo());
662646
663647 if (!hasReservedCallFrame(MF)) {
664648 int64_t Amount = I->getOperand(0).getImm();
129129 MachineBasicBlock &MBB = MF.front();
130130 MachineBasicBlock::iterator I = MBB.begin();
131131 MachineRegisterInfo &RegInfo = MF.getRegInfo();
132 const TargetInstrInfo &TII =
133 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
132 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134133 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135134 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136135 const TargetRegisterClass *RC;
171171 unsigned Reg = RegInfo.createVirtualRegister(RC);
172172 const MipsSEInstrInfo &TII =
173173 *static_cast(
174 MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo());
174 MBB.getParent()->getSubtarget().getInstrInfo());
175175 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
176176
177177 FrameReg = Reg;
186186 unsigned NewImm = 0;
187187 const MipsSEInstrInfo &TII =
188188 *static_cast(
189 MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo());
189 MBB.getParent()->getSubtarget().getInstrInfo());
190190 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
191191 OffsetBitSize == 16 ? &NewImm : nullptr);
192192 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
9696 Subtarget = &NoMips16Subtarget;
9797 else
9898 Subtarget = &DefaultSubtarget;
99 MF->setSubtarget(Subtarget);
99100 return;
100101 }
101102
17721772
17731773 // Map the global virtual register number to a register class specific
17741774 // virtual register number starting from 1 with that class.
1775 const TargetRegisterInfo *TRI =
1776 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
1775 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
17771776 //unsigned numRegClasses = TRI->getNumRegClasses();
17781777
17791778 // Emit the Fake Stack Object
4747 if (is64bit) {
4848 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
4949 MachineInstr *MI =
50 BuildMI(MBB, MBBI, dl,
51 MF.getTarget().getSubtargetImpl()->getInstrInfo()->get(
52 NVPTX::cvta_local_yes_64),
50 BuildMI(MBB, MBBI, dl, MF.getSubtarget().getInstrInfo()->get(
51 NVPTX::cvta_local_yes_64),
5352 NVPTX::VRFrame).addReg(LocalReg);
5453 BuildMI(MBB, MI, dl,
55 MF.getTarget().getSubtargetImpl()->getInstrInfo()->get(
56 NVPTX::MOV_DEPOT_ADDR_64),
54 MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64),
5755 LocalReg).addImm(MF.getFunctionNumber());
5856 } else {
5957 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
6058 MachineInstr *MI =
6159 BuildMI(MBB, MBBI, dl,
62 MF.getTarget().getSubtargetImpl()->getInstrInfo()->get(
63 NVPTX::cvta_local_yes),
60 MF.getSubtarget().getInstrInfo()->get(NVPTX::cvta_local_yes),
6461 NVPTX::VRFrame).addReg(LocalReg);
6562 BuildMI(MBB, MI, dl,
66 MF.getTarget().getSubtargetImpl()->getInstrInfo()->get(
67 NVPTX::MOV_DEPOT_ADDR),
63 MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR),
6864 LocalReg).addImm(MF.getFunctionNumber());
6965 }
7066 }
20272027
20282028 const Function *F = MF.getFunction();
20292029 const AttributeSet &PAL = F->getAttributes();
2030 const TargetLowering *TLI =
2031 DAG.getTarget().getSubtargetImpl()->getTargetLowering();
2030 const TargetLowering *TLI = DAG.getSubtarget().getTargetLowering();
20322031
20332032 SDValue Root = DAG.getRoot();
20342033 std::vector OutChains;
108108
109109 void
110110 NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
111 const TargetFrameLowering &TFI =
112 *Fn.getTarget().getSubtargetImpl()->getFrameLowering();
113 const TargetRegisterInfo *RegInfo =
114 Fn.getTarget().getSubtargetImpl()->getRegisterInfo();
111 const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering();
112 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
115113
116114 bool StackGrowsDown =
117115 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
6363 }
6464
6565 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
66 const PPCInstrInfo *TII = static_cast(
67 Fn.getTarget().getSubtargetImpl()->getInstrInfo());
66 const PPCInstrInfo *TII =
67 static_cast(Fn.getSubtarget().getInstrInfo());
6868 // Give the blocks of the function a dense, in-order, numbering.
6969 Fn.RenumberBlocks();
7070 BlockSizes.resize(Fn.getNumBlockIDs());
253253 // transform this into the appropriate ORI instruction.
254254 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
255255 MachineFunction *MF = MI->getParent()->getParent();
256 const TargetRegisterInfo *TRI =
257 MF->getTarget().getSubtargetImpl()->getRegisterInfo();
256 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
258257 DebugLoc dl = MI->getDebugLoc();
259258
260259 unsigned UsedRegMask = 0;
371370 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372371 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
373372
374 const PPCRegisterInfo *RegInfo = static_cast(
375 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
373 const PPCRegisterInfo *RegInfo =
374 static_cast(MF.getSubtarget().getRegisterInfo());
376375
377376 // If we are a leaf function, and use up to 224 bytes of stack space,
378377 // don't have a frame pointer, calls, or dynamic alloca then we do not need
459458 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
460459 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
461460
462 const PPCRegisterInfo *RegInfo = static_cast(
463 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
461 const PPCRegisterInfo *RegInfo =
462 static_cast(MF.getSubtarget().getRegisterInfo());
464463 bool HasBP = RegInfo->hasBasePointer(MF);
465464 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
466465 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
498497 MachineBasicBlock::iterator MBBI = MBB.begin();
499498 MachineFrameInfo *MFI = MF.getFrameInfo();
500499 const PPCInstrInfo &TII =
501 *static_cast(
502 MF.getTarget().getSubtargetImpl()->getInstrInfo());
503 const PPCRegisterInfo *RegInfo = static_cast(
504 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
500 *static_cast(MF.getSubtarget().getInstrInfo());
501 const PPCRegisterInfo *RegInfo =
502 static_cast(MF.getSubtarget().getRegisterInfo());
505503
506504 MachineModuleInfo &MMI = MF.getMMI();
507505 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
825823 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
826824 assert(MBBI != MBB.end() && "Returning block has no terminator");
827825 const PPCInstrInfo &TII =
828 *static_cast(
829 MF.getTarget().getSubtargetImpl()->getInstrInfo());
830 const PPCRegisterInfo *RegInfo = static_cast(
831 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
826 *static_cast(MF.getSubtarget().getInstrInfo());
827 const PPCRegisterInfo *RegInfo =
828 static_cast(MF.getSubtarget().getRegisterInfo());
832829
833830 unsigned RetOpcode = MBBI->getOpcode();
834831 DebugLoc dl;
10701067 void
10711068 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
10721069 RegScavenger *) const {
1073 const PPCRegisterInfo *RegInfo = static_cast(
1074 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1070 const PPCRegisterInfo *RegInfo =
1071 static_cast(MF.getSubtarget().getRegisterInfo());
10751072
10761073 // Save and clear the LR state.
10771074 PPCFunctionInfo *FI = MF.getInfo();
12031200 }
12041201
12051202 PPCFunctionInfo *PFI = MF.getInfo();
1206 const TargetRegisterInfo *TRI =
1207 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
1203 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
12081204
12091205 int64_t LowerBound = 0;
12101206
12381234 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
12391235 }
12401236
1241 const PPCRegisterInfo *RegInfo = static_cast(
1242 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1237 const PPCRegisterInfo *RegInfo =
1238 static_cast(MF.getSubtarget().getRegisterInfo());
12431239 if (RegInfo->hasBasePointer(MF)) {
12441240 HasGPSaveArea = true;
12451241
13871383
13881384 MachineFunction *MF = MBB.getParent();
13891385 const PPCInstrInfo &TII =
1390 *static_cast(
1391 MF->getTarget().getSubtargetImpl()->getInstrInfo());
1386 *static_cast(MF->getSubtarget().getInstrInfo());
13921387 DebugLoc DL;
13931388 bool CRSpilled = false;
13941389 MachineInstrBuilder CRMIB;
14501445
14511446 MachineFunction *MF = MBB.getParent();
14521447 const PPCInstrInfo &TII =
1453 *static_cast(
1454 MF->getTarget().getSubtargetImpl()->getInstrInfo());
1448 *static_cast(MF->getSubtarget().getInstrInfo());
14551449 DebugLoc DL;
14561450 unsigned RestoreOp, MoveReg;
14571451
14841478 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
14851479 MachineBasicBlock::iterator I) const {
14861480 const PPCInstrInfo &TII =
1487 *static_cast(
1488 MF.getTarget().getSubtargetImpl()->getInstrInfo());
1481 *static_cast(MF.getSubtarget().getInstrInfo());
14891482 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
14901483 I->getOpcode() == PPC::ADJCALLSTACKUP) {
14911484 // Add (actually subtract) back the amount the callee popped on return.
15351528
15361529 MachineFunction *MF = MBB.getParent();
15371530 const PPCInstrInfo &TII =
1538 *static_cast(
1539 MF->getTarget().getSubtargetImpl()->getInstrInfo());
1531 *static_cast(MF->getSubtarget().getInstrInfo());
15401532 bool CR2Spilled = false;
15411533 bool CR3Spilled = false;
15421534 bool CR4Spilled = false;
857857 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
858858 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
859859 SelectionDAG &DAG) {
860 bool IsLE =
861 DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian();
860 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
862861 if (ShuffleKind == 0) {
863862 if (IsLE)
864863 return false;
889888 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
890889 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
891890 SelectionDAG &DAG) {
892 bool IsLE =
893 DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian();
891 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
894892 if (ShuffleKind == 0) {
895893 if (IsLE)
896894 return false;
945943 /// the input operands are swapped (see PPCInstrAltivec.td).
946944 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
947945 unsigned ShuffleKind, SelectionDAG &DAG) {
948 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
946 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
949947 if (ShuffleKind == 1) // unary
950948 return isVMerge(N, UnitSize, 0, 0);
951949 else if (ShuffleKind == 2) // swapped
970968 /// the input operands are swapped (see PPCInstrAltivec.td).
971969 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
972970 unsigned ShuffleKind, SelectionDAG &DAG) {
973 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
971 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
974972 if (ShuffleKind == 1) // unary
975973 return isVMerge(N, UnitSize, 8, 8);
976974 else if (ShuffleKind == 2) // swapped
10771075 SelectionDAG &DAG) {
10781076 ShuffleVectorSDNode *SVOp = cast(N);
10791077 assert(isSplatShuffleMask(SVOp, EltSize));
1080 if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian())
1078 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
10811079 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
10821080 else
10831081 return SVOp->getMaskElt(0) / EltSize;
1717 void PPCFunctionInfo::anchor() { }
1818
1919 MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const {
20 const DataLayout *DL = MF.getTarget().getSubtargetImpl()->getDataLayout();
20 const DataLayout *DL = MF.getSubtarget().getDataLayout();
2121 return MF.getContext().GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+
2222 Twine(MF.getFunctionNumber())+"$poff");
2323 }
140140 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
141141 BitVector Reserved(getNumRegs());
142142 const PPCFrameLowering *PPCFI = static_cast(
143 MF.getTarget().getSubtargetImpl()->getFrameLowering());
143 MF.getSubtarget().getFrameLowering());
144144
145145 // The ZERO register is not really a register, but the representation of r0
146146 // when used in instructions that treat r0 as the constant 0.
222222 unsigned
223223 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
224224 MachineFunction &MF) const {
225 const TargetFrameLowering *TFI =
226 MF.getTarget().getSubtargetImpl()->getFrameLowering();
225 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
227226 const unsigned DefaultSafety = 1;
228227
229228 switch (RC->getID()) {
287286 // Get the frame info.
288287 MachineFrameInfo *MFI = MF.getFrameInfo();
289288 // Get the instruction info.
290 const TargetInstrInfo &TII =
291 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
289 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
292290 // Determine whether 64-bit pointers are used.
293291 bool LP64 = Subtarget.isPPC64();
294292 DebugLoc dl = MI.getDebugLoc();
407405 // Get the instruction's basic block.
408406 MachineBasicBlock &MBB = *MI.getParent();
409407 MachineFunction &MF = *MBB.getParent();
410 const TargetInstrInfo &TII =
411 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
408 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
412409 DebugLoc dl = MI.getDebugLoc();
413410
414411 bool LP64 = Subtarget.isPPC64();
452449 // Get the instruction's basic block.
453450 MachineBasicBlock &MBB = *MI.getParent();
454451 MachineFunction &MF = *MBB.getParent();
455 const TargetInstrInfo &TII =
456 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
452 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
457453 DebugLoc dl = MI.getDebugLoc();
458454
459455 bool LP64 = Subtarget.isPPC64();
526522 // Get the instruction's basic block.
527523 MachineBasicBlock &MBB = *MI.getParent();
528524 MachineFunction &MF = *MBB.getParent();
529 const TargetInstrInfo &TII =
530 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
525 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
531526 DebugLoc dl = MI.getDebugLoc();
532527
533528 bool LP64 = Subtarget.isPPC64();
570565 // Get the instruction's basic block.
571566 MachineBasicBlock &MBB = *MI.getParent();
572567 MachineFunction &MF = *MBB.getParent();
573 const TargetInstrInfo &TII =
574 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
568 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
575569 DebugLoc dl = MI.getDebugLoc();
576570
577571 bool LP64 = Subtarget.isPPC64();
618612 // Get the instruction's basic block.
619613 MachineBasicBlock &MBB = *MI.getParent();
620614 MachineFunction &MF = *MBB.getParent();
621 const TargetInstrInfo &TII =
622 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
615 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
623616 DebugLoc dl = MI.getDebugLoc();
624617
625618 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
644637 // Get the instruction's basic block.
645638 MachineBasicBlock &MBB = *MI.getParent();
646639 MachineFunction &MF = *MBB.getParent();
647 const TargetInstrInfo &TII =
648 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
640 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
649641 DebugLoc dl = MI.getDebugLoc();
650642
651643 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
725717 // Get the basic block's function.
726718 MachineFunction &MF = *MBB.getParent();
727719 // Get the instruction info.
728 const TargetInstrInfo &TII =
729 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
720 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
730721 // Get the frame info.
731722 MachineFrameInfo *MFI = MF.getFrameInfo();
732723 DebugLoc dl = MI.getDebugLoc();
851842 }
852843
853844 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
854 const TargetFrameLowering *TFI =
855 MF.getTarget().getSubtargetImpl()->getFrameLowering();
845 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
856846
857847 if (!Subtarget.isPPC64())
858848 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
938928 MachineFunction &MF = *MBB.getParent();
939929
940930 const PPCFrameLowering *PPCFI = static_cast(
941 MF.getTarget().getSubtargetImpl()->getFrameLowering());
931 MF.getSubtarget().getFrameLowering());
942932 unsigned StackEst =
943933 PPCFI->determineFrameLayout(MF, false, true);
944934
972962 DL = Ins->getDebugLoc();
973963
974964 const MachineFunction &MF = *MBB->getParent();
975 const TargetInstrInfo &TII =
976 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
965 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
977966 const MCInstrDesc &MCID = TII.get(ADDriOpc);
978967 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
979968 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
998987
999988 MachineBasicBlock &MBB = *MI.getParent();
1000989 MachineFunction &MF = *MBB.getParent();
1001 const TargetInstrInfo &TII =
1002 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
990 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1003991 const MCInstrDesc &MCID = MI.getDesc();
1004992 MachineRegisterInfo &MRI = MF.getRegInfo();
1005993 MRI.constrainRegClass(BaseReg,
821821
822822 SDLoc DL(Addr);
823823 MachineFunction &MF = CurDAG->getMachineFunction();
824 const SIRegisterInfo *TRI = static_cast(
825 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
824 const SIRegisterInfo *TRI =
825 static_cast(MF.getSubtarget().getRegisterInfo());
826826 MachineRegisterInfo &MRI = MF.getRegInfo();
827827
828828
160160 bool prepare();
161161
162162 bool runOnMachineFunction(MachineFunction &MF) override {
163 TII = static_cast(
164 MF.getTarget().getSubtargetImpl()->getInstrInfo());
163 TII = static_cast(MF.getSubtarget().getInstrInfo());
165164 TRI = &TII->getRegisterInfo();
166165 DEBUG(MF.dump(););
167166 OrderedBlks.clear();
167167 }
168168
169169 bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
170 TII = static_cast(
171 MF.getTarget().getSubtargetImpl()->getInstrInfo());
170 TII = static_cast(MF.getSubtarget().getInstrInfo());
172171 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
173172 BB != BB_E; ++BB) {
174173 MachineBasicBlock &MBB = *BB;
476476 }
477477
478478 bool runOnMachineFunction(MachineFunction &MF) override {
479 TII = static_cast(
480 MF.getTarget().getSubtargetImpl()->getInstrInfo());
479 TII = static_cast(MF.getSubtarget().getInstrInfo());
481480 TRI = static_cast(
482 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
481 MF.getSubtarget().getRegisterInfo());
483482 R600MachineFunctionInfo *MFI = MF.getInfo();
484483
485484 CFStack CFStack(ST, MFI->getShaderType());
297297 }
298298
299299 bool runOnMachineFunction(MachineFunction &MF) override {
300 TII = static_cast(
301 MF.getTarget().getSubtargetImpl()->getInstrInfo());
300 TII = static_cast(MF.getSubtarget().getInstrInfo());
302301
303302 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
304303 BB != BB_E; ++BB) {
6565 }
6666
6767 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
68 TII = static_cast(
69 MF.getTarget().getSubtargetImpl()->getInstrInfo());
68 TII = static_cast(MF.getSubtarget().getInstrInfo());
7069
7170 const R600RegisterInfo &TRI = TII->getRegisterInfo();
7271
190190 MachineFunction * MF = BB->getParent();
191191 MachineRegisterInfo &MRI = MF->getRegInfo();
192192 MachineBasicBlock::iterator I = *MI;
193 const R600InstrInfo *TII = static_cast(
194 MF->getTarget().getSubtargetImpl()->getInstrInfo());
193 const R600InstrInfo *TII =
194 static_cast(MF->getSubtarget().getInstrInfo());
195195
196196 switch (MI->getOpcode()) {
197197 default:
645645 if (ijb < 0) {
646646 const MachineFunction &MF = DAG.getMachineFunction();
647647 const R600InstrInfo *TII = static_cast(
648 MF.getTarget().getSubtargetImpl()->getInstrInfo());
648 MF.getSubtarget().getInstrInfo());
649649 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
650650 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
651651 return DAG.getTargetExtractSubreg(
20802080 static bool
20812081 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
20822082 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2083 const R600InstrInfo *TII = static_cast(
2084 DAG.getTarget().getSubtargetImpl()->getInstrInfo());
2083 const R600InstrInfo *TII =
2084 static_cast(DAG.getSubtarget().getInstrInfo());
20852085 if (!Src.isMachineOpcode())
20862086 return false;
20872087 switch (Src.getMachineOpcode()) {
22052205 /// \brief Fold the instructions after selecting them
22062206 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
22072207 SelectionDAG &DAG) const {
2208 const R600InstrInfo *TII = static_cast(
2209 DAG.getTarget().getSubtargetImpl()->getInstrInfo());
2208 const R600InstrInfo *TII =
2209 static_cast(DAG.getSubtarget().getInstrInfo());
22102210 if (!Node->isMachineOpcode())
22112211 return Node;
22122212 unsigned Opcode = Node->getMachineOpcode();
10831083 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
10841084 const MachineFunction &MF) const {
10851085 const AMDGPUFrameLowering *TFL = static_cast(
1086 MF.getTarget().getSubtargetImpl()->getFrameLowering());
1086 MF.getSubtarget().getFrameLowering());
10871087
10881088 unsigned StackWidth = TFL->getStackWidth(MF);
10891089 int End = getIndirectIndexEnd(MF);
314314 }
315315
316316 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
317 TII = static_cast(
318 Fn.getTarget().getSubtargetImpl()->getInstrInfo());
317 TII = static_cast(Fn.getSubtarget().getInstrInfo());
319318 MRI = &(Fn.getRegInfo());
320319 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
321320 MBB != MBBe; ++MBB) {
151151 MachineDominatorTree &MDT)
152152 : VLIWPacketizerList(MF, MLI, MDT, true),
153153 TII(static_cast(
154 MF.getTarget().getSubtargetImpl()->getInstrInfo())),
154 MF.getSubtarget().getInstrInfo())),
155155 TRI(TII->getRegisterInfo()) {
156156 VLIW5 = !MF.getTarget().getSubtarget().hasCaymanISA();
157157 }
328328 };
329329
330330 bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
331 const TargetInstrInfo *TII =
332 Fn.getTarget().getSubtargetImpl()->getInstrInfo();
331 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
333332 MachineLoopInfo &MLI = getAnalysis();
334333 MachineDominatorTree &MDT = getAnalysis();
335334
195195
196196 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
197197 MachineRegisterInfo &MRI = MF.getRegInfo();
198 const SIRegisterInfo *TRI = static_cast(
199 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
200 const SIInstrInfo *TII = static_cast(
201 MF.getTarget().getSubtargetImpl()->getInstrInfo());
198 const SIRegisterInfo *TRI =
199 static_cast(MF.getSubtarget().getRegisterInfo());
200 const SIInstrInfo *TII =
201 static_cast(MF.getSubtarget().getInstrInfo());
202202 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
203203 BI != BE; ++BI) {
204204
7272
7373 bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
7474 MachineRegisterInfo &MRI = MF.getRegInfo();
75 const SIRegisterInfo *TRI = static_cast(
76 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
75 const SIRegisterInfo *TRI =
76 static_cast(MF.getSubtarget().getRegisterInfo());
7777 LiveIntervals *LIS = &getAnalysis();
7878
7979 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
346346 bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
347347 bool Changes = false;
348348
349 TII = static_cast(
350 MF.getTarget().getSubtargetImpl()->getInstrInfo());
351 TRI = static_cast(
352 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
349 TII = static_cast(MF.getSubtarget().getInstrInfo());
350 TRI =
351 static_cast(MF.getSubtarget().getRegisterInfo());
353352
354353 MRI = &MF.getRegInfo();
355354
442442 }
443443
444444 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
445 TII = static_cast(
446 MF.getTarget().getSubtargetImpl()->getInstrInfo());
447 TRI = static_cast(
448 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
445 TII = static_cast(MF.getSubtarget().getInstrInfo());
446 TRI =
447 static_cast(MF.getSubtarget().getRegisterInfo());
449448 SIMachineFunctionInfo *MFI = MF.getInfo();
450449
451450 bool HaveKill = false;
7070
7171 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
7272 MachineRegisterInfo &MRI = MF.getRegInfo();
73 const SIInstrInfo *TII = static_cast(
74 MF.getTarget().getSubtargetImpl()->getInstrInfo());
75 const TargetRegisterInfo *TRI =
76 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
73 const SIInstrInfo *TII =
74 static_cast(MF.getSubtarget().getInstrInfo());
75 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
7776 std::vector I1Defs;
7877
7978 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
176176
177177 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
178178 MachineRegisterInfo &MRI = MF.getRegInfo();
179 const SIInstrInfo *TII = static_cast(
180 MF.getTarget().getSubtargetImpl()->getInstrInfo());
179 const SIInstrInfo *TII =
180 static_cast(MF.getSubtarget().getInstrInfo());
181181 const SIRegisterInfo &TRI = TII->getRegisterInfo();
182182 std::vector I1Defs;
183183
4545
4646 DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
4747 const SparcInstrInfo &TII =
48 *static_cast(
49 MF.getTarget().getSubtargetImpl()->getInstrInfo());
48 *static_cast(MF.getSubtarget().getInstrInfo());
5049
5150 if (NumBytes >= -4096 && NumBytes < 4096) {
5251 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
8887 MachineBasicBlock &MBB = MF.front();
8988 MachineFrameInfo *MFI = MF.getFrameInfo();
9089 const SparcInstrInfo &TII =
91 *static_cast(
92 MF.getTarget().getSubtargetImpl()->getInstrInfo());
90 *static_cast(MF.getSubtarget().getInstrInfo());
9391 MachineBasicBlock::iterator MBBI = MBB.begin();
9492 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
9593
154152 SparcMachineFunctionInfo *FuncInfo = MF.getInfo();
155153 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
156154 const SparcInstrInfo &TII =
157 *static_cast(
158 MF.getTarget().getSubtargetImpl()->getInstrInfo());
155 *static_cast(MF.getSubtarget().getInstrInfo());
159156 DebugLoc dl = MBBI->getDebugLoc();
160157 assert(MBBI->getOpcode() == SP::RETL &&
161158 "Can only put epilog before 'retl' instruction!");
107107 return;
108108 }
109109
110 const TargetInstrInfo &TII =
111 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
110 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
112111
113112 // FIXME: it would be better to scavenge a register here instead of
114113 // reserving G1 all of the time.
174173
175174 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
176175 if (MI.getOpcode() == SP::STQFri) {
177 const TargetInstrInfo &TII =
178 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
176 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
179177 unsigned SrcReg = MI.getOperand(2).getReg();
180178 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
181179 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
187185 MI.getOperand(2).setReg(SrcOddReg);
188186 Offset += 8;
189187 } else if (MI.getOpcode() == SP::LDQFri) {
190 const TargetInstrInfo &TII =
191 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
188 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
192189 unsigned DestReg = MI.getOperand(0).getReg();
193190 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
194191 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
457457 }
458458
459459 bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
460 TII = static_cast(
461 F.getTarget().getSubtargetImpl()->getInstrInfo());
460 TII = static_cast(F.getSubtarget().getInstrInfo());
462461 TRI = &TII->getRegisterInfo();
463462
464463 bool Changed = false;
6565 RegScavenger *RS) const {
6666 MachineFrameInfo *MFFrame = MF.getFrameInfo();
6767 MachineRegisterInfo &MRI = MF.getRegInfo();
68 const TargetRegisterInfo *TRI =
69 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
68 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
7069 bool HasFP = hasFP(MF);
7170 SystemZMachineFunctionInfo *MFI = MF.getInfo();
7271 bool IsVarArg = MF.getFunction()->isVarArg();
110109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
111110 unsigned GPR64, bool IsImplicit) {
112111 const TargetRegisterInfo *RI =
113 MBB.getParent()->getTarget().getSubtargetImpl()->getRegisterInfo();
112 MBB.getParent()->getSubtarget().getRegisterInfo();
114113 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
115114 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
116115 if (!IsLive || !IsImplicit) {
129128 return false;
130129
131130 MachineFunction &MF = *MBB.getParent();
132 const TargetInstrInfo *TII =
133 MF.getTarget().getSubtargetImpl()->getInstrInfo();
131 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
134132 SystemZMachineFunctionInfo *ZFI = MF.getInfo();
135133 bool IsVarArg = MF.getFunction()->isVarArg();
136134 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
219217 return false;
220218
221219 MachineFunction &MF = *MBB.getParent();
222 const TargetInstrInfo *TII =
223 MF.getTarget().getSubtargetImpl()->getInstrInfo();
220 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
224221 SystemZMachineFunctionInfo *ZFI = MF.getInfo();
225222 bool HasFP = hasFP(MF);
226223 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
314311 void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
315312 MachineBasicBlock &MBB = MF.front();
316313 MachineFrameInfo *MFFrame = MF.getFrameInfo();
317 auto *ZII = static_cast(
318 MF.getTarget().getSubtargetImpl()->getInstrInfo());
314 auto *ZII =
315 static_cast(MF.getSubtarget().getInstrInfo());
319316 SystemZMachineFunctionInfo *ZFI = MF.getInfo();
320317 MachineBasicBlock::iterator MBBI = MBB.begin();
321318 MachineModuleInfo &MMI = MF.getMMI();
411408 void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
412409 MachineBasicBlock &MBB) const {
413410 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
414 auto *ZII = static_cast(
415 MF.getTarget().getSubtargetImpl()->getInstrInfo());
411 auto *ZII =
412 static_cast(MF.getSubtarget().getInstrInfo());
416413 SystemZMachineFunctionInfo *ZFI = MF.getInfo();
417414
418415 // Skip the return instruction.
674674 SystemZMachineFunctionInfo *FuncInfo =
675675 MF.getInfo();
676676 auto *TFL = static_cast(
677 DAG.getTarget().getSubtargetImpl()->getFrameLowering());
677 DAG.getSubtarget().getFrameLowering());
678678
679679 // Assign locations to all of the incoming arguments.
680680 SmallVector ArgLocs;
26152615 SystemZTargetLowering::emitSelect(MachineInstr *MI,
26162616 MachineBasicBlock *MBB) const {
26172617 const SystemZInstrInfo *TII = static_cast(
2618 MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo());
2618 MBB->getParent()->getSubtarget().getInstrInfo());
26192619
26202620 unsigned DestReg = MI->getOperand(0).getReg();
26212621 unsigned TrueReg = MI->getOperand(1).getReg();
26642664 unsigned StoreOpcode, unsigned STOCOpcode,
26652665 bool Invert) const {
26662666 const SystemZInstrInfo *TII = static_cast(
2667 MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo());
2667 MBB->getParent()->getSubtarget().getInstrInfo());
26682668
26692669 unsigned SrcReg = MI->getOperand(0).getReg();
26702670 MachineOperand Base = MI->getOperand(1);
27322732 unsigned BitSize,
27332733 bool Invert) const {
27342734 MachineFunction &MF = *MBB->getParent();
2735 const SystemZInstrInfo *TII = static_cast(
2736 MF.getTarget().getSubtargetImpl()->getInstrInfo());
2735 const SystemZInstrInfo *TII =
2736 static_cast(MF.getSubtarget().getInstrInfo());
27372737 MachineRegisterInfo &MRI = MF.getRegInfo();
27382738 bool IsSubWord = (BitSize < 32);
27392739
28562856 unsigned KeepOldMask,
28572857 unsigned BitSize) const {
28582858 MachineFunction &MF = *MBB->getParent();
2859 const SystemZInstrInfo *TII = static_cast(
2860 MF.getTarget().getSubtargetImpl()->getInstrInfo());
2859 const SystemZInstrInfo *TII =
2860 static_cast(MF.getSubtarget().getInstrInfo());
28612861 MachineRegisterInfo &MRI = MF.getRegInfo();
28622862 bool IsSubWord = (BitSize < 32);
28632863
29682968 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
29692969 MachineBasicBlock *MBB) const {
29702970 MachineFunction &MF = *MBB->getParent();
2971 const SystemZInstrInfo *TII = static_cast(
2972 MF.getTarget().getSubtargetImpl()->getInstrInfo());
2971 const SystemZInstrInfo *TII =
2972 static_cast(MF.getSubtarget().getInstrInfo());
29732973 MachineRegisterInfo &MRI = MF.getRegInfo();
29742974
29752975 // Extract the operands. Base can be a register or a frame index.
30853085 MachineBasicBlock *MBB,
30863086 bool ClearEven, unsigned SubReg) const {
30873087 MachineFunction &MF = *MBB->getParent();
3088 const SystemZInstrInfo *TII = static_cast(
3089 MF.getTarget().getSubtargetImpl()->getInstrInfo());
3088 const SystemZInstrInfo *TII =
3089 static_cast(MF.getSubtarget().getInstrInfo());
30903090 MachineRegisterInfo &MRI = MF.getRegInfo();
30913091 DebugLoc DL = MI->getDebugLoc();
30923092
31173117 MachineBasicBlock *MBB,
31183118 unsigned Opcode) const {
31193119 MachineFunction &MF = *MBB->getParent();
3120 const SystemZInstrInfo *TII = static_cast(
3121 MF.getTarget().getSubtargetImpl()->getInstrInfo());
3120 const SystemZInstrInfo *TII =
3121 static_cast(MF.getSubtarget().getInstrInfo());
31223122 MachineRegisterInfo &MRI = MF.getRegInfo();
31233123 DebugLoc DL = MI->getDebugLoc();
31243124
32873287 MachineBasicBlock *MBB,
32883288 unsigned Opcode) const {
32893289 MachineFunction &MF = *MBB->getParent();
3290 const SystemZInstrInfo *TII = static_cast(
3291 MF.getTarget().getSubtargetImpl()->getInstrInfo());
3290 const SystemZInstrInfo *TII =
3291 static_cast(MF.getSubtarget().getInstrInfo());