llvm.org GIT mirror llvm / 6025dbf
Implement pattern match from v1xx to v1xx for AArch64 Neon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200113 91177308-0d34-0410-b5e6-96231b3b80d8 Jiangning Liu 6 years ago
2 changed file(s) with 199 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
62106210 defm : NeonI_SDUP;
62116211 defm : NeonI_SDUP;
62126212
6213 // The following is for sext/zext from v1xx to v1xx
6214 multiclass NeonI_ext {
6215 // v1i32 -> v1i64
6216 def : Pat<(v1i64 (ExtOp (v1i32 FPR32:$Rn))),
6217 (EXTRACT_SUBREG
6218 (v2i64 (!cast(prefix # "_2S")
6219 (v2i32 (SUBREG_TO_REG (i64 0), $Rn, sub_32)), 0)),
6220 sub_64)>;
6221
6222 // v1i16 -> v1i32
6223 def : Pat<(v1i32 (ExtOp (v1i16 FPR16:$Rn))),
6224 (EXTRACT_SUBREG
6225 (v4i32 (!cast(prefix # "_4H")
6226 (v4i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)), 0)),
6227 sub_32)>;
6228
6229 // v1i8 -> v1i16
6230 def : Pat<(v1i16 (ExtOp (v1i8 FPR8:$Rn))),
6231 (EXTRACT_SUBREG
6232 (v8i16 (!cast(prefix # "_8B")
6233 (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
6234 sub_16)>;
6235
6236 // v1i8 -> v1i32
6237 def : Pat<(v1i32 (ExtOp (v1i8 FPR8:$Rn))),
6238 (EXTRACT_SUBREG
6239 (v4i32 (!cast(prefix # "_4H")
6240 (v4i16 (SUBREG_TO_REG (i64 0),
6241 (v1i16 (EXTRACT_SUBREG
6242 (v8i16 (!cast(prefix # "_8B")
6243 (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
6244 sub_16)),
6245 sub_16)), 0)),
6246 sub_32)>;
6247 }
6248
6249 defm NeonI_zext : NeonI_ext<"USHLLvvi", zext>;
6250 defm NeonI_sext : NeonI_ext<"SSHLLvvi", sext>;
6251
6252 // zext v1i8 -> v1i64
6253 def : Pat<(v1i64 (zext (v1i8 FPR8:$Rn))),
6254 (v1i64 (SUBREG_TO_REG (i64 0),
6255 (v1i8 (DUPbv_B
6256 (v16i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)),
6257 0)),
6258 sub_8))>;
6259
6260 // zext v1i16 -> v1i64
6261 def : Pat<(v1i64 (zext (v1i16 FPR16:$Rn))),
6262 (v1i64 (SUBREG_TO_REG (i64 0),
6263 (v1i16 (DUPhv_H
6264 (v8i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)),
6265 0)),
6266 sub_16))>;
6267
6268 // sext v1i8 -> v1i64
6269 def : Pat<(v1i64 (sext (v1i8 FPR8:$Rn))),
6270 (EXTRACT_SUBREG
6271 (v2i64 (SSHLLvvi_2S
6272 (v2i32 (SUBREG_TO_REG (i64 0),
6273 (v1i32 (EXTRACT_SUBREG
6274 (v4i32 (SSHLLvvi_4H
6275 (v4i16 (SUBREG_TO_REG (i64 0),
6276 (v1i16 (EXTRACT_SUBREG
6277 (v8i16 (SSHLLvvi_8B
6278 (v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
6279 sub_16)),
6280 sub_16)), 0)),
6281 sub_32)),
6282 sub_32)), 0)),
6283 sub_64)>;
6284
6285
6286 // sext v1i16 -> v1i64
6287 def : Pat<(v1i64 (sext (v1i16 FPR16:$Rn))),
6288 (EXTRACT_SUBREG
6289 (v2i64 (SSHLLvvi_2S
6290 (v2i32 (SUBREG_TO_REG (i64 0),
6291 (v1i32 (EXTRACT_SUBREG
6292 (v4i32 (SSHLLvvi_4H
6293 (v4i16 (SUBREG_TO_REG (i64 0), $Rn, sub_16)), 0)),
6294 sub_32)),
6295 sub_32)), 0)),
6296 sub_64)>;
6297
62136298 //===----------------------------------------------------------------------===//
62146299 // Non-Instruction Patterns
62156300 //===----------------------------------------------------------------------===//
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
1
2 define <1 x i64> @test_zext_v1i32_v1i64(<2 x i32> %v) nounwind readnone {
3 ; CHECK-LABEL: test_zext_v1i32_v1i64:
4 ; CHECK: ushll v0.2d, v0.2s, #0
5 %1 = extractelement <2 x i32> %v, i32 0
6 %2 = insertelement <1 x i32> undef, i32 %1, i32 0
7 %3 = zext <1 x i32> %2 to <1 x i64>
8 ret <1 x i64> %3
9 }
10
11 define <1 x i32> @test_zext_v1i16_v1i32(<4 x i16> %v) nounwind readnone {
12 ; CHECK-LABEL: test_zext_v1i16_v1i32:
13 ; CHECK: ushll v0.4s, v0.4h, #0
14 %1 = extractelement <4 x i16> %v, i32 0
15 %2 = insertelement <1 x i16> undef, i16 %1, i32 0
16 %3 = zext <1 x i16> %2 to <1 x i32>
17 ret <1 x i32> %3
18 }
19
20 define <1 x i16> @test_zext_v1i8_v1i16(<8 x i8> %v) nounwind readnone {
21 ; CHECK-LABEL: test_zext_v1i8_v1i16:
22 ; CHECK: ushll v0.8h, v0.8b, #0
23 %1 = extractelement <8 x i8> %v, i32 0
24 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
25 %3 = zext <1 x i8> %2 to <1 x i16>
26 ret <1 x i16> %3
27 }
28
29 define <1 x i32> @test_zext_v1i8_v1i32(<8 x i8> %v) nounwind readnone {
30 ; CHECK-LABEL: test_zext_v1i8_v1i32:
31 ; CHECK: ushll v0.8h, v0.8b, #0
32 ; CHECK: ushll v0.4s, v0.4h, #0
33 %1 = extractelement <8 x i8> %v, i32 0
34 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
35 %3 = zext <1 x i8> %2 to <1 x i32>
36 ret <1 x i32> %3
37 }
38
39 define <1 x i64> @test_zext_v1i16_v1i64(<4 x i16> %v) nounwind readnone {
40 ; CHECK-LABEL: test_zext_v1i16_v1i64:
41 ; CHECK: dup h0, v0.h[0]
42 %1 = extractelement <4 x i16> %v, i32 0
43 %2 = insertelement <1 x i16> undef, i16 %1, i32 0
44 %3 = zext <1 x i16> %2 to <1 x i64>
45 ret <1 x i64> %3
46 }
47
48 define <1 x i64> @test_zext_v1i8_v1i64(<8 x i8> %v) nounwind readnone {
49 ; CHECK-LABEL: test_zext_v1i8_v1i64:
50 ; CHECK: dup b0, v0.b[0]
51 %1 = extractelement <8 x i8> %v, i32 0
52 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
53 %3 = zext <1 x i8> %2 to <1 x i64>
54 ret <1 x i64> %3
55 }
56
57 define <1 x i64> @test_sext_v1i32_v1i64(<2 x i32> %v) nounwind readnone {
58 ; CHECK-LABEL: test_sext_v1i32_v1i64:
59 ; CHECK: sshll v0.2d, v0.2s, #0
60 %1 = extractelement <2 x i32> %v, i32 0
61 %2 = insertelement <1 x i32> undef, i32 %1, i32 0
62 %3 = sext <1 x i32> %2 to <1 x i64>
63 ret <1 x i64> %3
64 }
65
66 define <1 x i32> @test_sext_v1i16_v1i32(<4 x i16> %v) nounwind readnone {
67 ; CHECK-LABEL: test_sext_v1i16_v1i32:
68 ; CHECK: sshll v0.4s, v0.4h, #0
69 %1 = extractelement <4 x i16> %v, i32 0
70 %2 = insertelement <1 x i16> undef, i16 %1, i32 0
71 %3 = sext <1 x i16> %2 to <1 x i32>
72 ret <1 x i32> %3
73 }
74
75 define <1 x i16> @test_sext_v1i8_v1i16(<8 x i8> %v) nounwind readnone {
76 ; CHECK-LABEL: test_sext_v1i8_v1i16:
77 ; CHECK: sshll v0.8h, v0.8b, #0
78 %1 = extractelement <8 x i8> %v, i32 0
79 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
80 %3 = sext <1 x i8> %2 to <1 x i16>
81 ret <1 x i16> %3
82 }
83
84 define <1 x i32> @test_sext_v1i8_v1i32(<8 x i8> %v) nounwind readnone {
85 ; CHECK-LABEL: test_sext_v1i8_v1i32:
86 ; CHECK: sshll v0.8h, v0.8b, #0
87 ; CHECK: sshll v0.4s, v0.4h, #0
88 %1 = extractelement <8 x i8> %v, i32 0
89 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
90 %3 = sext <1 x i8> %2 to <1 x i32>
91 ret <1 x i32> %3
92 }
93
94 define <1 x i64> @test_sext_v1i16_v1i64(<4 x i16> %v) nounwind readnone {
95 ; CHECK-LABEL: test_sext_v1i16_v1i64:
96 ; CHECK: sshll v0.4s, v0.4h, #0
97 ; CHECK: sshll v0.2d, v0.2s, #0
98 %1 = extractelement <4 x i16> %v, i32 0
99 %2 = insertelement <1 x i16> undef, i16 %1, i32 0
100 %3 = sext <1 x i16> %2 to <1 x i64>
101 ret <1 x i64> %3
102 }
103
104 define <1 x i64> @test_sext_v1i8_v1i64(<8 x i8> %v) nounwind readnone {
105 ; CHECK-LABEL: test_sext_v1i8_v1i64:
106 ; CHECK: sshll v0.8h, v0.8b, #0
107 ; CHECK: sshll v0.4s, v0.4h, #0
108 ; CHECK: sshll v0.2d, v0.2s, #0
109 %1 = extractelement <8 x i8> %v, i32 0
110 %2 = insertelement <1 x i8> undef, i8 %1, i32 0
111 %3 = sext <1 x i8> %2 to <1 x i64>
112 ret <1 x i64> %3
113 }