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R600: Cleanup fadd and fsub tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214991 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 5 years ago
2 changed file(s) with 99 addition(s) and 77 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK --check-prefix=FUNC
1 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
0 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
22
33 ; FUNC-LABEL: @fadd_f32
4 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
5 ; SI-CHECK: V_ADD_F32
4 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
5 ; SI: V_ADD_F32
66 define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) {
7 entry:
8 %0 = fadd float %a, %b
9 store float %0, float addrspace(1)* %out
7 %add = fadd float %a, %b
8 store float %add, float addrspace(1)* %out, align 4
109 ret void
1110 }
1211
1312 ; FUNC-LABEL: @fadd_v2f32
14 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
15 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
16 ; SI-CHECK: V_ADD_F32
17 ; SI-CHECK: V_ADD_F32
13 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
14 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
15 ; SI: V_ADD_F32
16 ; SI: V_ADD_F32
1817 define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
19 entry:
20 %0 = fadd <2 x float> %a, %b
21 store <2 x float> %0, <2 x float> addrspace(1)* %out
18 %add = fadd <2 x float> %a, %b
19 store <2 x float> %add, <2 x float> addrspace(1)* %out, align 8
2220 ret void
2321 }
2422
2523 ; FUNC-LABEL: @fadd_v4f32
26 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
30 ; SI-CHECK: V_ADD_F32
31 ; SI-CHECK: V_ADD_F32
32 ; SI-CHECK: V_ADD_F32
33 ; SI-CHECK: V_ADD_F32
24 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; SI: V_ADD_F32
29 ; SI: V_ADD_F32
30 ; SI: V_ADD_F32
31 ; SI: V_ADD_F32
3432 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
3533 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
36 %a = load <4 x float> addrspace(1) * %in
37 %b = load <4 x float> addrspace(1) * %b_ptr
34 %a = load <4 x float> addrspace(1)* %in, align 16
35 %b = load <4 x float> addrspace(1)* %b_ptr, align 16
3836 %result = fadd <4 x float> %a, %b
39 store <4 x float> %result, <4 x float> addrspace(1)* %out
37 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
4038 ret void
4139 }
4240
4341 ; FUNC-LABEL: @fadd_v8f32
44 ; R600-CHECK: ADD
45 ; R600-CHECK: ADD
46 ; R600-CHECK: ADD
47 ; R600-CHECK: ADD
48 ; R600-CHECK: ADD
49 ; R600-CHECK: ADD
50 ; R600-CHECK: ADD
51 ; R600-CHECK: ADD
52 ; SI-CHECK: V_ADD_F32
53 ; SI-CHECK: V_ADD_F32
54 ; SI-CHECK: V_ADD_F32
55 ; SI-CHECK: V_ADD_F32
56 ; SI-CHECK: V_ADD_F32
57 ; SI-CHECK: V_ADD_F32
58 ; SI-CHECK: V_ADD_F32
59 ; SI-CHECK: V_ADD_F32
42 ; R600: ADD
43 ; R600: ADD
44 ; R600: ADD
45 ; R600: ADD
46 ; R600: ADD
47 ; R600: ADD
48 ; R600: ADD
49 ; R600: ADD
50 ; SI: V_ADD_F32
51 ; SI: V_ADD_F32
52 ; SI: V_ADD_F32
53 ; SI: V_ADD_F32
54 ; SI: V_ADD_F32
55 ; SI: V_ADD_F32
56 ; SI: V_ADD_F32
57 ; SI: V_ADD_F32
6058 define void @fadd_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) {
61 entry:
62 %0 = fadd <8 x float> %a, %b
63 store <8 x float> %0, <8 x float> addrspace(1)* %out
59 %add = fadd <8 x float> %a, %b
60 store <8 x float> %add, <8 x float> addrspace(1)* %out, align 32
6461 ret void
6562 }
None ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
1 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
0 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
22
3 ; R600-CHECK: @fsub_f32
4 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
5 ; SI-CHECK: @fsub_f32
6 ; SI-CHECK: V_SUB_F32
7 define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) {
8 entry:
9 %0 = fsub float %a, %b
10 store float %0, float addrspace(1)* %out
3
4 ; FUNC-LABEL: @v_fsub_f32
5 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
6 define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
7 %b_ptr = getelementptr float addrspace(1)* %in, i32 1
8 %a = load float addrspace(1)* %in, align 4
9 %b = load float addrspace(1)* %b_ptr, align 4
10 %result = fsub float %a, %b
11 store float %result, float addrspace(1)* %out, align 4
12 ret void
13 }
14
15 ; FUNC-LABEL: @s_fsub_f32
16 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
17
18 ; SI: V_SUB_F32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
19 define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) {
20 %sub = fsub float %a, %b
21 store float %sub, float addrspace(1)* %out, align 4
1122 ret void
1223 }
1324
1526
1627 declare void @llvm.AMDGPU.store.output(float, i32)
1728
18 ; R600-CHECK: @fsub_v2f32
19 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
20 ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
21 ; SI-CHECK: @fsub_v2f32
22 ; SI-CHECK: V_SUBREV_F32
23 ; SI-CHECK: V_SUBREV_F32
29 ; FUNC-LABEL: @fsub_v2f32
30 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
31 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
32
33 ; FIXME: Should be using SGPR directly for first operand
34 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
35 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
2436 define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
25 entry:
26 %0 = fsub <2 x float> %a, %b
27 store <2 x float> %0, <2 x float> addrspace(1)* %out
37 %sub = fsub <2 x float> %a, %b
38 store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8
2839 ret void
2940 }
3041
31 ; R600-CHECK: @fsub_v4f32
32 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
33 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
34 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
35 ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
36 ; SI-CHECK: @fsub_v4f32
37 ; SI-CHECK: V_SUBREV_F32
38 ; SI-CHECK: V_SUBREV_F32
39 ; SI-CHECK: V_SUBREV_F32
40 ; SI-CHECK: V_SUBREV_F32
41 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
42 ; FUNC-LABEL: @v_fsub_v4f32
43 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
44 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
45 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
46 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
47
48 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
49 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
50 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
51 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
52 define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
4253 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
43 %a = load <4 x float> addrspace(1) * %in
44 %b = load <4 x float> addrspace(1) * %b_ptr
54 %a = load <4 x float> addrspace(1)* %in, align 16
55 %b = load <4 x float> addrspace(1)* %b_ptr, align 16
4556 %result = fsub <4 x float> %a, %b
46 store <4 x float> %result, <4 x float> addrspace(1)* %out
57 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
4758 ret void
4859 }
60
61 ; FIXME: Should be using SGPR directly for first operand
62
63 ; FUNC-LABEL: @s_fsub_v4f32
64 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
65 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
66 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
67 ; SI: V_SUBREV_F32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
68 ; SI: S_ENDPGM
69 define void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
70 %result = fsub <4 x float> %a, %b
71 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
72 ret void
73 }