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Enable allocation of R3 in Thumb1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 10 years ago
5 changed file(s) with 4 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
739739 case ARM::R1:
740740 return ARM::R0;
741741 case ARM::R3:
742 // FIXME!
743 return STI.isThumb1Only() ? 0 : ARM::R2;
742 return ARM::R2;
744743 case ARM::R5:
745744 return ARM::R4;
746745 case ARM::R7:
829828 case ARM::R0:
830829 return ARM::R1;
831830 case ARM::R2:
832 // FIXME!
833 return STI.isThumb1Only() ? 0 : ARM::R3;
831 return ARM::R3;
834832 case ARM::R4:
835833 return ARM::R5;
836834 case ARM::R6:
221221 iterator allocation_order_begin(const MachineFunction &MF) const;
222222 iterator allocation_order_end(const MachineFunction &MF) const;
223223 }];
224 // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
225 // to generate large stack offset. Make it available once we have register
226 // scavenging.
227224 let MethodBodies = [{
228225 static const unsigned THUMB_tGPR_AO[] = {
229 ARM::R0, ARM::R1, ARM::R2,
226 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
230227 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
231228
232229 // FP is R7, only low registers available.
195195 objects are referenced off the frame pointer with negative offsets. See
196196 oggenc for an example.
197197
198 //===---------------------------------------------------------------------===//
199
200 We are reserving R3 as a scratch register under thumb mode. So if it is live in
201 to the function, we save / restore R3 to / from R12. Until register scavenging
202 is done, we should save R3 to a high callee saved reg at emitPrologue time
203 (when hasFP is true or stack size is large) and restore R3 from that register
204 instead. This allows us to at least get rid of the save to r12 everytime it is
205 used.
206198
207199 //===---------------------------------------------------------------------===//
208200
844844
845845 if (VARegSaveSize) {
846846 // Epilogue for vararg functions: pop LR to R3 and branch off it.
847 // FIXME: Verify this is still ok when R3 is no longer being reserved.
848847 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
849848 .addReg(0) // No write back.
850849 .addReg(ARM::R3, RegState::Define);
1010
1111 define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
1212 ; CHECK: t:
13 ; CHECK: adds r4, #8
13 ; CHECK: adds r3, #8
1414 entry:
1515 %val = alloca i64, align 4 ; [#uses=3]
1616 %0 = icmp eq %struct.asl_file_t* %s, null ; [#uses=1]