llvm.org GIT mirror llvm / 60079c1
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0. Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212747 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 5 years ago
3 changed file(s) with 25 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
12771277 def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
12781278
12791279 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
1280 // register class is constrained to GR8_NOREX.
1281 let isPseudo = 1 in
1280 // register class is constrained to GR8_NOREX. This pseudo is explicitly
1281 // marked side-effect free, since it doesn't have an isel pattern like
1282 // other test instructions.
1283 let isPseudo = 1, hasSideEffects = 0 in
12821284 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
12831285 "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;
12841286 } // Defs = [EFLAGS]
50365036 case X86::TEST16rm:
50375037 case X86::TEST32rm:
50385038 case X86::TEST64rm:
5039 case X86::TEST8ri_NOREX:
50395040 case X86::AND16i16:
50405041 case X86::AND16ri:
50415042 case X86::AND16ri8:
0 ; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s
1
2 ; testb should be scheduled right before je to enable macro-fusion.
3
4 ; CHECK: testb $2, %{{[abcd]}}h
5 ; CHECK-NEXT: je
6
7 define i32 @check_flag(i32 %flags, ...) nounwind {
8 entry:
9 %and = and i32 %flags, 512
10 %tobool = icmp eq i32 %and, 0
11 br i1 %tobool, label %if.end, label %if.then
12
13 if.then:
14 br label %if.end
15
16 if.end:
17 %hasflag = phi i32 [ 1, %if.then ], [ 0, %entry ]
18 ret i32 %hasflag
19 }