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[X86] Add NT load/store scheduler classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332274 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 5 months ago
13 changed file(s) with 148 addition(s) and 84 deletion(s). Raw diff Collapse all Expand all
43724372 }
43734373
43744374 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info,
4375 SchedWriteVecMoveLS>, PD;
4375 SchedWriteVecMoveLSNT>, PD;
43764376 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info,
4377 SchedWriteFMoveLS>, PD, VEX_W;
4377 SchedWriteFMoveLSNT>, PD, VEX_W;
43784378 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info,
4379 SchedWriteFMoveLS>, PS;
4379 SchedWriteFMoveLSNT>, PS;
43804380
43814381 let Predicates = [HasAVX512], AddedComplexity = 400 in {
43824382 def : Pat<(alignednontemporalstore (v16i32 VR512:$src), addr:$dst),
271271 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
272272 "movntq\t{$src, $dst|$dst, $src}",
273273 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
274 Sched<[SchedWriteVecMoveLS.MMX.MR]>;
274 Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;
275275
276276 let Predicates = [HasMMX] in {
277277 let AddedComplexity = 15 in
30163016
30173017 let AddedComplexity = 400 in { // Prefer non-temporal versions
30183018 let Predicates = [HasAVX, NoVLX] in {
3019 let SchedRW = [SchedWriteFMoveLS.XMM.MR] in {
3019 let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in {
30203020 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
30213021 (ins f128mem:$dst, VR128:$src),
30223022 "movntps\t{$src, $dst|$dst, $src}",
30293029 addr:$dst)]>, VEX, VEX_WIG;
30303030 } // SchedRW
30313031
3032 let SchedRW = [SchedWriteFMoveLS.YMM.MR] in {
3032 let SchedRW = [SchedWriteFMoveLSNT.YMM.MR] in {
30333033 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
30343034 (ins f256mem:$dst, VR256:$src),
30353035 "movntps\t{$src, $dst|$dst, $src}",
30483048 "movntdq\t{$src, $dst|$dst, $src}",
30493049 [(alignednontemporalstore (v2i64 VR128:$src),
30503050 addr:$dst)]>, VEX, VEX_WIG,
3051 Sched<[SchedWriteVecMoveLS.XMM.MR]>;
3051 Sched<[SchedWriteVecMoveLSNT.XMM.MR]>;
30523052 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
30533053 (ins i256mem:$dst, VR256:$src),
30543054 "movntdq\t{$src, $dst|$dst, $src}",
30553055 [(alignednontemporalstore (v4i64 VR256:$src),
30563056 addr:$dst)]>, VEX, VEX_L, VEX_WIG,
3057 Sched<[SchedWriteVecMoveLS.YMM.MR]>;
3057 Sched<[SchedWriteVecMoveLSNT.YMM.MR]>;
30583058 } // ExeDomain
30593059 } // Predicates
30603060
3061 let SchedRW = [SchedWriteFMoveLS.XMM.MR] in {
3061 let SchedRW = [SchedWriteFMoveLSNT.XMM.MR] in {
30623062 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
30633063 "movntps\t{$src, $dst|$dst, $src}",
30643064 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
30673067 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
30683068 } // SchedRW
30693069
3070 let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in
3070 let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLSNT.XMM.MR] in
30713071 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
30723072 "movntdq\t{$src, $dst|$dst, $src}",
30733073 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
30743074
3075 let SchedRW = [WriteStore] in {
3075 let SchedRW = [WriteStoreNT] in {
30763076 // There is no AVX form for instructions below this point
30773077 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
30783078 "movnti{l}\t{$src, $dst|$dst, $src}",
64086408 let Predicates = [HasAVX, NoVLX] in
64096409 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
64106410 "vmovntdqa\t{$src, $dst|$dst, $src}", []>,
6411 Sched<[SchedWriteVecMoveLS.XMM.RM]>, VEX, VEX_WIG;
6411 Sched<[SchedWriteVecMoveLSNT.XMM.RM]>, VEX, VEX_WIG;
64126412 let Predicates = [HasAVX2, NoVLX] in
64136413 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
64146414 "vmovntdqa\t{$src, $dst|$dst, $src}", []>,
6415 Sched<[SchedWriteVecMoveLS.YMM.RM]>, VEX, VEX_L, VEX_WIG;
6415 Sched<[SchedWriteVecMoveLSNT.YMM.RM]>, VEX, VEX_L, VEX_WIG;
64166416 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
64176417 "movntdqa\t{$src, $dst|$dst, $src}", []>,
6418 Sched<[SchedWriteVecMoveLS.XMM.RM]>;
6418 Sched<[SchedWriteVecMoveLSNT.XMM.RM]>;
64196419
64206420 let Predicates = [HasAVX2, NoVLX] in {
64216421 def : Pat<(v8f32 (alignednontemporalload addr:$src)),
69346934
69356935 // Non-temporal (unaligned) scalar stores.
69366936 let AddedComplexity = 400 in { // Prefer non-temporal versions
6937 let hasSideEffects = 0, mayStore = 1, SchedRW = [WriteStore] in {
6937 let hasSideEffects = 0, mayStore = 1, SchedRW = [SchedWriteFMoveLSNT.Scl.MR] in {
69386938 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
69396939 "movntss\t{$src, $dst|$dst, $src}", []>, XS;
69406940
146146 defm : BWWriteResPair;
147147
148148 // Loads, stores, and moves, not folded with other operations.
149 def : WriteRes { let Latency = 5; }
150 def : WriteRes;
151 def : WriteRes>;
149 defm : X86WriteRes>;
150 defm : X86WriteRes;
151 defm : X86WriteRes;
152 defm : X86WriteRes;
152153
153154 // Idioms that clear a register, like xorps %xmm0, %xmm0.
154155 // These can often bypass execution ports completely.
170171 defm : X86WriteRes;
171172 defm : X86WriteRes;
172173 defm : X86WriteRes;
174 defm : X86WriteRes;
175 defm : X86WriteRes;
176 defm : X86WriteRes;
173177 defm : X86WriteRes;
174178 defm : X86WriteRes;
175179 defm : X86WriteRes;
265269 defm : X86WriteRes;
266270 defm : X86WriteRes;
267271 defm : X86WriteRes;
272 defm : X86WriteRes;
273 defm : X86WriteRes;
268274 defm : X86WriteRes;
269275 defm : X86WriteRes;
270276 defm : X86WriteRes;
271277 defm : X86WriteRes;
272278 defm : X86WriteRes;
279 defm : X86WriteRes;
280 defm : X86WriteRes;
273281 defm : X86WriteRes;
274282 defm : X86WriteRes;
275283 defm : X86WriteRes;
577585 }
578586 def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
579587 "MMX_MOVD64mr",
580 "MOVNTI_64mr",
581 "MOVNTImr",
582588 "ST_FP(32|64|80)m",
583589 "(V?)MOV(H|L)(PD|PS)mr",
584590 "(V?)MOVPDI2DImr",
106106
107107 // Store_addr on 237.
108108 // Store_data on 4.
109 def : WriteRes;
110 def : WriteRes { let Latency = 5; }
111 def : WriteRes;
112 def : WriteRes>;
109 defm : X86WriteRes>;
110 defm : X86WriteRes;
111 defm : X86WriteRes;
112 defm : X86WriteRes;
113 def : WriteRes;
113114
114115 defm : HWWriteResPair;
115116 defm : HWWriteResPair;
160161 defm : X86WriteRes;
161162 defm : X86WriteRes;
162163 defm : X86WriteRes;
164 defm : X86WriteRes;
165 defm : X86WriteRes;
166 defm : X86WriteRes;
163167 defm : X86WriteRes;
164168 defm : X86WriteRes;
165169 defm : X86WriteRes;
256260 defm : X86WriteRes;
257261 defm : X86WriteRes;
258262 defm : X86WriteRes;
263 defm : X86WriteRes;
264 defm : X86WriteRes;
259265 defm : X86WriteRes;
260266 defm : X86WriteRes;
261267 defm : X86WriteRes;
262268 defm : X86WriteRes;
263269 defm : X86WriteRes;
270 defm : X86WriteRes;
271 defm : X86WriteRes;
264272 defm : X86WriteRes;
265273 defm : X86WriteRes;
266274 defm : X86WriteRes;
753761 }
754762 def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
755763 "MMX_MOVD64mr",
756 "MOVNTI_64mr",
757 "MOVNTImr",
758764 "ST_FP(32|64|80)m",
759765 "(V?)MOV(H|L)(PD|PS)mr",
760766 "(V?)MOVPDI2DImr",
9595 // 2/3 cycle to recompute the address.
9696 def : WriteRes;
9797
98 def : WriteRes;
99 def : WriteRes { let Latency = 5; }
100 def : WriteRes;
101 def : WriteResZero, []>;
98 def : WriteResStore, [SBPort23, SBPort4]>;
99 def : WriteRes;
100 def : WriteRes { let Latency = 5; }
101 def : WriteRes;
102 def : WriteRes;
102103
103104 defm : SBWriteResPair;
104105 defm : SBWriteResPair;
152153 defm : X86WriteRes;
153154 defm : X86WriteRes;
154155 defm : X86WriteRes;
156 defm : X86WriteRes;
157 defm : X86WriteRes;
158 defm : X86WriteRes;
155159 defm : X86WriteRes;
156160 defm : X86WriteRes;
157161 defm : X86WriteRes;
236240 defm : X86WriteRes;
237241 defm : X86WriteRes;
238242 defm : X86WriteRes;
243 defm : X86WriteRes;
244 defm : X86WriteRes;
239245 defm : X86WriteRes;
240246 defm : X86WriteRes;
241247 defm : X86WriteRes;
242248 defm : X86WriteRes;
243249 defm : X86WriteRes;
250 defm : X86WriteRes;
251 defm : X86WriteRes;
244252 defm : X86WriteRes;
245253 defm : X86WriteRes;
246254 defm : X86WriteRes;
144144 defm : SKLWriteResPair;
145145
146146 // Loads, stores, and moves, not folded with other operations.
147 def : WriteRes { let Latency = 5; }
148 def : WriteRes;
149 def : WriteRes>;
147 defm : X86WriteRes>;
148 defm : X86WriteRes;
149 defm : X86WriteRes;
150 defm : X86WriteRes;
150151
151152 // Idioms that clear a register, like xorps %xmm0, %xmm0.
152153 // These can often bypass execution ports completely.
165166 defm : X86WriteRes;
166167 defm : X86WriteRes;
167168 defm : X86WriteRes;
169 defm : X86WriteRes;
170 defm : X86WriteRes;
171 defm : X86WriteRes;
168172 defm : X86WriteRes;
169173 defm : X86WriteRes;
170174 defm : X86WriteRes;
257261 defm : X86WriteRes;
258262 defm : X86WriteRes;
259263 defm : X86WriteRes;
264 defm : X86WriteRes;
265 defm : X86WriteRes;
260266 defm : X86WriteRes;
261267 defm : X86WriteRes;
262268 defm : X86WriteRes;
263269 defm : X86WriteRes;
264270 defm : X86WriteRes;
271 defm : X86WriteRes;
272 defm : X86WriteRes;
265273 defm : X86WriteRes;
266274 defm : X86WriteRes;
267275 defm : X86WriteRes;
579587 }
580588 def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
581589 "MMX_MOVD64mr",
582 "MOVNTI_64mr",
583 "MOVNTImr",
584590 "ST_FP(32|64|80)m",
585591 "(V?)MOV(H|L)(PD|PS)mr",
586592 "(V?)MOVPDI2DImr",
144144 defm : SKXWriteResPair;
145145
146146 // Loads, stores, and moves, not folded with other operations.
147 def : WriteRes { let Latency = 5; }
148 def : WriteRes;
149 def : WriteRes>;
147 defm : X86WriteRes>;
148 defm : X86WriteRes;
149 defm : X86WriteRes;
150 defm : X86WriteRes;
150151
151152 // Idioms that clear a register, like xorps %xmm0, %xmm0.
152153 // These can often bypass execution ports completely.
165166 defm : X86WriteRes;
166167 defm : X86WriteRes;
167168 defm : X86WriteRes;
169 defm : X86WriteRes;
170 defm : X86WriteRes;
171 defm : X86WriteRes;
168172 defm : X86WriteRes;
169173 defm : X86WriteRes;
170174 defm : X86WriteRes;
257261 defm : X86WriteRes;
258262 defm : X86WriteRes;
259263 defm : X86WriteRes;
264 defm : X86WriteRes;
265 defm : X86WriteRes;
260266 defm : X86WriteRes;
261267 defm : X86WriteRes;
262268 defm : X86WriteRes;
263269 defm : X86WriteRes;
264270 defm : X86WriteRes;
271 defm : X86WriteRes;
272 defm : X86WriteRes;
265273 defm : X86WriteRes;
266274 defm : X86WriteRes;
267275 defm : X86WriteRes;
604612 def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
605613 "KMOV(B|D|Q|W)mk",
606614 "MMX_MOVD64mr",
607 "MOVNTI_64mr",
608 "MOVNTImr",
609615 "ST_FP(32|64|80)m",
610616 "VMOV(H|L)(PD|PS)Z128mr(b?)",
611617 "(V?)MOV(H|L)(PD|PS)mr",
8989 }
9090
9191 // Loads, stores, and moves, not folded with other operations.
92 def WriteLoad : SchedWrite;
93 def WriteStore : SchedWrite;
94 def WriteMove : SchedWrite;
92 def WriteLoad : SchedWrite;
93 def WriteStore : SchedWrite;
94 def WriteStoreNT : SchedWrite;
95 def WriteMove : SchedWrite;
9596
9697 // Arithmetic.
9798 defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
144145 def WriteFStore : SchedWrite;
145146 def WriteFStoreX : SchedWrite;
146147 def WriteFStoreY : SchedWrite;
148 def WriteFStoreNT : SchedWrite;
149 def WriteFStoreNTX : SchedWrite;
150 def WriteFStoreNTY : SchedWrite;
147151 def WriteFMaskedStore : SchedWrite;
148152 def WriteFMaskedStoreY : SchedWrite;
149153 def WriteFMove : SchedWrite;
228232 def WriteVecLoad : SchedWrite;
229233 def WriteVecLoadX : SchedWrite;
230234 def WriteVecLoadY : SchedWrite;
235 def WriteVecLoadNT : SchedWrite;
236 def WriteVecLoadNTY : SchedWrite;
231237 def WriteVecMaskedLoad : SchedWrite;
232238 def WriteVecMaskedLoadY : SchedWrite;
233239 def WriteVecStore : SchedWrite;
234240 def WriteVecStoreX : SchedWrite;
235241 def WriteVecStoreY : SchedWrite;
242 def WriteVecStoreNT : SchedWrite;
243 def WriteVecStoreNTY : SchedWrite;
236244 def WriteVecMaskedStore : SchedWrite;
237245 def WriteVecMaskedStoreY : SchedWrite;
238246 def WriteVecMove : SchedWrite;
351359 : X86SchedWriteMoveLSWidths
352360 WriteFMoveLSY, WriteFMoveLSY>;
353361
362 def WriteFMoveLSNT
363 : X86SchedWriteMoveLS;
364 def WriteFMoveLSNTX
365 : X86SchedWriteMoveLS;
366 def WriteFMoveLSNTY
367 : X86SchedWriteMoveLS;
368 def SchedWriteFMoveLSNT
369 : X86SchedWriteMoveLSWidths
370 WriteFMoveLSNTY, WriteFMoveLSNTY>;
371
354372 def WriteVecMoveLS
355373 : X86SchedWriteMoveLS;
356374 def WriteVecMoveLSX
360378 def SchedWriteVecMoveLS
361379 : X86SchedWriteMoveLSWidths
362380 WriteVecMoveLSY, WriteVecMoveLSY>;
381
382 def WriteVecMoveLSNT
383 : X86SchedWriteMoveLS;
384 def WriteVecMoveLSNTX
385 : X86SchedWriteMoveLS;
386 def WriteVecMoveLSNTY
387 : X86SchedWriteMoveLS;
388 def SchedWriteVecMoveLSNT
389 : X86SchedWriteMoveLSWidths
390 WriteVecMoveLSNTY, WriteVecMoveLSNTY>;
363391
364392 // Vector width wrappers.
365393 def SchedWriteFAdd
143143 // Loads, stores, and moves, not folded with other operations.
144144 ////////////////////////////////////////////////////////////////////////////////
145145
146 def : WriteRes;
147 def : WriteRes;
148 def : WriteResMove, [AtomPort01]>;
146 def : WriteResLoad, [AtomPort0]>;
147 def : WriteRes;
148 def : WriteRes;
149 def : WriteRes;
149150
150151 // Treat misc copies as a move.
151152 def : InstRW<[WriteMove], (instrs COPY)>;
189190 def : WriteRes;
190191 def : WriteRes;
191192 def : WriteRes;
193 def : WriteRes;
194 def : WriteRes;
195 def : WriteRes;
192196 def : WriteRes;
193197 def : WriteRes;
194198
280284 def : WriteRes;
281285 def : WriteRes;
282286 def : WriteRes;
287 def : WriteRes;
288 def : WriteRes;
283289 def : WriteRes;
284290 def : WriteRes;
285291
286292 def : WriteRes;
287293 def : WriteRes;
288294 def : WriteRes;
295 def : WriteRes;
296 def : WriteRes;
289297 def : WriteRes;
290298 def : WriteRes;
291299
225225 // Loads, stores, and moves, not folded with other operations.
226226 ////////////////////////////////////////////////////////////////////////////////
227227
228 def : WriteRes { let Latency = 5; }
229 def : WriteRes;
230 def : WriteResMove, [JALU01]>;
228 def : WriteResLoad, [JLAGU]> { let Latency = 5; }
229 def : WriteRes;
230 def : WriteRes;
231 def : WriteRes;
231232
232233 // Load/store MXCSR.
233234 // FIXME: These are copy and pasted from WriteLoad/Store.
276277 defm : X86WriteRes;
277278 defm : X86WriteRes;
278279 defm : X86WriteRes;
280 defm : X86WriteRes;
281 defm : X86WriteRes;
282 defm : X86WriteRes;
279283 defm : X86WriteRes;
280284 defm : X86WriteRes;
281285
406410 defm : X86WriteRes;
407411 defm : X86WriteRes;
408412 defm : X86WriteRes;
413 defm : X86WriteRes;
414 defm : X86WriteRes;
409415 defm : X86WriteRes;
410416 defm : X86WriteRes;
411417
412418 defm : X86WriteRes;
413419 defm : X86WriteRes;
414420 defm : X86WriteRes;
421 defm : X86WriteRes;
422 defm : X86WriteRes;
415423 defm : X86WriteRes;
416424 defm : X86WriteRes;
417425
571579 def : InstRW<[JWriteVCVTYLd, ReadAfterLd], (instrs VCVTDQ2PDYrm, VCVTDQ2PSYrm,
572580 VCVTPS2DQYrm, VCVTTPS2DQYrm)>;
573581
574 def JWriteVMOVNTDQSt: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
575 let Latency = 2;
576 }
577 def : InstRW<[JWriteVMOVNTDQSt], (instrs MMX_MOVNTQmr, MOVNTDQmr, VMOVNTDQmr)>;
578
579 def JWriteVMOVNTDQYSt: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
580 let Latency = 2;
581 let ResourceCycles = [2, 2, 2];
582 }
583 def : InstRW<[JWriteVMOVNTDQYSt], (instrs VMOVNTDQYmr)>;
584
585 def JWriteMOVNTSt: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
586 let Latency = 3;
587 }
588 def : InstRW<[JWriteMOVNTSt], (instrs MOVNTPDmr, MOVNTPSmr, MOVNTSD, MOVNTSS, VMOVNTPDmr, VMOVNTPSmr)>;
589
590 def JWriteVMOVNTPYSt: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
591 let Latency = 3;
592 let ResourceCycles = [2, 2, 2];
593 }
594 def : InstRW<[JWriteVMOVNTPYSt], (instrs VMOVNTPDYmr, VMOVNTPSYmr)>;
595
596582 def JWriteVCVTPDY: SchedWriteRes<[JFPU1, JSTC, JFPX]> {
597583 let Latency = 6;
598584 let ResourceCycles = [2, 2, 4];
7878 // need an extra port cycle to recompute the address.
7979 def : WriteRes;
8080
81 def : WriteRes;
82 def : WriteRes { let Latency = 3; }
83 def : WriteRes;
84 def : WriteResZero, []>;
81 def : WriteResStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
82 def : WriteRes;
83 def : WriteRes { let Latency = 3; }
84 def : WriteRes;
85 def : WriteRes;
8586
8687 // Load/store MXCSR.
8788 // FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
140141 def : WriteRes;
141142 def : WriteRes;
142143 def : WriteRes;
144 def : WriteRes;
145 def : WriteRes;
146 def : WriteRes;
143147 def : WriteRes;
144148 def : WriteRes;
145149 def : WriteRes;
213217 def : WriteRes { let Latency = 3; }
214218 def : WriteRes { let Latency = 3; }
215219 def : WriteRes { let Latency = 3; }
220 def : WriteRes { let Latency = 3; }
221 def : WriteRes { let Latency = 3; }
216222 def : WriteRes { let Latency = 3; }
217223 def : WriteRes { let Latency = 3; }
218224 def : WriteRes;
219225 def : WriteRes;
220226 def : WriteRes;
227 def : WriteRes;
228 def : WriteRes;
221229 def : WriteRes;
222230 def : WriteRes;
223231 def : WriteRes;
142142 // operation in codegen
143143 def : WriteRes;
144144
145 def : WriteRes;
146 def : WriteRes;
147 def : WriteResLoad, [ZnAGU]> { let Latency = 8; }
145 def : WriteResStore, [ZnAGU]>;
146 def : WriteRes;
147 def : WriteRes;
148 def : WriteRes { let Latency = 8; }
148149
149150 def : WriteRes;
150151 def : WriteRes;
196197 defm : X86WriteRes;
197198 defm : X86WriteRes;
198199 defm : X86WriteRes;
200 defm : X86WriteRes;
201 defm : X86WriteRes;
202 defm : X86WriteRes;
199203 defm : X86WriteRes;
200204 defm : X86WriteRes;
201205 defm : X86WriteRes;
273277 defm : X86WriteRes;
274278 defm : X86WriteRes;
275279 defm : X86WriteRes;
280 defm : X86WriteRes;
281 defm : X86WriteRes;
276282 defm : X86WriteRes;
277283 defm : X86WriteRes;
278284 defm : X86WriteRes;
279285 defm : X86WriteRes;
280286 defm : X86WriteRes;
287 defm : X86WriteRes;
288 defm : X86WriteRes;
281289 defm : X86WriteRes;
282290 defm : X86WriteRes;
283291 defm : X86WriteRes;
13431351 }
13441352 def : InstRW<[ZnWriteINSERTQ], (instregex "INSERTQ")>;
13451353
1346 // MOVNTSS/MOVNTSD
1347 def ZnWriteMOVNT: SchedWriteRes<[ZnAGU,ZnFPU2]> {
1348 let Latency = 8;
1349 }
1350 def : InstRW<[ZnWriteMOVNT], (instregex "MOVNTS(S|D)")>;
1351
13521354 //-- SHA instructions --//
13531355 // SHA256MSG2
13541356 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;