llvm.org GIT mirror llvm / 5f7a8a4
GlobalISel: Allow shift amount to be a different type For AMDGPU the shift amount is never 64-bit, and this needs to use a 32-bit shift. X86 uses i8, but seemed to be hacking around this before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351882 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 1 year, 8 months ago
26 changed file(s) with 548 addition(s) and 493 deletion(s). Raw diff Collapse all Expand all
107107 unsigned TruncSrc;
108108 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
109109 LLT DstTy = MRI.getType(DstReg);
110 if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy}}) ||
111 isInstUnsupported({TargetOpcode::G_ASHR, {DstTy}}) ||
110 // Guess on the RHS shift amount type, which should be re-legalized if
111 // applicable.
112 if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy, DstTy}}) ||
113 isInstUnsupported({TargetOpcode::G_ASHR, {DstTy, DstTy}}) ||
112114 isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
113115 return false;
114116 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
103103 unsigned ExtOpcode);
104104
105105 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
106 /// Use by truncating the operand's type to \p NarrowTy using G_TRUNC, and
107 /// replacing the vreg of the operand in place.
108 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
109
110 /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
106111 /// Def by extending the operand's type to \p WideTy and truncating it back
107112 /// with the \p TruncOpcode, and replacing the vreg of the operand in place.
108113 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
665665 Query.Types[TypeIdx].getSizeInBits();
666666 },
667667 [=](const LegalityQuery &Query) {
668 LLT T = Query.Types[LargeTypeIdx];
668669 return std::make_pair(TypeIdx,
669 Query.Types[LargeTypeIdx].getElementType());
670 T.isVector() ? T.getElementType() : T);
670671 });
671672 }
672673
255255 // Generic left-shift.
256256 def G_SHL : GenericInstruction {
257257 let OutOperandList = (outs type0:$dst);
258 let InOperandList = (ins type0:$src1, type0:$src2);
258 let InOperandList = (ins type0:$src1, type1:$src2);
259259 let hasSideEffects = 0;
260260 }
261261
262262 // Generic logical right-shift.
263263 def G_LSHR : GenericInstruction {
264264 let OutOperandList = (outs type0:$dst);
265 let InOperandList = (ins type0:$src1, type0:$src2);
265 let InOperandList = (ins type0:$src1, type1:$src2);
266266 let hasSideEffects = 0;
267267 }
268268
269269 // Generic arithmetic right-shift.
270270 def G_ASHR : GenericInstruction {
271271 let OutOperandList = (outs type0:$dst);
272 let InOperandList = (ins type0:$src1, type0:$src2);
272 let InOperandList = (ins type0:$src1, type1:$src2);
273273 let hasSideEffects = 0;
274274 }
275275
281281 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
282282 unsigned TypeIdx,
283283 LLT NarrowTy) {
284 // FIXME: Don't know how to handle secondary types yet.
285 if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
286 return UnableToLegalize;
287
288284 MIRBuilder.setInstr(MI);
289285
290286 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
407403 return Legalized;
408404 }
409405 case TargetOpcode::G_INSERT: {
406 // FIXME: Don't know how to handle secondary types yet.
407 if (TypeIdx != 0)
408 return UnableToLegalize;
409
410410 // FIXME: add support for when SizeOp0 isn't an exact multiple of
411411 // NarrowSize.
412412 if (SizeOp0 % NarrowSize != 0)
658658 MI.eraseFromParent();
659659 return Legalized;
660660 }
661 case TargetOpcode::G_SHL:
662 case TargetOpcode::G_LSHR:
663 case TargetOpcode::G_ASHR: {
664 if (TypeIdx != 1)
665 return UnableToLegalize; // TODO
666 narrowScalarSrc(MI, NarrowTy, 2);
667 return Legalized;
668 }
661669 }
662670 }
663671
665673 unsigned OpIdx, unsigned ExtOpcode) {
666674 MachineOperand &MO = MI.getOperand(OpIdx);
667675 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
676 MO.setReg(ExtB->getOperand(0).getReg());
677 }
678
679 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
680 unsigned OpIdx) {
681 MachineOperand &MO = MI.getOperand(OpIdx);
682 auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
683 {MO.getReg()});
668684 MO.setReg(ExtB->getOperand(0).getReg());
669685 }
670686
765781 return Legalized;
766782
767783 case TargetOpcode::G_SHL:
768 Observer.changingInstr(MI);
769 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
770 // The "number of bits to shift" operand must preserve its value as an
771 // unsigned integer:
772 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
773 widenScalarDst(MI, WideTy);
784 Observer.changingInstr(MI);
785
786 if (TypeIdx == 0) {
787 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
788 widenScalarDst(MI, WideTy);
789 } else {
790 assert(TypeIdx == 1);
791 // The "number of bits to shift" operand must preserve its value as an
792 // unsigned integer:
793 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
794 }
795
774796 Observer.changedInstr(MI);
775797 return Legalized;
776798
784806 return Legalized;
785807
786808 case TargetOpcode::G_ASHR:
787 Observer.changingInstr(MI);
788 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
789 // The "number of bits to shift" operand must preserve its value as an
790 // unsigned integer:
791 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
792 widenScalarDst(MI, WideTy);
793 Observer.changedInstr(MI);
794 return Legalized;
795
809 case TargetOpcode::G_LSHR:
810 Observer.changingInstr(MI);
811
812 if (TypeIdx == 0) {
813 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
814 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
815
816 widenScalarSrc(MI, WideTy, 1, CvtOp);
817 widenScalarDst(MI, WideTy);
818 } else {
819 assert(TypeIdx == 1);
820 // The "number of bits to shift" operand must preserve its value as an
821 // unsigned integer:
822 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
823 }
824
825 Observer.changedInstr(MI);
826 return Legalized;
796827 case TargetOpcode::G_UDIV:
797828 case TargetOpcode::G_UREM:
798 case TargetOpcode::G_LSHR:
799829 Observer.changingInstr(MI);
800830 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
801831 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
7272 .clampScalar(0, s16, s64)
7373 .widenScalarToNextPow2(0);
7474
75 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL})
75 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
7676 .legalFor({s32, s64, v2s32, v4s32, v2s64})
7777 .clampScalar(0, s32, s64)
7878 .widenScalarToNextPow2(0)
8080 .clampNumElements(0, v2s64, v2s64)
8181 .moreElementsToNextPow2(0);
8282
83 getActionDefinitionsBuilder(G_SHL)
84 .legalFor({{s32, s32}, {s64, s64},
85 {v2s32, v2s32}, {v4s32, v4s32}, {v2s64, v2s64}})
86 .clampScalar(0, s32, s64)
87 .widenScalarToNextPow2(0)
88 .clampNumElements(0, v2s32, v4s32)
89 .clampNumElements(0, v2s64, v2s64)
90 .moreElementsToNextPow2(0)
91 .minScalarSameAs(1, 0);
92
8393 getActionDefinitionsBuilder(G_GEP)
8494 .legalFor({{p0, s64}})
8595 .clampScalar(1, s64, s64);
8696
8797 getActionDefinitionsBuilder(G_PTR_MASK).legalFor({p0});
8898
89 getActionDefinitionsBuilder({G_LSHR, G_ASHR, G_SDIV, G_UDIV})
99 getActionDefinitionsBuilder({G_SDIV, G_UDIV})
90100 .legalFor({s32, s64})
91101 .clampScalar(0, s32, s64)
92102 .widenScalarToNextPow2(0);
103
104 getActionDefinitionsBuilder({G_LSHR, G_ASHR})
105 .legalFor({{s32, s32}, {s64, s64}})
106 .clampScalar(0, s32, s64)
107 .minScalarSameAs(1, 0);
93108
94109 getActionDefinitionsBuilder({G_SREM, G_UREM})
95110 .lowerFor({s1, s8, s16, s32, s64});
9797
9898 setAction({G_ADD, S32}, Legal);
9999 setAction({G_ASHR, S32}, Legal);
100 setAction({G_ASHR, 1, S32}, Legal);
100101 setAction({G_SUB, S32}, Legal);
101102 setAction({G_MUL, S32}, Legal);
102103
273274 .clampScalar(0, S32, S64);
274275
275276 setAction({G_SHL, S32}, Legal);
277 setAction({G_SHL, 1, S32}, Legal);
276278
277279
278280 // FIXME: When RegBankSelect inserts copies, it will only create new
134134 setAction({Op, s32}, Libcall);
135135 }
136136
137 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}).legalFor({s32});
137 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
138 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
139
140 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
141 .legalFor({{s32, s32}})
142 .clampScalar(1, s32, s32);
138143
139144 if (ST.hasV5TOps()) {
140145 getActionDefinitionsBuilder(G_CTLZ)
4242 .legalFor({s32})
4343 .clampScalar(0, s32, s32);
4444
45 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
46 .legalFor({s32});
47
4845 getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
4946 .legalFor({s32})
5047 .minScalar(0, s32)
5148 .libcallFor({s64});
49
50 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
51 .legalFor({s32, s32})
52 .minScalar(1, s32);
5253
5354 getActionDefinitionsBuilder(G_ICMP)
5455 .legalFor({{s32, s32}})
15281528
15291529 const static struct ShiftEntry {
15301530 unsigned SizeInBits;
1531 unsigned CReg;
15321531 unsigned OpLSHR;
15331532 unsigned OpASHR;
15341533 unsigned OpSHL;
15351534 } OpTable[] = {
1536 {8, X86::CL, X86::SHR8rCL, X86::SAR8rCL, X86::SHL8rCL}, // i8
1537 {16, X86::CX, X86::SHR16rCL, X86::SAR16rCL, X86::SHL16rCL}, // i16
1538 {32, X86::ECX, X86::SHR32rCL, X86::SAR32rCL, X86::SHL32rCL}, // i32
1539 {64, X86::RCX, X86::SHR64rCL, X86::SAR64rCL, X86::SHL64rCL} // i64
1535 {8, X86::SHR8rCL, X86::SAR8rCL, X86::SHL8rCL}, // i8
1536 {16, X86::SHR16rCL, X86::SAR16rCL, X86::SHL16rCL}, // i16
1537 {32, X86::SHR32rCL, X86::SAR32rCL, X86::SHL32rCL}, // i32
1538 {64, X86::SHR64rCL, X86::SAR64rCL, X86::SHL64rCL} // i64
15401539 };
15411540
15421541 if (DstRB.getID() != X86::GPRRegBankID)
15491548 if (ShiftEntryIt == std::end(OpTable))
15501549 return false;
15511550
1552 unsigned CReg = ShiftEntryIt->CReg;
15531551 unsigned Opcode = 0;
15541552 switch (I.getOpcode()) {
15551553 case TargetOpcode::G_SHL:
15681566 unsigned Op0Reg = I.getOperand(1).getReg();
15691567 unsigned Op1Reg = I.getOperand(2).getReg();
15701568
1569 assert(MRI.getType(Op1Reg).getSizeInBits() == 8);
1570
15711571 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
1572 ShiftEntryIt->CReg)
1573 .addReg(Op1Reg);
1574
1575 // The shift instruction uses X86::CL. If we defined a super-register
1576 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1577 if (CReg != X86::CL)
1578 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::KILL),
1579 X86::CL)
1580 .addReg(CReg, RegState::Kill);
1572 X86::CL)
1573 .addReg(Op1Reg);
15811574
15821575 MachineInstr &ShiftInst =
15831576 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
132132
133133 // Shifts and SDIV
134134 getActionDefinitionsBuilder(
135 {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM})
136 .legalFor({s8, s16, s32})
137 .clampScalar(0, s8, s32);
135 {G_SDIV, G_SREM, G_UDIV, G_UREM})
136 .legalFor({s8, s16, s32})
137 .clampScalar(0, s8, s32);
138
139 getActionDefinitionsBuilder(
140 {G_SHL, G_LSHR, G_ASHR})
141 .legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
142 .clampScalar(0, s8, s32)
143 .clampScalar(1, s8, s8);
138144 }
139145
140146 // Control-flow
234240 .clampScalar(1, s32, s64)
235241 .widenScalarToNextPow2(1);
236242
237 // Shifts and SDIV
243 // Divisions
238244 getActionDefinitionsBuilder(
239 {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM})
245 {G_SDIV, G_SREM, G_UDIV, G_UREM})
240246 .legalFor({s8, s16, s32, s64})
241247 .clampScalar(0, s8, s64);
248
249 // Shifts
250 getActionDefinitionsBuilder(
251 {G_SHL, G_LSHR, G_ASHR})
252 .legalFor({{s8, s8}, {s16, s8}, {s32, s8}, {s64, s8}})
253 .clampScalar(0, s8, s64)
254 .clampScalar(1, s8, s8);
242255
243256 // Merge/Unmerge
244257 setAction({G_MERGE_VALUES, s128}, Legal);
172172 case TargetOpcode::G_ADD:
173173 case TargetOpcode::G_SUB:
174174 case TargetOpcode::G_MUL:
175 case TargetOpcode::G_SHL:
176 case TargetOpcode::G_LSHR:
177 case TargetOpcode::G_ASHR:
178175 return getSameOperandsMapping(MI, false);
179 break;
180176 case TargetOpcode::G_FADD:
181177 case TargetOpcode::G_FSUB:
182178 case TargetOpcode::G_FMUL:
183179 case TargetOpcode::G_FDIV:
184180 return getSameOperandsMapping(MI, true);
185 break;
181 case TargetOpcode::G_SHL:
182 case TargetOpcode::G_LSHR:
183 case TargetOpcode::G_ASHR: {
184 const MachineFunction &MF = *MI.getParent()->getParent();
185 const MachineRegisterInfo &MRI = MF.getRegInfo();
186
187 unsigned NumOperands = MI.getNumOperands();
188 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
189
190 auto Mapping = getValueMapping(getPartialMappingIdx(Ty, false), 3);
191 return getInstructionMapping(DefaultMappingID, 1, Mapping, NumOperands);
192
193 }
186194 default:
187195 break;
188196 }
88 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
99 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
1010 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
11 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
12 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
11 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
12 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
1313 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
1414 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
1515 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
16 ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]]
16 ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
1717 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
1818 ; CHECK: $w0 = COPY [[COPY2]](s32)
1919 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
2222 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
2323 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
2424 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
25 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND2]]
25 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND2]](s32)
2626 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
2727 ; CHECK: $w0 = COPY [[COPY3]](s32)
2828 ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
2929 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
3030 ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
3131 ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C4]]
32 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[AND3]]
32 ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[AND3]](s32)
3333 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
3434 ; CHECK: $w0 = COPY [[COPY4]](s32)
3535 %0:_(s64) = COPY $x0
4747 $w0 = COPY %9(s32)
4848
4949 ...
50 ---
51 name: test_shl_i64_i32
52 body: |
53 bb.0:
54 ; CHECK-LABEL: name: test_shl_i64_i32
55 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
56 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
57 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
58 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[ZEXT]](s64)
59 ; CHECK: $x0 = COPY [[SHL]](s64)
60 %0:_(s64) = COPY $x0
61 %1:_(s32) = COPY $w1
62 %2:_(s64) = G_SHL %0, %1
63 $x0 = COPY %2(s64)
64
65 ...
66 ---
67 name: test_ashr_i64_i32
68 body: |
69 bb.0:
70 ; CHECK-LABEL: name: test_ashr_i64_i32
71 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
72 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
73 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
74 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[ZEXT]](s64)
75 ; CHECK: $x0 = COPY [[ASHR]](s64)
76 %0:_(s64) = COPY $x0
77 %1:_(s32) = COPY $w1
78 %2:_(s64) = G_ASHR %0, %1
79 $x0 = COPY %2(s64)
80
81 ...
82 ---
83 name: test_lshr_i64_i32
84 body: |
85 bb.0:
86 ; CHECK-LABEL: name: test_lshr_i64_i32
87 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
88 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
89 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
90 ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[ZEXT]](s64)
91 ; CHECK: $x0 = COPY [[LSHR]](s64)
92 %0:_(s64) = COPY $x0
93 %1:_(s32) = COPY $w1
94 %2:_(s64) = G_LSHR %0, %1
95 $x0 = COPY %2(s64)
96
97 ...
2525 ; CHECK-LABEL: name: test_implicit_def_s3
2626 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 61
2727 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
28 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[DEF]], [[C]]
29 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
28 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[DEF]], [[C]](s64)
29 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
3030 ; CHECK: $x0 = COPY [[ASHR]](s64)
3131 %0:_(s3) = G_IMPLICIT_DEF
3232 %1:_(s64) = G_SEXT %0
179179 # DEBUG-NEXT: G_ZEXT (opcode {{[0-9]+}}): 2 type indices
180180 # DEBUG: .. the first uncovered type index: 2, OK
181181 #
182 # DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 1 type index
183 # DEBUG: .. the first uncovered type index: 1, OK
184 #
185 # DEBUG-NEXT: G_LSHR (opcode {{[0-9]+}}): 1 type index
186 # DEBUG: .. the first uncovered type index: 1, OK
187 #
188 # DEBUG-NEXT: G_ASHR (opcode {{[0-9]+}}): 1 type index
189 # DEBUG: .. the first uncovered type index: 1, OK
182 # DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 2 type indices
183 # DEBUG:.. type index coverage check SKIPPED: user-defined predicate detected
184 #
185 # DEBUG-NEXT: G_LSHR (opcode {{[0-9]+}}): 2 type indices
186 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
187 #
188 # DEBUG-NEXT: G_ASHR (opcode {{[0-9]+}}): 2 type indices
189 # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
190190 #
191191 # DEBUG-NEXT: G_ICMP (opcode {{[0-9]+}}): 2 type indices
192192 # DEBUG: .. the first uncovered type index: 2, OK
55 ; X64: # %bb.0:
66 ; X64-NEXT: movq %rdi, %rax
77 ; X64-NEXT: movq %rsi, %rcx
8 ; X64-NEXT: # kill: def $cl killed $rcx
8 ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
99 ; X64-NEXT: sarq %cl, %rax
1010 ; X64-NEXT: retq
1111 %res = ashr i64 %arg1, %arg2
1717 ; X64: # %bb.0:
1818 ; X64-NEXT: movq %rdi, %rax
1919 ; X64-NEXT: movq $5, %rcx
20 ; X64-NEXT: # kill: def $cl killed $rcx
2120 ; X64-NEXT: sarq %cl, %rax
2221 ; X64-NEXT: retq
2322 %res = ashr i64 %arg1, 5
2928 ; X64: # %bb.0:
3029 ; X64-NEXT: movq %rdi, %rax
3130 ; X64-NEXT: movq $1, %rcx
32 ; X64-NEXT: # kill: def $cl killed $rcx
3331 ; X64-NEXT: sarq %cl, %rax
3432 ; X64-NEXT: retq
3533 %res = ashr i64 %arg1, 1
4139 ; X64: # %bb.0:
4240 ; X64-NEXT: movl %edi, %eax
4341 ; X64-NEXT: movl %esi, %ecx
44 ; X64-NEXT: # kill: def $cl killed $ecx
42 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
4543 ; X64-NEXT: sarl %cl, %eax
4644 ; X64-NEXT: retq
4745 %res = ashr i32 %arg1, %arg2
5351 ; X64: # %bb.0:
5452 ; X64-NEXT: movl %edi, %eax
5553 ; X64-NEXT: movl $5, %ecx
56 ; X64-NEXT: # kill: def $cl killed $ecx
5754 ; X64-NEXT: sarl %cl, %eax
5855 ; X64-NEXT: retq
5956 %res = ashr i32 %arg1, 5
6562 ; X64: # %bb.0:
6663 ; X64-NEXT: movl %edi, %eax
6764 ; X64-NEXT: movl $1, %ecx
68 ; X64-NEXT: # kill: def $cl killed $ecx
6965 ; X64-NEXT: sarl %cl, %eax
7066 ; X64-NEXT: retq
7167 %res = ashr i32 %arg1, 1
7773 ; X64: # %bb.0:
7874 ; X64-NEXT: movl %edi, %eax
7975 ; X64-NEXT: movl %esi, %ecx
80 ; X64-NEXT: # kill: def $cx killed $cx killed $ecx
81 ; X64-NEXT: # kill: def $cl killed $cx
76 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
8277 ; X64-NEXT: sarw %cl, %ax
8378 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
8479 ; X64-NEXT: retq
9388 ; X64: # %bb.0:
9489 ; X64-NEXT: movl %edi, %eax
9590 ; X64-NEXT: movw $5, %cx
96 ; X64-NEXT: # kill: def $cl killed $cx
9791 ; X64-NEXT: sarw %cl, %ax
9892 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
9993 ; X64-NEXT: retq
107101 ; X64: # %bb.0:
108102 ; X64-NEXT: movl %edi, %eax
109103 ; X64-NEXT: movw $1, %cx
110 ; X64-NEXT: # kill: def $cl killed $cx
111104 ; X64-NEXT: sarw %cl, %ax
112105 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
113106 ; X64-NEXT: retq
1818 ; X64: # %bb.0:
1919 ; X64-NEXT: movl %edi, %eax
2020 ; X64-NEXT: movq $56, %rcx
21 ; X64-NEXT: # kill: def $cl killed $rcx
2221 ; X64-NEXT: shlq %cl, %rax
2322 ; X64-NEXT: movq $56, %rcx
24 ; X64-NEXT: # kill: def $cl killed $rcx
2523 ; X64-NEXT: sarq %cl, %rax
2624 ; X64-NEXT: retq
2725 %r = sext i8 %val to i64
3331 ; X64: # %bb.0:
3432 ; X64-NEXT: movl %edi, %eax
3533 ; X64-NEXT: movq $48, %rcx
36 ; X64-NEXT: # kill: def $cl killed $rcx
3734 ; X64-NEXT: shlq %cl, %rax
3835 ; X64-NEXT: movq $48, %rcx
39 ; X64-NEXT: # kill: def $cl killed $rcx
4036 ; X64-NEXT: sarq %cl, %rax
4137 ; X64-NEXT: retq
4238 %r = sext i16 %val to i64
8989 ; X64: # %bb.0:
9090 ; X64-NEXT: movl %edi, %eax
9191 ; X64-NEXT: movl $24, %ecx
92 ; X64-NEXT: # kill: def $cl killed $ecx
9392 ; X64-NEXT: shll %cl, %eax
9493 ; X64-NEXT: movl $24, %ecx
95 ; X64-NEXT: # kill: def $cl killed $ecx
9694 ; X64-NEXT: sarl %cl, %eax
9795 ; X64-NEXT: retq
9896 ;
109107 ; X64: # %bb.0:
110108 ; X64-NEXT: movl %edi, %eax
111109 ; X64-NEXT: movl $16, %ecx
112 ; X64-NEXT: # kill: def $cl killed $ecx
113110 ; X64-NEXT: shll %cl, %eax
114111 ; X64-NEXT: movl $16, %ecx
115 ; X64-NEXT: # kill: def $cl killed $ecx
116112 ; X64-NEXT: sarl %cl, %eax
117113 ; X64-NEXT: retq
118114 ;
77 ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
88 ; X64_GISEL-NEXT: movq $4, %rax
99 ; X64_GISEL-NEXT: movq $56, %rcx
10 ; X64_GISEL-NEXT: # kill: def $cl killed $rcx
1110 ; X64_GISEL-NEXT: shlq %cl, %rsi
1211 ; X64_GISEL-NEXT: movq $56, %rcx
13 ; X64_GISEL-NEXT: # kill: def $cl killed $rcx
1412 ; X64_GISEL-NEXT: sarq %cl, %rsi
1513 ; X64_GISEL-NEXT: imulq %rax, %rsi
1614 ; X64_GISEL-NEXT: leaq (%rdi,%rsi), %rax
4745 ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
4846 ; X64_GISEL-NEXT: movq $4, %rax
4947 ; X64_GISEL-NEXT: movq $48, %rcx
50 ; X64_GISEL-NEXT: # kill: def $cl killed $rcx
5148 ; X64_GISEL-NEXT: shlq %cl, %rsi
5249 ; X64_GISEL-NEXT: movq $48, %rcx
53 ; X64_GISEL-NEXT: # kill: def $cl killed $rcx
5450 ; X64_GISEL-NEXT: sarq %cl, %rsi
5551 ; X64_GISEL-NEXT: imulq %rax, %rsi
5652 ; X64_GISEL-NEXT: leaq (%rdi,%rsi), %rax
7878 ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
7979 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
8080 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
81 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]]
82 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
81 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
82 ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s8)
83 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
84 ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s8)
8385 ; CHECK: $rax = COPY [[ASHR]](s64)
8486 ; CHECK: RET 0, implicit $rax
8587 %0(s8) = COPY $dil
55 ; X64: # %bb.0:
66 ; X64-NEXT: movq %rdi, %rax
77 ; X64-NEXT: movq %rsi, %rcx
8 ; X64-NEXT: # kill: def $cl killed $rcx
8 ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
99 ; X64-NEXT: shrq %cl, %rax
1010 ; X64-NEXT: retq
1111 %res = lshr i64 %arg1, %arg2
1717 ; X64: # %bb.0:
1818 ; X64-NEXT: movq %rdi, %rax
1919 ; X64-NEXT: movq $5, %rcx
20 ; X64-NEXT: # kill: def $cl killed $rcx
2120 ; X64-NEXT: shrq %cl, %rax
2221 ; X64-NEXT: retq
2322 %res = lshr i64 %arg1, 5
2928 ; X64: # %bb.0:
3029 ; X64-NEXT: movq %rdi, %rax
3130 ; X64-NEXT: movq $1, %rcx
32 ; X64-NEXT: # kill: def $cl killed $rcx
3331 ; X64-NEXT: shrq %cl, %rax
3432 ; X64-NEXT: retq
3533 %res = lshr i64 %arg1, 1
4139 ; X64: # %bb.0:
4240 ; X64-NEXT: movl %edi, %eax
4341 ; X64-NEXT: movl %esi, %ecx
44 ; X64-NEXT: # kill: def $cl killed $ecx
42 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
4543 ; X64-NEXT: shrl %cl, %eax
4644 ; X64-NEXT: retq
4745 %res = lshr i32 %arg1, %arg2
5351 ; X64: # %bb.0:
5452 ; X64-NEXT: movl %edi, %eax
5553 ; X64-NEXT: movl $5, %ecx
56 ; X64-NEXT: # kill: def $cl killed $ecx
5754 ; X64-NEXT: shrl %cl, %eax
5855 ; X64-NEXT: retq
5956 %res = lshr i32 %arg1, 5
6562 ; X64: # %bb.0:
6663 ; X64-NEXT: movl %edi, %eax
6764 ; X64-NEXT: movl $1, %ecx
68 ; X64-NEXT: # kill: def $cl killed $ecx
6965 ; X64-NEXT: shrl %cl, %eax
7066 ; X64-NEXT: retq
7167 %res = lshr i32 %arg1, 1
7773 ; X64: # %bb.0:
7874 ; X64-NEXT: movl %edi, %eax
7975 ; X64-NEXT: movl %esi, %ecx
80 ; X64-NEXT: # kill: def $cx killed $cx killed $ecx
81 ; X64-NEXT: # kill: def $cl killed $cx
76 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
8277 ; X64-NEXT: shrw %cl, %ax
8378 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
8479 ; X64-NEXT: retq
9388 ; X64: # %bb.0:
9489 ; X64-NEXT: movl %edi, %eax
9590 ; X64-NEXT: movw $5, %cx
96 ; X64-NEXT: # kill: def $cl killed $cx
9791 ; X64-NEXT: shrw %cl, %ax
9892 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
9993 ; X64-NEXT: retq
107101 ; X64: # %bb.0:
108102 ; X64-NEXT: movl %edi, %eax
109103 ; X64-NEXT: movw $1, %cx
110 ; X64-NEXT: # kill: def $cl killed $cx
111104 ; X64-NEXT: shrw %cl, %ax
112105 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
113106 ; X64-NEXT: retq
7979 - { id: 0, class: gpr, preferred-register: '' }
8080 - { id: 1, class: gpr, preferred-register: '' }
8181 - { id: 2, class: gpr, preferred-register: '' }
82 - { id: 3, class: gpr, preferred-register: '' }
8283 liveins:
8384 fixedStack:
8485 stack:
9091 ; ALL-LABEL: name: test_ashr_i64
9192 ; ALL: liveins: $rdi, $rsi
9293 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
93 ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
94 ; ALL: $rcx = COPY [[COPY1]]
95 ; ALL: $cl = KILL killed $rcx
94 ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
95 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
96 ; ALL: $cl = COPY [[COPY2]]
9697 ; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
9798 ; ALL: $rax = COPY [[SAR64rCL]]
9899 ; ALL: RET 0, implicit $rax
99100 %0(s64) = COPY $rdi
100101 %1(s64) = COPY $rsi
102 %2(s8) = G_TRUNC %1
103 %3(s64) = G_ASHR %0, %2
104 $rax = COPY %3(s64)
105 RET 0, implicit $rax
106
107 ...
108 ---
109 name: test_ashr_i64_imm
110 alignment: 4
111 legalized: true
112 regBankSelected: true
113 tracksRegLiveness: true
114 registers:
115 - { id: 0, class: gpr, preferred-register: '' }
116 - { id: 1, class: gpr, preferred-register: '' }
117 - { id: 2, class: gpr, preferred-register: '' }
118 liveins:
119 fixedStack:
120 stack:
121 constants:
122 body: |
123 bb.1 (%ir-block.0):
124 liveins: $rdi
125
126 ; ALL-LABEL: name: test_ashr_i64_imm
127 ; ALL: liveins: $rdi
128 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
129 ; ALL: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def $eflags
130 ; ALL: $rax = COPY [[SAR64ri]]
131 ; ALL: RET 0, implicit $rax
132 %0(s64) = COPY $rdi
133 %1(s8) = G_CONSTANT i64 5
101134 %2(s64) = G_ASHR %0, %1
102135 $rax = COPY %2(s64)
103136 RET 0, implicit $rax
104137
105138 ...
106139 ---
107 name: test_ashr_i64_imm
140 name: test_ashr_i64_imm1
108141 alignment: 4
109142 legalized: true
110143 regBankSelected: true
121154 bb.1 (%ir-block.0):
122155 liveins: $rdi
123156
124 ; ALL-LABEL: name: test_ashr_i64_imm
157 ; ALL-LABEL: name: test_ashr_i64_imm1
125158 ; ALL: liveins: $rdi
126159 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
127 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 5
128 ; ALL: $rcx = COPY [[MOV64ri32_]]
129 ; ALL: $cl = KILL killed $rcx
130 ; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
131 ; ALL: $rax = COPY [[SAR64rCL]]
160 ; ALL: [[SAR64r1_:%[0-9]+]]:gr64 = SAR64r1 [[COPY]], implicit-def $eflags
161 ; ALL: $rax = COPY [[SAR64r1_]]
132162 ; ALL: RET 0, implicit $rax
133163 %0(s64) = COPY $rdi
134 %1(s64) = G_CONSTANT i64 5
164 %1(s8) = G_CONSTANT i64 1
135165 %2(s64) = G_ASHR %0, %1
136166 $rax = COPY %2(s64)
137167 RET 0, implicit $rax
138168
139169 ...
140170 ---
141 name: test_ashr_i64_imm1
142 alignment: 4
143 legalized: true
144 regBankSelected: true
145 tracksRegLiveness: true
146 registers:
147 - { id: 0, class: gpr, preferred-register: '' }
148 - { id: 1, class: gpr, preferred-register: '' }
149 - { id: 2, class: gpr, preferred-register: '' }
150 liveins:
151 fixedStack:
152 stack:
153 constants:
154 body: |
155 bb.1 (%ir-block.0):
156 liveins: $rdi
157
158 ; ALL-LABEL: name: test_ashr_i64_imm1
159 ; ALL: liveins: $rdi
160 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
161 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1
162 ; ALL: $rcx = COPY [[MOV64ri32_]]
163 ; ALL: $cl = KILL killed $rcx
164 ; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
165 ; ALL: $rax = COPY [[SAR64rCL]]
166 ; ALL: RET 0, implicit $rax
167 %0(s64) = COPY $rdi
168 %1(s64) = G_CONSTANT i64 1
169 %2(s64) = G_ASHR %0, %1
170 $rax = COPY %2(s64)
171 RET 0, implicit $rax
172
173 ...
174 ---
175171 name: test_ashr_i32
176172 alignment: 4
177173 legalized: true
181177 - { id: 0, class: gpr, preferred-register: '' }
182178 - { id: 1, class: gpr, preferred-register: '' }
183179 - { id: 2, class: gpr, preferred-register: '' }
180 - { id: 3, class: gpr, preferred-register: '' }
184181 liveins:
185182 fixedStack:
186183 stack:
193190 ; ALL: liveins: $edi, $esi
194191 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
195192 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
196 ; ALL: $ecx = COPY [[COPY1]]
197 ; ALL: $cl = KILL killed $ecx
193 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
194 ; ALL: $cl = COPY [[COPY2]]
198195 ; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
199196 ; ALL: $eax = COPY [[SAR32rCL]]
200197 ; ALL: RET 0, implicit $eax
201198 %0(s32) = COPY $edi
202199 %1(s32) = COPY $esi
200 %2(s8) = G_TRUNC %1
201 %3(s32) = G_ASHR %0, %2
202 $eax = COPY %3(s32)
203 RET 0, implicit $eax
204
205 ...
206 ---
207 name: test_ashr_i32_imm
208 alignment: 4
209 legalized: true
210 regBankSelected: true
211 tracksRegLiveness: true
212 registers:
213 - { id: 0, class: gpr, preferred-register: '' }
214 - { id: 1, class: gpr, preferred-register: '' }
215 - { id: 2, class: gpr, preferred-register: '' }
216 liveins:
217 fixedStack:
218 stack:
219 constants:
220 body: |
221 bb.1 (%ir-block.0):
222 liveins: $edi
223
224 ; ALL-LABEL: name: test_ashr_i32_imm
225 ; ALL: liveins: $edi
226 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
227 ; ALL: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def $eflags
228 ; ALL: $eax = COPY [[SAR32ri]]
229 ; ALL: RET 0, implicit $eax
230 %0(s32) = COPY $edi
231 %1(s8) = G_CONSTANT i32 5
203232 %2(s32) = G_ASHR %0, %1
204233 $eax = COPY %2(s32)
205234 RET 0, implicit $eax
206235
207236 ...
208237 ---
209 name: test_ashr_i32_imm
210 alignment: 4
211 legalized: true
212 regBankSelected: true
213 tracksRegLiveness: true
214 registers:
215 - { id: 0, class: gpr, preferred-register: '' }
216 - { id: 1, class: gpr, preferred-register: '' }
217 - { id: 2, class: gpr, preferred-register: '' }
218 liveins:
219 fixedStack:
220 stack:
221 constants:
222 body: |
223 bb.1 (%ir-block.0):
224 liveins: $edi
225
226 ; ALL-LABEL: name: test_ashr_i32_imm
227 ; ALL: liveins: $edi
228 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
229 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 5
230 ; ALL: $ecx = COPY [[MOV32ri]]
231 ; ALL: $cl = KILL killed $ecx
232 ; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
233 ; ALL: $eax = COPY [[SAR32rCL]]
238 name: test_ashr_i32_imm1
239 alignment: 4
240 legalized: true
241 regBankSelected: true
242 tracksRegLiveness: true
243 registers:
244 - { id: 0, class: gpr, preferred-register: '' }
245 - { id: 1, class: gpr, preferred-register: '' }
246 - { id: 2, class: gpr, preferred-register: '' }
247 liveins:
248 fixedStack:
249 stack:
250 constants:
251 body: |
252 bb.1 (%ir-block.0):
253 liveins: $edi
254
255 ; ALL-LABEL: name: test_ashr_i32_imm1
256 ; ALL: liveins: $edi
257 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
258 ; ALL: [[SAR32r1_:%[0-9]+]]:gr32 = SAR32r1 [[COPY]], implicit-def $eflags
259 ; ALL: $eax = COPY [[SAR32r1_]]
234260 ; ALL: RET 0, implicit $eax
235261 %0(s32) = COPY $edi
236 %1(s32) = G_CONSTANT i32 5
262 %1(s8) = G_CONSTANT i32 1
237263 %2(s32) = G_ASHR %0, %1
238264 $eax = COPY %2(s32)
239265 RET 0, implicit $eax
240266
241267 ...
242268 ---
243 name: test_ashr_i32_imm1
244 alignment: 4
245 legalized: true
246 regBankSelected: true
247 tracksRegLiveness: true
248 registers:
249 - { id: 0, class: gpr, preferred-register: '' }
250 - { id: 1, class: gpr, preferred-register: '' }
251 - { id: 2, class: gpr, preferred-register: '' }
252 liveins:
253 fixedStack:
254 stack:
255 constants:
256 body: |
257 bb.1 (%ir-block.0):
258 liveins: $edi
259
260 ; ALL-LABEL: name: test_ashr_i32_imm1
261 ; ALL: liveins: $edi
262 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
263 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
264 ; ALL: $ecx = COPY [[MOV32ri]]
265 ; ALL: $cl = KILL killed $ecx
266 ; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
267 ; ALL: $eax = COPY [[SAR32rCL]]
268 ; ALL: RET 0, implicit $eax
269 %0(s32) = COPY $edi
270 %1(s32) = G_CONSTANT i32 1
271 %2(s32) = G_ASHR %0, %1
272 $eax = COPY %2(s32)
273 RET 0, implicit $eax
274
275 ...
276 ---
277269 name: test_ashr_i16
278270 alignment: 4
279271 legalized: true
298290 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
299291 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
300292 ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
301 ; ALL: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
302 ; ALL: $cx = COPY [[COPY3]]
303 ; ALL: $cl = KILL killed $cx
293 ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
294 ; ALL: $cl = COPY [[COPY3]]
304295 ; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def $eflags, implicit $cl
305296 ; ALL: $ax = COPY [[SAR16rCL]]
306297 ; ALL: RET 0, implicit $ax
307298 %0(s32) = COPY $edi
308299 %1(s32) = COPY $esi
309300 %2(s16) = G_TRUNC %0(s32)
310 %3(s16) = G_TRUNC %1(s32)
301 %3(s8) = G_TRUNC %1(s32)
311302 %4(s16) = G_ASHR %2, %3
312303 $ax = COPY %4(s16)
313304 RET 0, implicit $ax
335326 ; ALL-LABEL: name: test_ashr_i16_imm
336327 ; ALL: liveins: $edi
337328 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
338 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 5
339329 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
340 ; ALL: $cx = COPY [[MOV16ri]]
341 ; ALL: $cl = KILL killed $cx
342 ; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
343 ; ALL: $ax = COPY [[SAR16rCL]]
330 ; ALL: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def $eflags
331 ; ALL: $ax = COPY [[SAR16ri]]
344332 ; ALL: RET 0, implicit $ax
345333 %0(s32) = COPY $edi
346 %2(s16) = G_CONSTANT i16 5
334 %2(s8) = G_CONSTANT i16 5
347335 %1(s16) = G_TRUNC %0(s32)
348336 %3(s16) = G_ASHR %1, %2
349337 $ax = COPY %3(s16)
372360 ; ALL-LABEL: name: test_ashr_i16_imm1
373361 ; ALL: liveins: $edi
374362 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
375 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 1
376363 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
377 ; ALL: $cx = COPY [[MOV16ri]]
378 ; ALL: $cl = KILL killed $cx
379 ; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
380 ; ALL: $ax = COPY [[SAR16rCL]]
364 ; ALL: [[SAR16r1_:%[0-9]+]]:gr16 = SAR16r1 [[COPY1]], implicit-def $eflags
365 ; ALL: $ax = COPY [[SAR16r1_]]
381366 ; ALL: RET 0, implicit $ax
382367 %0(s32) = COPY $edi
383 %2(s16) = G_CONSTANT i16 1
368 %2(s8) = G_CONSTANT i16 1
384369 %1(s16) = G_TRUNC %0(s32)
385370 %3(s16) = G_ASHR %1, %2
386371 $ax = COPY %3(s16)
7979 - { id: 0, class: gpr, preferred-register: '' }
8080 - { id: 1, class: gpr, preferred-register: '' }
8181 - { id: 2, class: gpr, preferred-register: '' }
82 - { id: 3, class: gpr, preferred-register: '' }
8283 liveins:
8384 fixedStack:
8485 stack:
9091 ; ALL-LABEL: name: test_lshr_i64
9192 ; ALL: liveins: $rdi, $rsi
9293 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
93 ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
94 ; ALL: $rcx = COPY [[COPY1]]
95 ; ALL: $cl = KILL killed $rcx
94 ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
95 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
96 ; ALL: $cl = COPY [[COPY2]]
9697 ; ALL: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl
9798 ; ALL: $rax = COPY [[SHR64rCL]]
9899 ; ALL: RET 0, implicit $rax
99100 %0(s64) = COPY $rdi
100101 %1(s64) = COPY $rsi
102 %2(s8) = G_TRUNC %1
103 %3(s64) = G_LSHR %0, %2
104 $rax = COPY %3(s64)
105 RET 0, implicit $rax
106
107 ...
108 ---
109 name: test_lshr_i64_imm
110 alignment: 4
111 legalized: true
112 regBankSelected: true
113 tracksRegLiveness: true
114 registers:
115 - { id: 0, class: gpr, preferred-register: '' }
116 - { id: 1, class: gpr, preferred-register: '' }
117 - { id: 2, class: gpr, preferred-register: '' }
118 liveins:
119 fixedStack:
120 stack:
121 constants:
122 body: |
123 bb.1 (%ir-block.0):
124 liveins: $rdi
125
126 ; ALL-LABEL: name: test_lshr_i64_imm
127 ; ALL: liveins: $rdi
128 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
129 ; ALL: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def $eflags
130 ; ALL: $rax = COPY [[SHR64ri]]
131 ; ALL: RET 0, implicit $rax
132 %0(s64) = COPY $rdi
133 %1(s8) = G_CONSTANT i64 5
101134 %2(s64) = G_LSHR %0, %1
102135 $rax = COPY %2(s64)
103136 RET 0, implicit $rax
104137
105138 ...
106139 ---
107 name: test_lshr_i64_imm
140 name: test_lshr_i64_imm1
108141 alignment: 4
109142 legalized: true
110143 regBankSelected: true
121154 bb.1 (%ir-block.0):
122155 liveins: $rdi
123156
124 ; ALL-LABEL: name: test_lshr_i64_imm
157 ; ALL-LABEL: name: test_lshr_i64_imm1
125158 ; ALL: liveins: $rdi
126159 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
127 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 5
128 ; ALL: $rcx = COPY [[MOV64ri32_]]
129 ; ALL: $cl = KILL killed $rcx
130 ; ALL: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl
131 ; ALL: $rax = COPY [[SHR64rCL]]
160 ; ALL: [[SHR64r1_:%[0-9]+]]:gr64 = SHR64r1 [[COPY]], implicit-def $eflags
161 ; ALL: $rax = COPY [[SHR64r1_]]
132162 ; ALL: RET 0, implicit $rax
133163 %0(s64) = COPY $rdi
134 %1(s64) = G_CONSTANT i64 5
164 %1(s8) = G_CONSTANT i64 1
135165 %2(s64) = G_LSHR %0, %1
136166 $rax = COPY %2(s64)
137167 RET 0, implicit $rax
138168
139169 ...
140170 ---
141 name: test_lshr_i64_imm1
142 alignment: 4
143 legalized: true
144 regBankSelected: true
145 tracksRegLiveness: true
146 registers:
147 - { id: 0, class: gpr, preferred-register: '' }
148 - { id: 1, class: gpr, preferred-register: '' }
149 - { id: 2, class: gpr, preferred-register: '' }
150 liveins:
151 fixedStack:
152 stack:
153 constants:
154 body: |
155 bb.1 (%ir-block.0):
156 liveins: $rdi
157
158 ; ALL-LABEL: name: test_lshr_i64_imm1
159 ; ALL: liveins: $rdi
160 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
161 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1
162 ; ALL: $rcx = COPY [[MOV64ri32_]]
163 ; ALL: $cl = KILL killed $rcx
164 ; ALL: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl
165 ; ALL: $rax = COPY [[SHR64rCL]]
166 ; ALL: RET 0, implicit $rax
167 %0(s64) = COPY $rdi
168 %1(s64) = G_CONSTANT i64 1
169 %2(s64) = G_LSHR %0, %1
170 $rax = COPY %2(s64)
171 RET 0, implicit $rax
172
173 ...
174 ---
175171 name: test_lshr_i32
176172 alignment: 4
177173 legalized: true
181177 - { id: 0, class: gpr, preferred-register: '' }
182178 - { id: 1, class: gpr, preferred-register: '' }
183179 - { id: 2, class: gpr, preferred-register: '' }
180 - { id: 3, class: gpr, preferred-register: '' }
184181 liveins:
185182 fixedStack:
186183 stack:
193190 ; ALL: liveins: $edi, $esi
194191 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
195192 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
196 ; ALL: $ecx = COPY [[COPY1]]
197 ; ALL: $cl = KILL killed $ecx
193 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
194 ; ALL: $cl = COPY [[COPY2]]
198195 ; ALL: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def $eflags, implicit $cl
199196 ; ALL: $eax = COPY [[SHR32rCL]]
200197 ; ALL: RET 0, implicit $eax
201198 %0(s32) = COPY $edi
202199 %1(s32) = COPY $esi
200 %2(s8) = G_TRUNC %1
201 %3(s32) = G_LSHR %0, %2
202 $eax = COPY %3(s32)
203 RET 0, implicit $eax
204
205 ...
206 ---
207 name: test_lshr_i32_imm
208 alignment: 4
209 legalized: true
210 regBankSelected: true
211 tracksRegLiveness: true
212 registers:
213 - { id: 0, class: gpr, preferred-register: '' }
214 - { id: 1, class: gpr, preferred-register: '' }
215 - { id: 2, class: gpr, preferred-register: '' }
216 liveins:
217 fixedStack:
218 stack:
219 constants:
220 body: |
221 bb.1 (%ir-block.0):
222 liveins: $edi
223
224 ; ALL-LABEL: name: test_lshr_i32_imm
225 ; ALL: liveins: $edi
226 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
227 ; ALL: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def $eflags
228 ; ALL: $eax = COPY [[SHR32ri]]
229 ; ALL: RET 0, implicit $eax
230 %0(s32) = COPY $edi
231 %1(s8) = G_CONSTANT i32 5
203232 %2(s32) = G_LSHR %0, %1
204233 $eax = COPY %2(s32)
205234 RET 0, implicit $eax
206235
207236 ...
208237 ---
209 name: test_lshr_i32_imm
210 alignment: 4
211 legalized: true
212 regBankSelected: true
213 tracksRegLiveness: true
214 registers:
215 - { id: 0, class: gpr, preferred-register: '' }
216 - { id: 1, class: gpr, preferred-register: '' }
217 - { id: 2, class: gpr, preferred-register: '' }
218 liveins:
219 fixedStack:
220 stack:
221 constants:
222 body: |
223 bb.1 (%ir-block.0):
224 liveins: $edi
225
226 ; ALL-LABEL: name: test_lshr_i32_imm
227 ; ALL: liveins: $edi
228 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
229 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 5
230 ; ALL: $ecx = COPY [[MOV32ri]]
231 ; ALL: $cl = KILL killed $ecx
232 ; ALL: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def $eflags, implicit $cl
233 ; ALL: $eax = COPY [[SHR32rCL]]
238 name: test_lshr_i32_imm1
239 alignment: 4
240 legalized: true
241 regBankSelected: true
242 tracksRegLiveness: true
243 registers:
244 - { id: 0, class: gpr, preferred-register: '' }
245 - { id: 1, class: gpr, preferred-register: '' }
246 - { id: 2, class: gpr, preferred-register: '' }
247 liveins:
248 fixedStack:
249 stack:
250 constants:
251 body: |
252 bb.1 (%ir-block.0):
253 liveins: $edi
254
255 ; ALL-LABEL: name: test_lshr_i32_imm1
256 ; ALL: liveins: $edi
257 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
258 ; ALL: [[SHR32r1_:%[0-9]+]]:gr32 = SHR32r1 [[COPY]], implicit-def $eflags
259 ; ALL: $eax = COPY [[SHR32r1_]]
234260 ; ALL: RET 0, implicit $eax
235261 %0(s32) = COPY $edi
236 %1(s32) = G_CONSTANT i32 5
262 %1(s8) = G_CONSTANT i32 1
237263 %2(s32) = G_LSHR %0, %1
238264 $eax = COPY %2(s32)
239265 RET 0, implicit $eax
240266
241267 ...
242268 ---
243 name: test_lshr_i32_imm1
244 alignment: 4
245 legalized: true
246 regBankSelected: true
247 tracksRegLiveness: true
248 registers:
249 - { id: 0, class: gpr, preferred-register: '' }
250 - { id: 1, class: gpr, preferred-register: '' }
251 - { id: 2, class: gpr, preferred-register: '' }
252 liveins:
253 fixedStack:
254 stack:
255 constants:
256 body: |
257 bb.1 (%ir-block.0):
258 liveins: $edi
259
260 ; ALL-LABEL: name: test_lshr_i32_imm1
261 ; ALL: liveins: $edi
262 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
263 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
264 ; ALL: $ecx = COPY [[MOV32ri]]
265 ; ALL: $cl = KILL killed $ecx
266 ; ALL: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def $eflags, implicit $cl
267 ; ALL: $eax = COPY [[SHR32rCL]]
268 ; ALL: RET 0, implicit $eax
269 %0(s32) = COPY $edi
270 %1(s32) = G_CONSTANT i32 1
271 %2(s32) = G_LSHR %0, %1
272 $eax = COPY %2(s32)
273 RET 0, implicit $eax
274
275 ...
276 ---
277269 name: test_lshr_i16
278270 alignment: 4
279271 legalized: true
298290 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
299291 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
300292 ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
301 ; ALL: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
302 ; ALL: $cx = COPY [[COPY3]]
303 ; ALL: $cl = KILL killed $cx
293 ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
294 ; ALL: $cl = COPY [[COPY3]]
304295 ; ALL: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY2]], implicit-def $eflags, implicit $cl
305296 ; ALL: $ax = COPY [[SHR16rCL]]
306297 ; ALL: RET 0, implicit $ax
307298 %0(s32) = COPY $edi
308299 %1(s32) = COPY $esi
309300 %2(s16) = G_TRUNC %0(s32)
310 %3(s16) = G_TRUNC %1(s32)
301 %3(s8) = G_TRUNC %1(s32)
311302 %4(s16) = G_LSHR %2, %3
312303 $ax = COPY %4(s16)
313304 RET 0, implicit $ax
335326 ; ALL-LABEL: name: test_lshr_i16_imm
336327 ; ALL: liveins: $edi
337328 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
338 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 5
339329 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
340 ; ALL: $cx = COPY [[MOV16ri]]
341 ; ALL: $cl = KILL killed $cx
342 ; ALL: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
343 ; ALL: $ax = COPY [[SHR16rCL]]
330 ; ALL: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def $eflags
331 ; ALL: $ax = COPY [[SHR16ri]]
344332 ; ALL: RET 0, implicit $ax
345333 %0(s32) = COPY $edi
346 %2(s16) = G_CONSTANT i16 5
334 %2(s8) = G_CONSTANT i16 5
347335 %1(s16) = G_TRUNC %0(s32)
348336 %3(s16) = G_LSHR %1, %2
349337 $ax = COPY %3(s16)
372360 ; ALL-LABEL: name: test_lshr_i16_imm1
373361 ; ALL: liveins: $edi
374362 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
375 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 1
376363 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
377 ; ALL: $cx = COPY [[MOV16ri]]
378 ; ALL: $cl = KILL killed $cx
379 ; ALL: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY1]], implicit-def $eflags, implicit $cl
380 ; ALL: $ax = COPY [[SHR16rCL]]
364 ; ALL: [[SHR16r1_:%[0-9]+]]:gr16 = SHR16r1 [[COPY1]], implicit-def $eflags
365 ; ALL: $ax = COPY [[SHR16r1_]]
381366 ; ALL: RET 0, implicit $ax
382367 %0(s32) = COPY $edi
383 %2(s16) = G_CONSTANT i16 1
368 %2(s8) = G_CONSTANT i16 1
384369 %1(s16) = G_TRUNC %0(s32)
385370 %3(s16) = G_LSHR %1, %2
386371 $ax = COPY %3(s16)
8080 - { id: 0, class: gpr, preferred-register: '' }
8181 - { id: 1, class: gpr, preferred-register: '' }
8282 - { id: 2, class: gpr, preferred-register: '' }
83 - { id: 3, class: gpr, preferred-register: '' }
8384 liveins:
8485 fixedStack:
8586 stack:
9192 ; ALL-LABEL: name: test_shl_i64
9293 ; ALL: liveins: $rdi, $rsi
9394 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
94 ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
95 ; ALL: $rcx = COPY [[COPY1]]
96 ; ALL: $cl = KILL killed $rcx
95 ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
96 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
97 ; ALL: $cl = COPY [[COPY2]]
9798 ; ALL: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def $eflags, implicit $cl
9899 ; ALL: $rax = COPY [[SHL64rCL]]
99100 ; ALL: RET 0, implicit $rax
100101 %0(s64) = COPY $rdi
101102 %1(s64) = COPY $rsi
103 %2(s8) = G_TRUNC %1
104 %3(s64) = G_SHL %0, %2
105 $rax = COPY %3(s64)
106 RET 0, implicit $rax
107
108 ...
109 ---
110 name: test_shl_i64_imm
111 alignment: 4
112 legalized: true
113 regBankSelected: true
114 tracksRegLiveness: true
115 registers:
116 - { id: 0, class: gpr, preferred-register: '' }
117 - { id: 1, class: gpr, preferred-register: '' }
118 - { id: 2, class: gpr, preferred-register: '' }
119 liveins:
120 fixedStack:
121 stack:
122 constants:
123 body: |
124 bb.1 (%ir-block.0):
125 liveins: $rdi
126
127 ; ALL-LABEL: name: test_shl_i64_imm
128 ; ALL: liveins: $rdi
129 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
130 ; ALL: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def $eflags
131 ; ALL: $rax = COPY [[SHL64ri]]
132 ; ALL: RET 0, implicit $rax
133 %0(s64) = COPY $rdi
134 %1(s8) = G_CONSTANT i64 5
102135 %2(s64) = G_SHL %0, %1
103136 $rax = COPY %2(s64)
104137 RET 0, implicit $rax
105138
106139 ...
107140 ---
108 name: test_shl_i64_imm
141 name: test_shl_i64_imm1
109142 alignment: 4
110143 legalized: true
111144 regBankSelected: true
122155 bb.1 (%ir-block.0):
123156 liveins: $rdi
124157
125 ; ALL-LABEL: name: test_shl_i64_imm
158 ; ALL-LABEL: name: test_shl_i64_imm1
126159 ; ALL: liveins: $rdi
127160 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
128 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 5
129 ; ALL: $rcx = COPY [[MOV64ri32_]]
130 ; ALL: $cl = KILL killed $rcx
131 ; ALL: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def $eflags, implicit $cl
132 ; ALL: $rax = COPY [[SHL64rCL]]
161 ; ALL: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def $eflags
162 ; ALL: $rax = COPY [[ADD64rr]]
133163 ; ALL: RET 0, implicit $rax
134164 %0(s64) = COPY $rdi
135 %1(s64) = G_CONSTANT i64 5
165 %1(s8) = G_CONSTANT i64 1
136166 %2(s64) = G_SHL %0, %1
137167 $rax = COPY %2(s64)
138168 RET 0, implicit $rax
139169
140170 ...
141171 ---
142 name: test_shl_i64_imm1
143 alignment: 4
144 legalized: true
145 regBankSelected: true
146 tracksRegLiveness: true
147 registers:
148 - { id: 0, class: gpr, preferred-register: '' }
149 - { id: 1, class: gpr, preferred-register: '' }
150 - { id: 2, class: gpr, preferred-register: '' }
151 liveins:
152 fixedStack:
153 stack:
154 constants:
155 body: |
156 bb.1 (%ir-block.0):
157 liveins: $rdi
158
159 ; ALL-LABEL: name: test_shl_i64_imm1
160 ; ALL: liveins: $rdi
161 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
162 ; ALL: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1
163 ; ALL: $rcx = COPY [[MOV64ri32_]]
164 ; ALL: $cl = KILL killed $rcx
165 ; ALL: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def $eflags, implicit $cl
166 ; ALL: $rax = COPY [[SHL64rCL]]
167 ; ALL: RET 0, implicit $rax
168 %0(s64) = COPY $rdi
169 %1(s64) = G_CONSTANT i64 1
170 %2(s64) = G_SHL %0, %1
171 $rax = COPY %2(s64)
172 RET 0, implicit $rax
173
174 ...
175 ---
176172 name: test_shl_i32
177173 alignment: 4
178174 legalized: true
182178 - { id: 0, class: gpr, preferred-register: '' }
183179 - { id: 1, class: gpr, preferred-register: '' }
184180 - { id: 2, class: gpr, preferred-register: '' }
181 - { id: 3, class: gpr, preferred-register: '' }
185182 liveins:
186183 fixedStack:
187184 stack:
194191 ; ALL: liveins: $edi, $esi
195192 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
196193 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
197 ; ALL: $ecx = COPY [[COPY1]]
198 ; ALL: $cl = KILL killed $ecx
194 ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
195 ; ALL: $cl = COPY [[COPY2]]
199196 ; ALL: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def $eflags, implicit $cl
200197 ; ALL: $eax = COPY [[SHL32rCL]]
201198 ; ALL: RET 0, implicit $eax
202199 %0(s32) = COPY $edi
203200 %1(s32) = COPY $esi
201 %2(s8) = G_TRUNC %1
202 %3(s32) = G_SHL %0, %2
203 $eax = COPY %3(s32)
204 RET 0, implicit $eax
205
206 ...
207 ---
208 name: test_shl_i32_imm
209 alignment: 4
210 legalized: true
211 regBankSelected: true
212 tracksRegLiveness: true
213 registers:
214 - { id: 0, class: gpr, preferred-register: '' }
215 - { id: 1, class: gpr, preferred-register: '' }
216 - { id: 2, class: gpr, preferred-register: '' }
217 liveins:
218 fixedStack:
219 stack:
220 constants:
221 body: |
222 bb.1 (%ir-block.0):
223 liveins: $edi
224
225 ; ALL-LABEL: name: test_shl_i32_imm
226 ; ALL: liveins: $edi
227 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
228 ; ALL: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def $eflags
229 ; ALL: $eax = COPY [[SHL32ri]]
230 ; ALL: RET 0, implicit $eax
231 %0(s32) = COPY $edi
232 %1(s8) = G_CONSTANT i32 5
204233 %2(s32) = G_SHL %0, %1
205234 $eax = COPY %2(s32)
206235 RET 0, implicit $eax
207236
208237 ...
209238 ---
210 name: test_shl_i32_imm
211 alignment: 4
212 legalized: true
213 regBankSelected: true
214 tracksRegLiveness: true
215 registers:
216 - { id: 0, class: gpr, preferred-register: '' }
217 - { id: 1, class: gpr, preferred-register: '' }
218 - { id: 2, class: gpr, preferred-register: '' }
219 liveins:
220 fixedStack:
221 stack:
222 constants:
223 body: |
224 bb.1 (%ir-block.0):
225 liveins: $edi
226
227 ; ALL-LABEL: name: test_shl_i32_imm
228 ; ALL: liveins: $edi
229 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
230 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 5
231 ; ALL: $ecx = COPY [[MOV32ri]]
232 ; ALL: $cl = KILL killed $ecx
233 ; ALL: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def $eflags, implicit $cl
234 ; ALL: $eax = COPY [[SHL32rCL]]
239 name: test_shl_i32_imm1
240 alignment: 4
241 legalized: true
242 regBankSelected: true
243 tracksRegLiveness: true
244 registers:
245 - { id: 0, class: gpr, preferred-register: '' }
246 - { id: 1, class: gpr, preferred-register: '' }
247 - { id: 2, class: gpr, preferred-register: '' }
248 liveins:
249 fixedStack:
250 stack:
251 constants:
252 body: |
253 bb.1 (%ir-block.0):
254 liveins: $edi
255
256 ; ALL-LABEL: name: test_shl_i32_imm1
257 ; ALL: liveins: $edi
258 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
259 ; ALL: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def $eflags
260 ; ALL: $eax = COPY [[ADD32rr]]
235261 ; ALL: RET 0, implicit $eax
236262 %0(s32) = COPY $edi
237 %1(s32) = G_CONSTANT i32 5
263 %1(s8) = G_CONSTANT i32 1
238264 %2(s32) = G_SHL %0, %1
239265 $eax = COPY %2(s32)
240266 RET 0, implicit $eax
241267
242268 ...
243269 ---
244 name: test_shl_i32_imm1
245 alignment: 4
246 legalized: true
247 regBankSelected: true
248 tracksRegLiveness: true
249 registers:
250 - { id: 0, class: gpr, preferred-register: '' }
251 - { id: 1, class: gpr, preferred-register: '' }
252 - { id: 2, class: gpr, preferred-register: '' }
253 liveins:
254 fixedStack:
255 stack:
256 constants:
257 body: |
258 bb.1 (%ir-block.0):
259 liveins: $edi
260
261 ; ALL-LABEL: name: test_shl_i32_imm1
262 ; ALL: liveins: $edi
263 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
264 ; ALL: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
265 ; ALL: $ecx = COPY [[MOV32ri]]
266 ; ALL: $cl = KILL killed $ecx
267 ; ALL: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def $eflags, implicit $cl
268 ; ALL: $eax = COPY [[SHL32rCL]]
269 ; ALL: RET 0, implicit $eax
270 %0(s32) = COPY $edi
271 %1(s32) = G_CONSTANT i32 1
272 %2(s32) = G_SHL %0, %1
273 $eax = COPY %2(s32)
274 RET 0, implicit $eax
275
276 ...
277 ---
278270 name: test_shl_i16
279271 alignment: 4
280272 legalized: true
299291 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
300292 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
301293 ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
302 ; ALL: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
303 ; ALL: $cx = COPY [[COPY3]]
304 ; ALL: $cl = KILL killed $cx
294 ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
295 ; ALL: $cl = COPY [[COPY3]]
305296 ; ALL: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def $eflags, implicit $cl
306297 ; ALL: $ax = COPY [[SHL16rCL]]
307298 ; ALL: RET 0, implicit $ax
308299 %0(s32) = COPY $edi
309300 %1(s32) = COPY $esi
310301 %2(s16) = G_TRUNC %0(s32)
311 %3(s16) = G_TRUNC %1(s32)
302 %3(s8) = G_TRUNC %1(s32)
312303 %4(s16) = G_SHL %2, %3
313304 $ax = COPY %4(s16)
314305 RET 0, implicit $ax
336327 ; ALL-LABEL: name: test_shl_i16_imm
337328 ; ALL: liveins: $edi
338329 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
339 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 5
340330 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
341 ; ALL: $cx = COPY [[MOV16ri]]
342 ; ALL: $cl = KILL killed $cx
343 ; ALL: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY1]], implicit-def $eflags, implicit $cl
344 ; ALL: $ax = COPY [[SHL16rCL]]
331 ; ALL: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def $eflags
332 ; ALL: $ax = COPY [[SHL16ri]]
345333 ; ALL: RET 0, implicit $ax
346334 %0(s32) = COPY $edi
347 %2(s16) = G_CONSTANT i16 5
335 %2(s8) = G_CONSTANT i16 5
348336 %1(s16) = G_TRUNC %0(s32)
349337 %3(s16) = G_SHL %1, %2
350338 $ax = COPY %3(s16)
373361 ; ALL-LABEL: name: test_shl_i16_imm1
374362 ; ALL: liveins: $edi
375363 ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
376 ; ALL: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 1
377364 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
378 ; ALL: $cx = COPY [[MOV16ri]]
379 ; ALL: $cl = KILL killed $cx
380 ; ALL: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY1]], implicit-def $eflags, implicit $cl
381 ; ALL: $ax = COPY [[SHL16rCL]]
365 ; ALL: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def $eflags
366 ; ALL: $ax = COPY [[ADD16rr]]
382367 ; ALL: RET 0, implicit $ax
383368 %0(s32) = COPY $edi
384 %2(s16) = G_CONSTANT i16 1
369 %2(s8) = G_CONSTANT i16 1
385370 %1(s16) = G_TRUNC %0(s32)
386371 %3(s16) = G_SHL %1, %2
387372 $ax = COPY %3(s16)
55 ; X64: # %bb.0:
66 ; X64-NEXT: movq %rdi, %rax
77 ; X64-NEXT: movq %rsi, %rcx
8 ; X64-NEXT: # kill: def $cl killed $rcx
8 ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
99 ; X64-NEXT: shlq %cl, %rax
1010 ; X64-NEXT: retq
1111 %res = shl i64 %arg1, %arg2
1717 ; X64: # %bb.0:
1818 ; X64-NEXT: movq %rdi, %rax
1919 ; X64-NEXT: movq $5, %rcx
20 ; X64-NEXT: # kill: def $cl killed $rcx
2120 ; X64-NEXT: shlq %cl, %rax
2221 ; X64-NEXT: retq
2322 %res = shl i64 %arg1, 5
2928 ; X64: # %bb.0:
3029 ; X64-NEXT: movq %rdi, %rax
3130 ; X64-NEXT: movq $1, %rcx
32 ; X64-NEXT: # kill: def $cl killed $rcx
3331 ; X64-NEXT: shlq %cl, %rax
3432 ; X64-NEXT: retq
3533 %res = shl i64 %arg1, 1
4139 ; X64: # %bb.0:
4240 ; X64-NEXT: movl %edi, %eax
4341 ; X64-NEXT: movl %esi, %ecx
44 ; X64-NEXT: # kill: def $cl killed $ecx
42 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
4543 ; X64-NEXT: shll %cl, %eax
4644 ; X64-NEXT: retq
4745 %res = shl i32 %arg1, %arg2
5351 ; X64: # %bb.0:
5452 ; X64-NEXT: movl %edi, %eax
5553 ; X64-NEXT: movl $5, %ecx
56 ; X64-NEXT: # kill: def $cl killed $ecx
5754 ; X64-NEXT: shll %cl, %eax
5855 ; X64-NEXT: retq
5956 %res = shl i32 %arg1, 5
6562 ; X64: # %bb.0:
6663 ; X64-NEXT: movl %edi, %eax
6764 ; X64-NEXT: movl $1, %ecx
68 ; X64-NEXT: # kill: def $cl killed $ecx
6965 ; X64-NEXT: shll %cl, %eax
7066 ; X64-NEXT: retq
7167 %res = shl i32 %arg1, 1
7773 ; X64: # %bb.0:
7874 ; X64-NEXT: movl %edi, %eax
7975 ; X64-NEXT: movl %esi, %ecx
80 ; X64-NEXT: # kill: def $cx killed $cx killed $ecx
81 ; X64-NEXT: # kill: def $cl killed $cx
76 ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
8277 ; X64-NEXT: shlw %cl, %ax
8378 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
8479 ; X64-NEXT: retq
9388 ; X64: # %bb.0:
9489 ; X64-NEXT: movl %edi, %eax
9590 ; X64-NEXT: movw $5, %cx
96 ; X64-NEXT: # kill: def $cl killed $cx
9791 ; X64-NEXT: shlw %cl, %ax
9892 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
9993 ; X64-NEXT: retq
107101 ; X64: # %bb.0:
108102 ; X64-NEXT: movl %edi, %eax
109103 ; X64-NEXT: movw $1, %cx
110 ; X64-NEXT: # kill: def $cl killed $cx
111104 ; X64-NEXT: shlw %cl, %ax
112105 ; X64-NEXT: # kill: def $ax killed $ax killed $eax
113106 ; X64-NEXT: retq
8989 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
9090 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
9191 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
92 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
93 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
92 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
93 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
94 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
95 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
9496 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
9597 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
9698 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
121123 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
122124 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
123125 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
124 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
125 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
126 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
127 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
128 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
129 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
126130 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
127131 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
128132 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
205209 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
206210 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
207211 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
208 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
209 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
212 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
213 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
214 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
215 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
210216 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
211217 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
212218 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
237243 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
238244 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
239245 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
240 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
241 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
246 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
247 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
248 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
249 ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
242250 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
243251 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
244252 ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)