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Merging r182364: ------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
2 changed file(s) with 27 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
93359335 if (Swap)
93369336 std::swap(Op0, Op1);
93379337
9338 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9339 // bits of the inputs before performing those operations.
9340 if (FlipSigns) {
9341 EVT EltVT = VT.getVectorElementType();
9342 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9343 EltVT);
9344 std::vector SignBits(VT.getVectorNumElements(), SignBit);
9345 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9346 SignBits.size());
9347 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9348 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9349 }
9350
93519338 // Check that the operation in question is available (most are plain SSE2,
93529339 // but PCMPGTQ and PCMPEQQ have different requirements).
93539340 if (VT == MVT::v2i64) {
93549341 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
93559342 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
93569343
9357 // First cast everything to the right type,
9344 // First cast everything to the right type.
93589345 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
93599346 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9347
9348 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9349 // bits of the inputs before performing those operations.
9350 if (FlipSigns) {
9351 SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9352 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9353 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9354 }
93609355
93619356 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
93629357 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
93839378 // pcmpeqd + pshufd + pand.
93849379 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
93859380
9386 // First cast everything to the right type,
9381 // First cast everything to the right type.
93879382 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
93889383 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
93899384
94009395
94019396 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
94029397 }
9398 }
9399
9400 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9401 // bits of the inputs before performing those operations.
9402 if (FlipSigns) {
9403 EVT EltVT = VT.getVectorElementType();
9404 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9405 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9406 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
94039407 }
94049408
94059409 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
130130 }
131131
132132 define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
133 ; CHECK: [[CONSTSEG:[A-Z0-9_]*]]:
134 ; CHECK: .long 2147483648
135 ; CHECK-NEXT: .long 2147483648
136 ; CHECK-NEXT: .long 2147483648
137 ; CHECK-NEXT: .long 2147483648
133138 ; CHECK: test11:
134 ; CHECK: pxor
135 ; CHECK: pxor
139 ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
140 ; CHECK: pxor [[CONSTREG]]
141 ; CHECK: pxor [[CONSTREG]]
136142 ; CHECK: pcmpgtd %xmm1
137143 ; CHECK: pshufd $-96
138144 ; CHECK: pcmpeqd