llvm.org GIT mirror llvm / 5f47106
[X86] Replace MVT::SimpleValueType in the AsmParser library and getX86SubSuperRegister with just an unsigned representing size. This a is step towards fixing a layering violation so the X86 AsmParser won't depending on CodeGen types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256425 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 years ago
7 changed file(s) with 120 addition(s) and 130 deletion(s). Raw diff Collapse all Expand all
1212 #include "X86RegisterInfo.h"
1313 #include "llvm/ADT/StringExtras.h"
1414 #include "llvm/ADT/Triple.h"
15 #include "llvm/CodeGen/MachineValueType.h"
1615 #include "llvm/MC/MCAsmInfo.h"
1716 #include "llvm/MC/MCContext.h"
1817 #include "llvm/MC/MCInst.h"
130129 public:
131130 RegisterContext(unsigned AddressReg, unsigned ShadowReg,
132131 unsigned ScratchReg) {
133 BusyRegs.push_back(convReg(AddressReg, MVT::i64));
134 BusyRegs.push_back(convReg(ShadowReg, MVT::i64));
135 BusyRegs.push_back(convReg(ScratchReg, MVT::i64));
136 }
137
138 unsigned AddressReg(MVT::SimpleValueType VT) const {
139 return convReg(BusyRegs[REG_OFFSET_ADDRESS], VT);
140 }
141
142 unsigned ShadowReg(MVT::SimpleValueType VT) const {
143 return convReg(BusyRegs[REG_OFFSET_SHADOW], VT);
144 }
145
146 unsigned ScratchReg(MVT::SimpleValueType VT) const {
147 return convReg(BusyRegs[REG_OFFSET_SCRATCH], VT);
132 BusyRegs.push_back(convReg(AddressReg, 64));
133 BusyRegs.push_back(convReg(ShadowReg, 64));
134 BusyRegs.push_back(convReg(ScratchReg, 64));
135 }
136
137 unsigned AddressReg(unsigned Size) const {
138 return convReg(BusyRegs[REG_OFFSET_ADDRESS], Size);
139 }
140
141 unsigned ShadowReg(unsigned Size) const {
142 return convReg(BusyRegs[REG_OFFSET_SHADOW], Size);
143 }
144
145 unsigned ScratchReg(unsigned Size) const {
146 return convReg(BusyRegs[REG_OFFSET_SCRATCH], Size);
148147 }
149148
150149 void AddBusyReg(unsigned Reg) {
151150 if (Reg != X86::NoRegister)
152 BusyRegs.push_back(convReg(Reg, MVT::i64));
151 BusyRegs.push_back(convReg(Reg, 64));
153152 }
154153
155154 void AddBusyRegs(const X86Operand &Op) {
157156 AddBusyReg(Op.getMemIndexReg());
158157 }
159158
160 unsigned ChooseFrameReg(MVT::SimpleValueType VT) const {
159 unsigned ChooseFrameReg(unsigned Size) const {
161160 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
162161 X86::RCX, X86::RDX, X86::RDI,
163162 X86::RSI };
164163 for (unsigned Reg : Candidates) {
165164 if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
166 return convReg(Reg, VT);
165 return convReg(Reg, Size);
167166 }
168167 return X86::NoRegister;
169168 }
170169
171170 private:
172 unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
173 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
171 unsigned convReg(unsigned Reg, unsigned Size) const {
172 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, Size);
174173 }
175174
176175 std::vector BusyRegs;
234233 protected:
235234 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
236235
237 void EmitLEA(X86Operand &Op, MVT::SimpleValueType VT, unsigned Reg,
238 MCStreamer &Out) {
239 assert(VT == MVT::i32 || VT == MVT::i64);
236 void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) {
237 assert(Size == 32 || Size == 64);
240238 MCInst Inst;
241 Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
242 Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, VT)));
239 Inst.setOpcode(Size == 32 ? X86::LEA32r : X86::LEA64r);
240 Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, Size)));
243241 Op.addMemOperands(Inst, 5);
244242 EmitInstruction(Out, Inst);
245243 }
246244
247 void ComputeMemOperandAddress(X86Operand &Op, MVT::SimpleValueType VT,
245 void ComputeMemOperandAddress(X86Operand &Op, unsigned Size,
248246 unsigned Reg, MCContext &Ctx, MCStreamer &Out);
249247
250248 // Creates new memory operand with Displacement added to an original
431429 }
432430
433431 void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
434 MVT::SimpleValueType VT,
432 unsigned Size,
435433 unsigned Reg, MCContext &Ctx,
436434 MCStreamer &Out) {
437435 int64_t Displacement = 0;
444442
445443 // Emit Op as is.
446444 if (Displacement == 0) {
447 EmitLEA(Op, VT, Reg, Out);
445 EmitLEA(Op, Size, Reg, Out);
448446 return;
449447 }
450448
451449 int64_t Residue;
452450 std::unique_ptr NewOp =
453451 AddDisplacement(Op, Displacement, Ctx, &Residue);
454 EmitLEA(*NewOp, VT, Reg, Out);
452 EmitLEA(*NewOp, Size, Reg, Out);
455453
456454 while (Residue != 0) {
457455 const MCConstantExpr *Disp =
459457 std::unique_ptr DispOp =
460458 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc(),
461459 SMLoc());
462 EmitLEA(*DispOp, VT, Reg, Out);
460 EmitLEA(*DispOp, Size, Reg, Out);
463461 Residue -= Disp->getValue();
464462 }
465463 }
506504 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
507505 if (FrameReg == X86::NoRegister)
508506 return FrameReg;
509 return getX86SubSuperRegister(FrameReg, MVT::i32);
507 return getX86SubSuperRegister(FrameReg, 32);
510508 }
511509
512510 void SpillReg(MCStreamer &Out, unsigned Reg) {
532530 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
533531 MCContext &Ctx,
534532 MCStreamer &Out) override {
535 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
533 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
536534 assert(LocalFrameReg != X86::NoRegister);
537535
538536 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
552550 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
553551 }
554552
555 SpillReg(Out, RegCtx.AddressReg(MVT::i32));
556 SpillReg(Out, RegCtx.ShadowReg(MVT::i32));
557 if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
558 SpillReg(Out, RegCtx.ScratchReg(MVT::i32));
553 SpillReg(Out, RegCtx.AddressReg(32));
554 SpillReg(Out, RegCtx.ShadowReg(32));
555 if (RegCtx.ScratchReg(32) != X86::NoRegister)
556 SpillReg(Out, RegCtx.ScratchReg(32));
559557 StoreFlags(Out);
560558 }
561559
562560 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
563561 MCContext &Ctx,
564562 MCStreamer &Out) override {
565 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
563 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
566564 assert(LocalFrameReg != X86::NoRegister);
567565
568566 RestoreFlags(Out);
569 if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
570 RestoreReg(Out, RegCtx.ScratchReg(MVT::i32));
571 RestoreReg(Out, RegCtx.ShadowReg(MVT::i32));
572 RestoreReg(Out, RegCtx.AddressReg(MVT::i32));
567 if (RegCtx.ScratchReg(32) != X86::NoRegister)
568 RestoreReg(Out, RegCtx.ScratchReg(32));
569 RestoreReg(Out, RegCtx.ShadowReg(32));
570 RestoreReg(Out, RegCtx.AddressReg(32));
573571
574572 unsigned FrameReg = GetFrameReg(Ctx, Out);
575573 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
604602 .addReg(X86::ESP)
605603 .addImm(-16));
606604 EmitInstruction(
607 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
605 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32)));
608606
609607 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
610608 (IsWrite ? "store" : "load") +
618616 void X86AddressSanitizer32::InstrumentMemOperandSmall(
619617 X86Operand &Op, unsigned AccessSize, bool IsWrite,
620618 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
621 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
622 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
623 unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
624
625 assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
626 unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
627
628 ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
619 unsigned AddressRegI32 = RegCtx.AddressReg(32);
620 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
621 unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
622
623 assert(RegCtx.ScratchReg(32) != X86::NoRegister);
624 unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
625
626 ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
629627
630628 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
631629 AddressRegI32));
668666 std::unique_ptr Op(
669667 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
670668 SMLoc(), SMLoc()));
671 EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
669 EmitLEA(*Op, 32, ScratchRegI32, Out);
672670 break;
673671 }
674672 case 4:
693691 void X86AddressSanitizer32::InstrumentMemOperandLarge(
694692 X86Operand &Op, unsigned AccessSize, bool IsWrite,
695693 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
696 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
697 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
698
699 ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
694 unsigned AddressRegI32 = RegCtx.AddressReg(32);
695 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
696
697 ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
700698
701699 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
702700 AddressRegI32));
764762 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
765763 if (FrameReg == X86::NoRegister)
766764 return FrameReg;
767 return getX86SubSuperRegister(FrameReg, MVT::i64);
765 return getX86SubSuperRegister(FrameReg, 64);
768766 }
769767
770768 void SpillReg(MCStreamer &Out, unsigned Reg) {
790788 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
791789 MCContext &Ctx,
792790 MCStreamer &Out) override {
793 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
791 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
794792 assert(LocalFrameReg != X86::NoRegister);
795793
796794 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
811809 }
812810
813811 EmitAdjustRSP(Ctx, Out, -128);
814 SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
815 SpillReg(Out, RegCtx.AddressReg(MVT::i64));
816 if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
817 SpillReg(Out, RegCtx.ScratchReg(MVT::i64));
812 SpillReg(Out, RegCtx.ShadowReg(64));
813 SpillReg(Out, RegCtx.AddressReg(64));
814 if (RegCtx.ScratchReg(64) != X86::NoRegister)
815 SpillReg(Out, RegCtx.ScratchReg(64));
818816 StoreFlags(Out);
819817 }
820818
821819 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
822820 MCContext &Ctx,
823821 MCStreamer &Out) override {
824 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
822 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
825823 assert(LocalFrameReg != X86::NoRegister);
826824
827825 RestoreFlags(Out);
828 if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
829 RestoreReg(Out, RegCtx.ScratchReg(MVT::i64));
830 RestoreReg(Out, RegCtx.AddressReg(MVT::i64));
831 RestoreReg(Out, RegCtx.ShadowReg(MVT::i64));
826 if (RegCtx.ScratchReg(64) != X86::NoRegister)
827 RestoreReg(Out, RegCtx.ScratchReg(64));
828 RestoreReg(Out, RegCtx.AddressReg(64));
829 RestoreReg(Out, RegCtx.ShadowReg(64));
832830 EmitAdjustRSP(Ctx, Out, 128);
833831
834832 unsigned FrameReg = GetFrameReg(Ctx, Out);
859857 std::unique_ptr Op(
860858 X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1,
861859 SMLoc(), SMLoc()));
862 EmitLEA(*Op, MVT::i64, X86::RSP, Out);
860 EmitLEA(*Op, 64, X86::RSP, Out);
863861 OrigSPOffset += Offset;
864862 }
865863
873871 .addReg(X86::RSP)
874872 .addImm(-16));
875873
876 if (RegCtx.AddressReg(MVT::i64) != X86::RDI) {
874 if (RegCtx.AddressReg(64) != X86::RDI) {
877875 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
878 RegCtx.AddressReg(MVT::i64)));
876 RegCtx.AddressReg(64)));
879877 }
880878 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
881879 (IsWrite ? "store" : "load") +
889887 void X86AddressSanitizer64::InstrumentMemOperandSmall(
890888 X86Operand &Op, unsigned AccessSize, bool IsWrite,
891889 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
892 unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
893 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
894 unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
895 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
896 unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
897
898 assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
899 unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
900
901 ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
890 unsigned AddressRegI64 = RegCtx.AddressReg(64);
891 unsigned AddressRegI32 = RegCtx.AddressReg(32);
892 unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
893 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
894 unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
895
896 assert(RegCtx.ScratchReg(32) != X86::NoRegister);
897 unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
898
899 ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
902900
903901 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
904902 AddressRegI64));
940938 std::unique_ptr Op(
941939 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
942940 SMLoc(), SMLoc()));
943 EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
941 EmitLEA(*Op, 32, ScratchRegI32, Out);
944942 break;
945943 }
946944 case 4:
965963 void X86AddressSanitizer64::InstrumentMemOperandLarge(
966964 X86Operand &Op, unsigned AccessSize, bool IsWrite,
967965 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
968 unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
969 unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
970
971 ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
966 unsigned AddressRegI64 = RegCtx.AddressReg(64);
967 unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
968
969 ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
972970
973971 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
974972 AddressRegI64));
216216 if (AsmVariant == 0) O << '%';
217217 unsigned Reg = MO.getReg();
218218 if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
219 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ?
220 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
221 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
222 Reg = getX86SubSuperRegister(Reg, VT);
219 unsigned Size = (strcmp(Modifier+6,"64") == 0) ? 64 :
220 (strcmp(Modifier+6,"32") == 0) ? 32 :
221 (strcmp(Modifier+6,"16") == 0) ? 16 : 8;
222 Reg = getX86SubSuperRegister(Reg, Size);
223223 }
224224 O << X86ATTInstPrinter::getRegisterName(Reg);
225225 return;
360360 switch (Mode) {
361361 default: return true; // Unknown mode.
362362 case 'b': // Print QImode register
363 Reg = getX86SubSuperRegister(Reg, MVT::i8);
363 Reg = getX86SubSuperRegister(Reg, 8);
364364 break;
365365 case 'h': // Print QImode high register
366 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
366 Reg = getX86SubSuperRegister(Reg, 8, true);
367367 break;
368368 case 'w': // Print HImode register
369 Reg = getX86SubSuperRegister(Reg, MVT::i16);
369 Reg = getX86SubSuperRegister(Reg, 16);
370370 break;
371371 case 'k': // Print SImode register
372 Reg = getX86SubSuperRegister(Reg, MVT::i32);
372 Reg = getX86SubSuperRegister(Reg, 32);
373373 break;
374374 case 'q':
375375 // Print 64-bit register names if 64-bit integer registers are available.
376376 // Otherwise, print 32-bit register names.
377 MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
378 Reg = getX86SubSuperRegister(Reg, Ty);
377 Reg = getX86SubSuperRegister(Reg, P.getSubtarget().is64Bit() ? 64 : 32);
379378 break;
380379 }
381380
926926 unsigned FramePtr = TRI->getFrameRegister(MF);
927927 const unsigned MachineFramePtr =
928928 STI.isTarget64BitILP32()
929 ? getX86SubSuperRegister(FramePtr, MVT::i64) : FramePtr;
929 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
930930 unsigned BasePtr = TRI->getBaseRegister();
931931
932932 // Debug location must be unknown since the first debug location is used
14641464 const bool Is64BitILP32 = STI.isTarget64BitILP32();
14651465 unsigned FramePtr = TRI->getFrameRegister(MF);
14661466 unsigned MachineFramePtr =
1467 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64) : FramePtr;
1467 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
14681468
14691469 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
14701470 bool NeedsWinCFI =
2852228522 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
2852328523 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
2852428524 unsigned Size = VT.getSizeInBits();
28525 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
28526 : Size == 16 ? MVT::i16
28527 : Size == 32 ? MVT::i32
28528 : Size == 64 ? MVT::i64
28529 : MVT::Other;
28530 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
28525 if (Size == 1) Size = 8;
28526 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
2853128527 if (DestReg > 0) {
2853228528 Res.first = DestReg;
28533 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
28534 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
28535 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
28529 Res.second = Size == 8 ? &X86::GR8RegClass
28530 : Size == 16 ? &X86::GR16RegClass
28531 : Size == 32 ? &X86::GR32RegClass
2853628532 : &X86::GR64RegClass;
2853728533 assert(Res.second->contains(Res.first) && "Register in register class");
2853828534 } else {
25692569 ImplicitOp = Src;
25702570 ImplicitOp.setImplicit();
25712571
2572 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2572 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
25732573 MachineBasicBlock::LivenessQueryResult LQR =
25742574 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
25752575
43034303 static
43044304 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
43054305 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4306 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
4306 DestReg = getX86SubSuperRegister(DestReg, 32);
43074307 return X86::KMOVBrk;
43084308 }
43094309 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4310 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4310 SrcReg = getX86SubSuperRegister(SrcReg, 32);
43114311 return X86::KMOVBkr;
43124312 }
43134313 return 0;
43484348 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
43494349 return X86::KMOVWkk;
43504350 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4351 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4351 SrcReg = getX86SubSuperRegister(SrcReg, 32);
43524352 return X86::KMOVWkr;
43534353 }
43544354 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4355 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
4355 DestReg = getX86SubSuperRegister(DestReg, 32);
43564356 return X86::KMOVWrk;
43574357 }
43584358 return 0;
53285328 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
53295329 MIB->setDesc(get(X86::POP64r));
53305330 MIB->getOperand(0)
5331 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), MVT::i64));
5331 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
53325332 } else {
53335333 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
53345334 StackAdjustment = 4;
2626 #include "llvm/CodeGen/MachineInstrBuilder.h"
2727 #include "llvm/CodeGen/MachineModuleInfo.h"
2828 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
3029 #include "llvm/IR/Constants.h"
3130 #include "llvm/IR/Function.h"
3231 #include "llvm/IR/Type.h"
419418 "Stack realignment in presence of dynamic allocas is not supported with"
420419 "this calling convention.");
421420
422 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64);
421 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
423422 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
424423 I.isValid(); ++I)
425424 Reserved.set(*I);
572571 // register as source operand, semantic is the same and destination is
573572 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
574573 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
575 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64);
574 BasePtr = getX86SubSuperRegister(BasePtr, 64);
576575
577576 // This must be part of a four operand memory reference. Replace the
578577 // FrameIndex with base register with EBP. Add an offset to the offset.
624623 const X86Subtarget &Subtarget = MF.getSubtarget();
625624 unsigned FrameReg = getFrameRegister(MF);
626625 if (Subtarget.isTarget64BitILP32())
627 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32);
626 FrameReg = getX86SubSuperRegister(FrameReg, 32);
628627 return FrameReg;
629628 }
630629
631630 namespace llvm {
632 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
633 bool High) {
634 switch (VT) {
631 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, bool High) {
632 switch (Size) {
635633 default: return 0;
636 case MVT::i8:
634 case 8:
637635 if (High) {
638636 switch (Reg) {
639 default: return getX86SubSuperRegisterOrZero(Reg, MVT::i64);
637 default: return getX86SubSuperRegisterOrZero(Reg, 64);
640638 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
641639 return X86::SI;
642640 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
691689 return X86::R15B;
692690 }
693691 }
694 case MVT::i16:
692 case 16:
695693 switch (Reg) {
696694 default: return 0;
697695 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
727725 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
728726 return X86::R15W;
729727 }
730 case MVT::i32:
728 case 32:
731729 switch (Reg) {
732730 default: return 0;
733731 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
763761 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
764762 return X86::R15D;
765763 }
766 case MVT::i64:
764 case 64:
767765 switch (Reg) {
768766 default: return 0;
769767 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
802800 }
803801 }
804802
805 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
806 bool High) {
807 unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
803 unsigned getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
804 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
808805 assert(Res != 0 && "Unexpected register or VT");
809806 return Res;
810807 }
135135 };
136136
137137 /// Returns the sub or super register of a specific X86 register.
138 /// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) returns X86::AX.
138 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
139139 /// Aborts on error.
140 unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
140 unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
141141
142142 /// Returns the sub or super register of a specific X86 register.
143143 /// Like getX86SubSuperRegister() but returns 0 on error.
144 unsigned getX86SubSuperRegisterOrZero(unsigned, MVT::SimpleValueType,
144 unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
145145 bool High = false);
146146
147147 //get512BitRegister - X86 utility - returns 512-bit super register