llvm.org GIT mirror llvm / 5f26855
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8 Mihai Popa 7 years ago
2 changed file(s) with 35 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
54605460 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
54615461 }
54625462
5463 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5464 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5465 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5466 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5467 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5468 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5469 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5470 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5471
5472 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5473 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5474 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5475 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5476 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5477 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5478 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5479 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5480
5481
54635482 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
54645483 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
54655484 IIC_VUNAQ, "vcvt", "f16.f32",
1717 vcvt.f32.u32 q8, q8
1818 @ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2]
1919 vcvt.s32.f32 d16, d16, #1
20 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
21 vcvt.s32.f32 d16, d16, #0
2022 @ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
2123 vcvt.u32.f32 d16, d16, #1
24 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
25 vcvt.u32.f32 d16, d16, #0
2226 @ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
2327 vcvt.f32.s32 d16, d16, #1
28 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
29 vcvt.f32.s32 d16, d16, #0
2430 @ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
2531 vcvt.f32.u32 d16, d16, #1
32 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
33 vcvt.f32.u32 d16, d16, #0
2634 @ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
2735 vcvt.s32.f32 q8, q8, #1
36 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
37 vcvt.s32.f32 q8, q8, #0
2838 @ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
2939 vcvt.u32.f32 q8, q8, #1
40 @ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
41 vcvt.u32.f32 q8, q8, #0
3042 @ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
3143 vcvt.f32.s32 q8, q8, #1
44 @ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
45 vcvt.f32.s32 q8, q8, #0
3246 @ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
3347 vcvt.f32.u32 q8, q8, #1
48 @ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
49 vcvt.f32.u32 q8, q8, #0
3450 @ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3]
3551 vcvt.f32.f16 q8, d16
3652 @ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3]