llvm.org GIT mirror llvm / 5f20963
[x86] Teach the asm comment printing to only print the clarification of an immediate operand when we don't have instruction-specific comments. This ensures that instruction-specific comments are attached to the same line as the instruction which is important for using them to write readable and maintainable tests. My next commit will just such a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217099 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 6 years ago
4 changed file(s) with 68 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
4444 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
4545 uint64_t TSFlags = Desc.TSFlags;
4646
47 // If verbose assembly is enabled, we can print some informative comments.
48 if (CommentStream)
49 HasCustomInstComment =
50 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
51
4752 if (TSFlags & X86II::LOCK)
4853 OS << "\tlock\n";
4954
5358
5459 // Next always print the annotation.
5560 printAnnotation(OS, Annot);
56
57 // If verbose assembly is enabled, we can print some informative comments.
58 if (CommentStream)
59 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
6061 }
6162
6263 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
169170 << '$' << formatImm((int64_t)Op.getImm())
170171 << markup(">");
171172
172 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
173 // If there are no instruction-specific comments, add a comment clarifying
174 // the hex value of the immediate operand when it isn't in the range
175 // [-256,255].
176 if (CommentStream && !HasCustomInstComment &&
177 (Op.getImm() > 255 || Op.getImm() < -256))
173178 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
174179
175180 } else {
128128 void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
129129 printMemOffset(MI, OpNo, O);
130130 }
131
132 private:
133 bool HasCustomInstComment;
131134 };
132135
133136 }
2727 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
2828 /// newline terminated strings to the specified string if desired. This
2929 /// information is shown in disassembly dumps when verbose assembly is enabled.
30 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
30 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
3131 const char *(*getRegName)(unsigned)) {
3232 // If this is a shuffle operation, the switch should fill in this state.
3333 SmallVector ShuffleMask;
3434 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
3535
3636 switch (MI->getOpcode()) {
37 default:
38 // Not an instruction for which we can decode comments.
39 return false;
40
3741 case X86::BLENDPDrri:
3842 case X86::VBLENDPDrri:
3943 Src2Name = getRegName(MI->getOperand(2).getReg());
552556 break;
553557 }
554558
555
556 // If this was a shuffle operation, print the shuffle mask.
557 if (!ShuffleMask.empty()) {
558 if (!DestName) DestName = Src1Name;
559 OS << (DestName ? DestName : "mem") << " = ";
560
561 // If the two sources are the same, canonicalize the input elements to be
562 // from the first src so that we get larger element spans.
563 if (Src1Name == Src2Name) {
564 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
565 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
566 ShuffleMask[i] >= (int)e) // From second mask.
567 ShuffleMask[i] -= e;
568 }
559 // The only comments we decode are shuffles, so give up if we were unable to
560 // decode a shuffle mask.
561 if (ShuffleMask.empty())
562 return false;
563
564 if (!DestName) DestName = Src1Name;
565 OS << (DestName ? DestName : "mem") << " = ";
566
567 // If the two sources are the same, canonicalize the input elements to be
568 // from the first src so that we get larger element spans.
569 if (Src1Name == Src2Name) {
570 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
571 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
572 ShuffleMask[i] >= (int)e) // From second mask.
573 ShuffleMask[i] -= e;
569574 }
570
571 // The shuffle mask specifies which elements of the src1/src2 fill in the
572 // destination, with a few sentinel values. Loop through and print them
573 // out.
574 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
575 if (i != 0)
575 }
576
577 // The shuffle mask specifies which elements of the src1/src2 fill in the
578 // destination, with a few sentinel values. Loop through and print them
579 // out.
580 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
581 if (i != 0)
582 OS << ',';
583 if (ShuffleMask[i] == SM_SentinelZero) {
584 OS << "zero";
585 continue;
586 }
587
588 // Otherwise, it must come from src1 or src2. Print the span of elements
589 // that comes from this src.
590 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
591 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
592 OS << (SrcName ? SrcName : "mem") << '[';
593 bool IsFirst = true;
594 while (i != e &&
595 (int)ShuffleMask[i] >= 0 &&
596 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
597 if (!IsFirst)
576598 OS << ',';
577 if (ShuffleMask[i] == SM_SentinelZero) {
578 OS << "zero";
579 continue;
580 }
581
582 // Otherwise, it must come from src1 or src2. Print the span of elements
583 // that comes from this src.
584 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
585 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
586 OS << (SrcName ? SrcName : "mem") << '[';
587 bool IsFirst = true;
588 while (i != e &&
589 (int)ShuffleMask[i] >= 0 &&
590 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
591 if (!IsFirst)
592 OS << ',';
593 else
594 IsFirst = false;
595 OS << ShuffleMask[i] % ShuffleMask.size();
596 ++i;
597 }
598 OS << ']';
599 --i; // For loop increments element #.
599 else
600 IsFirst = false;
601 OS << ShuffleMask[i] % ShuffleMask.size();
602 ++i;
600603 }
601 //MI->print(OS, 0);
602 OS << "\n";
604 OS << ']';
605 --i; // For loop increments element #.
603606 }
604
607 //MI->print(OS, 0);
608 OS << "\n";
609
610 // We successfully added a comment to this instruction.
611 return true;
605612 }
1717 namespace llvm {
1818 class MCInst;
1919 class raw_ostream;
20 void EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
20 bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
2121 const char *(*getRegName)(unsigned));
2222 }
2323