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Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34692 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
2 changed file(s) with 52 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
2424 #include "llvm/CodeGen/MachineFunction.h"
2525 #include "llvm/CodeGen/MachineInstrBuilder.h"
2626 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/RegisterScavenging.h"
2728 #include "llvm/Target/TargetFrameInfo.h"
2829 #include "llvm/Target/TargetMachine.h"
2930 #include "llvm/Target/TargetOptions.h"
8384 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
8485 TII(tii), STI(sti),
8586 FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
87 RS = new RegScavenger();
88 }
89
90 ARMRegisterInfo::~ARMRegisterInfo() {
91 delete RS;
92 }
93
94 RegScavenger *ARMRegisterInfo::getRegScavenger() const {
95 return EnableScavenging ? RS : NULL;
8696 }
8797
8898 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
327337 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
328338 }
329339
330 bool ARMRegisterInfo::requiresRegisterScavenging() const {
331 return EnableScavenging;
332 }
333
334340 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
335341 /// a destreg = basereg + immediate in ARM code.
336342 static
355361
356362 // Build the new ADD / SUB.
357363 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
358 .addReg(BaseReg).addImm(SOImmVal);
364 .addReg(BaseReg, false, false, true).addImm(SOImmVal);
359365 BaseReg = DestReg;
360366 }
361367 }
422428 if (DestReg == ARM::SP) {
423429 assert(BaseReg == ARM::SP && "Unexpected!");
424430 LdReg = ARM::R3;
425 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
431 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12)
432 .addReg(ARM::R3, false, false, true);
426433 }
427434
428435 if (NumBytes <= 255 && NumBytes >= 0)
429436 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
430437 else if (NumBytes < 0 && NumBytes >= -255) {
431438 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
432 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg);
439 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
440 .addReg(LdReg, false, false, true);
433441 } else
434442 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
435443
436444 // Emit add / sub.
437445 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
438446 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
447 if (DestReg == ARM::SP || isSub)
448 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
449 else
450 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
439451 if (DestReg == ARM::SP)
440 MIB.addReg(BaseReg).addReg(LdReg);
441 else if (isSub)
442 MIB.addReg(BaseReg).addReg(LdReg);
443 else
444 MIB.addReg(LdReg).addReg(BaseReg);
445 if (DestReg == ARM::SP)
446 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
452 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3)
453 .addReg(ARM::R12, false, false, true);
447454 }
448455
449456 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
509516 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
510517 Bytes -= ThisVal;
511518 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
512 .addReg(BaseReg).addImm(ThisVal);
519 .addReg(BaseReg, false, false, true).addImm(ThisVal);
513520 } else {
514 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
521 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg)
522 .addReg(BaseReg, false, false, true);
515523 }
516524 BaseReg = DestReg;
517525 }
525533 if (isTwoAddr)
526534 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
527535 else {
528 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
536 bool isKill = BaseReg != ARM::SP;
537 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
538 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
529539 BaseReg = DestReg;
530540
531541 if (Opc == ARM::tADDrSPi) {
542552 }
543553
544554 if (ExtraOpc)
545 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
555 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
556 .addReg(DestReg, false, false, true)
546557 .addImm(((unsigned)NumBytes) & 3);
547558 }
548559
600611 if (Imm > 0)
601612 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
602613 if (isSub)
603 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg);
614 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
615 .addReg(DestReg, false, false, true);
604616 }
605617
606618 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
721733 // r0 = add r0, sp
722734 emitThumbConstant(MBB, II, DestReg, Offset, TII);
723735 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
724 MI.getOperand(i).ChangeToRegister(DestReg, false);
736 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
725737 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
726738 }
727739 return;
830842 } else
831843 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
832844 MI.setInstrDescriptor(TII.get(ARM::tLDR));
833 MI.getOperand(i).ChangeToRegister(TmpReg, false);
845 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
834846 if (UseRR)
835847 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
836848 else
837 MI.addRegOperand(0, false); // tLDR has an extra register operand.
849 MI.addRegOperand(0, false); // tLDR has an extra register operand.
838850 } else if (TII.isStore(Opcode)) {
839851 // FIXME! This is horrific!!! We need register scavenging.
840852 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
848860 unsigned TmpReg = ARM::R3;
849861 bool UseRR = false;
850862 if (ValReg == ARM::R3) {
851 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
863 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12)
864 .addReg(ARM::R2, false, false, true);
852865 TmpReg = ARM::R2;
853866 }
854867 if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn())
855 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
868 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12)
869 .addReg(ARM::R3, false, false, true);
856870 if (Opcode == ARM::tSpill) {
857871 if (FrameReg == ARM::SP)
858872 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
863877 } else
864878 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
865879 MI.setInstrDescriptor(TII.get(ARM::tSTR));
866 MI.getOperand(i).ChangeToRegister(TmpReg, false);
880 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
867881 if (UseRR)
868882 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
869883 else
871885
872886 MachineBasicBlock::iterator NII = next(II);
873887 if (ValReg == ARM::R3)
874 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
888 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2)
889 .addReg(ARM::R12, false, false, true);
875890 if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn())
876 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
891 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3)
892 .addReg(ARM::R12, false, false, true);
877893 } else
878894 assert(false && "Unexpected opcode!");
879895 } else {
883899 // out of 'Offset'.
884900 emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
885901 isSub ? -Offset : Offset, TII);
886 MI.getOperand(i).ChangeToRegister(ARM::R12, false);
902 MI.getOperand(i).ChangeToRegister(ARM::R12, false, false, true);
887903 }
888904 }
889905
1818 #include "ARMGenRegisterInfo.h.inc"
1919
2020 namespace llvm {
21 class ARMSubtarget;
2122 class TargetInstrInfo;
22 class ARMSubtarget;
2323 class Type;
2424
2525 struct ARMRegisterInfo : public ARMGenRegisterInfo {
2626 const TargetInstrInfo &TII;
2727 const ARMSubtarget &STI;
2828 private:
29 /// RS - An instance of the register scavenger.
30 RegScavenger *RS;
31
2932 /// FramePtr - ARM physical register used as frame ptr.
3033 unsigned FramePtr;
3134
3235 public:
3336 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
37
38 ~ARMRegisterInfo();
39
40 RegScavenger *getRegScavenger() const;
3441
3542 /// getRegisterNumbering - Given the enum value for some register, e.g.
3643 /// ARM::LR, return the number that it corresponds to (e.g. 14).
6875
6976 BitVector getReservedRegs(const MachineFunction &MF) const;
7077
71 bool requiresRegisterScavenging() const;
72
7378 bool hasFP(const MachineFunction &MF) const;
7479
7580 void eliminateCallFramePseudoInstr(MachineFunction &MF,