llvm.org GIT mirror llvm / 5ec8afa
[Sparc] Added V9's extra floating point registers and their aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189195 91177308-0d34-0410-b5e6-96231b3b80d8 Venkatraman Govindaraju 6 years ago
3 changed file(s) with 81 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
6868 Reserved.set(SP::G0);
6969 Reserved.set(SP::G6);
7070 Reserved.set(SP::G7);
71
72 // Unaliased double registers are not available in non-V9 targets.
73 if (!Subtarget.isV9()) {
74 for (unsigned n = 0; n != 16; ++n) {
75 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
76 Reserved.set(*AI);
77 }
78 }
79
7180 return Reserved;
7281 }
7382
2222 let Namespace = "SP" in {
2323 def sub_even : SubRegIndex<32>;
2424 def sub_odd : SubRegIndex<32, 32>;
25 def sub_even64 : SubRegIndex<64>;
26 def sub_odd64 : SubRegIndex<64, 64>;
2527 }
2628
2729 // Registers are identified with 5-bit ID numbers.
3537 class Rd Enc, string n, list subregs> : SparcReg {
3638 let SubRegs = subregs;
3739 let SubRegIndices = [sub_even, sub_odd];
40 let CoveredBySubRegs = 1;
41 }
42
43 // Rq - Slots in the FP register file for 128-bit floating-point values.
44 class Rq Enc, string n, list subregs> : SparcReg {
45 let SubRegs = subregs;
46 let SubRegIndices = [sub_even64, sub_odd64];
3847 let CoveredBySubRegs = 1;
3948 }
4049
131140 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>;
132141 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
133142
143 // Unaliased double precision floating point registers.
144 // FIXME: Define DwarfRegNum for these registers.
145 def D16 : SparcReg< 1, "F32">;
146 def D17 : SparcReg< 3, "F34">;
147 def D18 : SparcReg< 5, "F36">;
148 def D19 : SparcReg< 7, "F38">;
149 def D20 : SparcReg< 9, "F40">;
150 def D21 : SparcReg<11, "F42">;
151 def D22 : SparcReg<13, "F44">;
152 def D23 : SparcReg<15, "F46">;
153 def D24 : SparcReg<17, "F48">;
154 def D25 : SparcReg<19, "F50">;
155 def D26 : SparcReg<21, "F52">;
156 def D27 : SparcReg<23, "F54">;
157 def D28 : SparcReg<25, "F56">;
158 def D29 : SparcReg<27, "F58">;
159 def D30 : SparcReg<29, "F60">;
160 def D31 : SparcReg<31, "F62">;
161
162 // Aliases of the F* registers used to hold 128-bit for values (long doubles).
163 def Q0 : Rq< 0, "F0", [D0, D1]>;
164 def Q1 : Rq< 4, "F4", [D2, D3]>;
165 def Q2 : Rq< 8, "F8", [D4, D5]>;
166 def Q3 : Rq<12, "F12", [D6, D7]>;
167 def Q4 : Rq<16, "F16", [D8, D9]>;
168 def Q5 : Rq<20, "F20", [D10, D11]>;
169 def Q6 : Rq<24, "F24", [D12, D13]>;
170 def Q7 : Rq<28, "F28", [D14, D15]>;
171 def Q8 : Rq< 1, "F32", [D16, D17]>;
172 def Q9 : Rq< 5, "F36", [D18, D19]>;
173 def Q10 : Rq< 9, "F40", [D20, D21]>;
174 def Q11 : Rq<13, "F44", [D22, D23]>;
175 def Q12 : Rq<17, "F48", [D24, D25]>;
176 def Q13 : Rq<21, "F52", [D26, D27]>;
177 def Q14 : Rq<25, "F56", [D28, D29]>;
178 def Q15 : Rq<29, "F60", [D30, D31]>;
179
134180 // Register classes.
135181 //
136182 // FIXME: the register order should be defined in terms of the preferred
154200 // Floating point register classes.
155201 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
156202
157 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
203 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
204
205 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
4444 declare double @get_double()
4545 declare double @llvm.fabs.f64(double) nounwind readonly
4646
47 ; V8-LABEL: test_v9_floatreg:
48 ; V8: fsubd {{.+}}, {{.+}}, {{.+}}
49 ; V8: faddd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
50 ; V8: std [[R]], [%{{.+}}]
51 ; V8: ldd [%{{.+}}], %f0
52
53 ; V9-LABEL: test_v9_floatreg:
54 ; V9: fsubd {{.+}}, {{.+}}, {{.+}}
55 ; V9: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
56 ; V9: fmovd [[R]], %f0
57
58
59 define double @test_v9_floatreg() {
60 entry:
61 %0 = tail call double @get_double()
62 %1 = tail call double @get_double()
63 %2 = fsub double %0, %1
64 tail call void asm sideeffect "", "~{f0},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
65 %3 = fadd double %2, %2
66 ret double %3
67 }
68
69