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[ARM] Turn some undefined encoding bits into 0s. The family of 32-bit Thumb instruction encodings that include t2ORR, t2AND and t2EOR are all listed in the ArmARM as having (0) in bit 15. The Tablegen descriptions of those instructions listed them as ?. This change tightens that up by making them into 0 + Unpredictable. In the specific case of t2ORR, we tighten it up still further by making the zero bit mandatory. This change comes from Arm v8.1-M, in which encodings with that bit equal to 1 will now be used for different instructions. Reviewers: dmgreen, samparker, SjoerdMeijer, efriedma Reviewed By: dmgreen, efriedma Subscribers: efriedma, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60705 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362470 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 3 months ago
2 changed file(s) with 109 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
602602 let Inst{31-27} = 0b11101;
603603 let Inst{26-25} = 0b01;
604604 let Inst{24-21} = opcod;
605 let Inst{15} = 0b0;
606 // In most of these instructions, and most versions of the Arm
607 // architecture, bit 15 of this encoding is listed as (0) rather
608 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail
609 // rather than a hard failure. In v8.1-M, this requirement is
610 // upgraded to a hard one for ORR, so that the encodings with 1
611 // in this bit can be reused for other instructions (such as
612 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce
613 // that encoding clash in the auto- generated MC decoder, so I
614 // comment it out.
615 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);
605616 let Inst{14-12} = 0b000; // imm3
606617 let Inst{7-6} = 0b00; // imm2
607618 let Inst{5-4} = 0b00; // type
615626 let Inst{31-27} = 0b11101;
616627 let Inst{26-25} = 0b01;
617628 let Inst{24-21} = opcod;
629 let Inst{15} = 0;
630 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above
618631 }
619632 // Assembly aliases for optional destination operand when it's the same
620633 // as the source operand.
878891 let Inst{31-27} = 0b11101;
879892 let Inst{26-21} = 0b010010;
880893 let Inst{19-16} = 0b1111; // Rn
894 let Inst{15} = 0b0;
881895 let Inst{5-4} = opcod;
882896 }
883897 // register
18711885 let Inst{26-25} = 0b01;
18721886 let Inst{24-21} = 0b0010;
18731887 let Inst{19-16} = 0b1111; // Rn
1888 let Inst{15} = 0b0;
18741889 let Inst{14-12} = 0b000;
18751890 let Inst{7-4} = 0b0000;
18761891 }
23992414 let Inst{26-25} = 0b01;
24002415 let Inst{24-21} = 0b0010;
24012416 let Inst{19-16} = 0b1111; // Rn
2417 let Inst{15} = 0b0;
2418 let Unpredictable{15} = 0b1;
24022419 let Inst{14-12} = 0b000;
24032420 let Inst{7-4} = 0b0011;
24042421 }
0 # RUN: not llvm-mc -triple=thumbv7 -mcpu=cortex-a8 -disassemble < %s 2> %t | FileCheck %s
1 # RUN: FileCheck --check-prefix=ERROR < %t %s
2
3 [0x09,0xea,0x08,0x04]
4 # CHECK: and.w r4, r9, r8
5
6 [0x09,0xea,0x08,0x84]
7 # CHECK: and.w r4, r9, r8
8 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
9
10 [0x04,0xea,0xe8,0x01]
11 # CHECK: and.w r1, r4, r8, asr #3
12
13 [0x04,0xea,0xe8,0x81]
14 # CHECK: and.w r1, r4, r8, asr #3
15 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
16
17 [0x11,0xea,0x47,0x02]
18 # CHECK: ands.w r2, r1, r7, lsl #1
19
20 [0x11,0xea,0x47,0x82]
21 # CHECK: ands.w r2, r1, r7, lsl #1
22 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
23
24 [0x45,0xea,0x06,0x04]
25 # CHECK: orr.w r4, r5, r6
26
27 [0x45,0xea,0x06,0x84]
28 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
29
30 [0x45,0xea,0x46,0x14]
31 # CHECK: orr.w r4, r5, r6, lsl #5
32
33 [0x45,0xea,0x46,0x94]
34 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
35
36 [0x55,0xea,0x56,0x14]
37 # CHECK: orrs.w r4, r5, r6, lsr #5
38
39 [0x55,0xea,0x56,0x94]
40 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
41
42 [0x85,0xea,0x06,0x04]
43 # CHECK: eor.w r4, r5, r6
44
45 [0x85,0xea,0x06,0x84]
46 # CHECK: eor.w r4, r5, r6
47 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
48
49 [0x85,0xea,0x46,0x14]
50 # CHECK: eor.w r4, r5, r6, lsl #5
51
52 [0x85,0xea,0x46,0x94]
53 # CHECK: eor.w r4, r5, r6, lsl #5
54 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
55
56 [0x4f,0xea,0x02,0x01]
57 # CHECK: mov.w r1, r2
58
59 [0x4f,0xea,0x02,0x81]
60 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
61
62 [0x4f,0xea,0x02,0x46]
63 # CHECK: lsl.w r6, r2, #16
64
65 [0x4f,0xea,0x02,0xc6]
66 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
67
68 [0x4f,0xea,0x12,0x46]
69 # CHECK: lsr.w r6, r2, #16
70
71 [0x4f,0xea,0x12,0xc6]
72 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
73
74 [0x5f,0xea,0x22,0x06]
75 # CHECK: asrs.w r6, r2, #32
76
77 [0x5f,0xea,0x22,0x86]
78 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
79
80 [0x5f,0xea,0x72,0x16]
81 # CHECK: rors.w r6, r2, #5
82
83 [0x5f,0xea,0x72,0x96]
84 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
85
86 [0x4f,0xea,0x34,0x04]
87 # CHECK: rrx r4, r4
88
89 [0x4f,0xea,0x34,0x84]
90 # CHECK: rrx r4, r4
91 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding