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[ARMv8] Add support for the v8 cryptography extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8 Amara Emerson 7 years ago
16 changed file(s) with 459 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
465465 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
466466 [IntrNoMem]>;
467467
468
469 // Crypto instructions
470 def int_arm_neon_aesd : Neon_2Arg_Intrinsic;
471 def int_arm_neon_aese : Neon_2Arg_Intrinsic;
472 def int_arm_neon_aesimc : Neon_1Arg_Intrinsic;
473 def int_arm_neon_aesmc : Neon_1Arg_Intrinsic;
474 def int_arm_neon_sha1h : Neon_1Arg_Intrinsic;
475 def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic;
476 def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic;
477 def int_arm_neon_sha1c : Neon_3Arg_Intrinsic;
478 def int_arm_neon_sha1m : Neon_3Arg_Intrinsic;
479 def int_arm_neon_sha1p : Neon_3Arg_Intrinsic;
480 def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic;
481 def int_arm_neon_sha256h: Neon_3Arg_Intrinsic;
482 def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic;
483 def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic;
484
468485 } // end TargetPrefix
6666 "Enable support for Performance Monitor extensions">;
6767 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
6868 "Enable support for TrustZone security extensions">;
69 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
70 "Enable support for Cryptography extensions",
71 [FeatureNEON]>;
6972
7073 // Some processors have FP multiply-accumulate instructions that don't
7174 // play nicely with other VFP / NEON instructions, and it's generally better
20142014 }
20152015
20162016 // Same as N2V but not predicated.
2017 class N2Vnp op17_16, bits<3> op10_8, bit op7, bit op6,
2017 class N2Vnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
20182018 dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
20192019 string Dt, ValueType ResTy, ValueType OpTy, list pattern>
20202020 : NeonInp
20312031 // Encode constant bits
20322032 let Inst{27-23} = 0b00111;
20332033 let Inst{21-20} = 0b11;
2034 let Inst{19-18} = 0b10;
2034 let Inst{19-18} = op19_18;
20352035 let Inst{17-16} = op17_16;
20362036 let Inst{11} = 0;
20372037 let Inst{10-8} = op10_8;
211211 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
212212 def HasNEON : Predicate<"Subtarget->hasNEON()">,
213213 AssemblerPredicate<"FeatureNEON", "NEON">;
214 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
215 AssemblerPredicate<"FeatureCrypto", "crypto">;
214216 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
215217 AssemblerPredicate<"FeatureFP16","half-float">;
216218 def HasDivide : Predicate<"Subtarget->hasDivide()">,
23542354 class N2VDIntnp op17_16, bits<3> op10_8, bit op7,
23552355 InstrItinClass itin, string OpcodeStr, string Dt,
23562356 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2357 : N2Vnp<op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2357 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
23582358 itin, OpcodeStr, Dt, ResTy, OpTy,
23592359 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
23602360
23612361 class N2VQIntnp op17_16, bits<3> op10_8, bit op7,
23622362 InstrItinClass itin, string OpcodeStr, string Dt,
23632363 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2364 : N2Vnp<op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2364 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
23652365 itin, OpcodeStr, Dt, ResTy, OpTy,
23662366 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2367
2368 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2369 class N2VQIntXnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2370 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2371 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2372 : N2Vnp
2373 itin, OpcodeStr, Dt, ResTy, OpTy,
2374 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2375
2376 // Same as N2VQIntXnp but with Vd as a src register.
2377 class N2VQIntX2np op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2378 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2379 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2380 : N2Vnp
2381 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2382 itin, OpcodeStr, Dt, ResTy, OpTy,
2383 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2384 let Constraints = "$src = $Vd";
2385 }
23672386
23682387 // Narrow 2-register operations.
23692388 class N2VN op24_23, bits<2> op21_20, bits<2> op19_18,
25332552 string Dt, ValueType ResTy, ValueType OpTy,
25342553 SDPatternOperator IntOp, bit Commutable>
25352554 : N3Vnp
2536 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, OpcodeStr, Dt,
2555 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
25372556 ResTy, OpTy, IntOp, Commutable,
25382557 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
25392558
25902609 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
25912610 ResTy, OpTy, IntOp, Commutable,
25922611 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2612
2613 // Same as N3VQIntnp but with Vd as a src register.
2614 class N3VQInt3np op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2615 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2616 string Dt, ValueType ResTy, ValueType OpTy,
2617 SDPatternOperator IntOp, bit Commutable>
2618 : N3Vnp
2619 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2620 Dt, ResTy, OpTy, IntOp, Commutable,
2621 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2622 (OpTy QPR:$Vm))))]> {
2623 let Constraints = "$src = $Vd";
2624 }
25932625
25942626 class N3VQIntSL op21_20, bits<4> op11_8, InstrItinClass itin,
25952627 string OpcodeStr, string Dt,
28412873 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
28422874 let isCommutable = Commutable;
28432875 }
2876
28442877 class N3VLSL op21_20, bits<4> op11_8,
28452878 InstrItinClass itin, string OpcodeStr, string Dt,
28462879 ValueType TyQ, ValueType TyD, SDNode OpNode>
28962929 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
28972930 let isCommutable = Commutable;
28982931 }
2932
2933 // Same as above, but not predicated.
2934 class N3VLIntnp op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2935 bit op4, InstrItinClass itin, string OpcodeStr,
2936 string Dt, ValueType ResTy, ValueType OpTy,
2937 SDPatternOperator IntOp, bit Commutable>
2938 : N3Vnp
2939 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2940 ResTy, OpTy, IntOp, Commutable,
2941 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2942
28992943 class N3VLIntSL op21_20, bits<4> op11_8, InstrItinClass itin,
29002944 string OpcodeStr, string Dt,
29012945 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
40774121 (SubReg_i32_lane imm:$lane)))>;
40784122
40794123 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4080 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4081 "vmull", "s", NEONvmulls, 1>;
4082 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4083 "vmull", "u", NEONvmullu, 1>;
4084 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4085 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4124 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4125 DecoderNamespace = "NEONData" in {
4126 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4127 "vmull", "s", NEONvmulls, 1>;
4128 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4129 "vmull", "u", NEONvmullu, 1>;
4130 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4131 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4132 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4133 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4134 Requires<[HasV8, HasCrypto]>;
4135 }
40864136 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
40874137 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
40884138
58165866 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
58175867 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
58185868 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
5869
5870 // Cryptography instructions
5871 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
5872 DecoderNamespace = "v8Crypto" in {
5873 class AES
5874 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5875 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5876 Requires<[HasV8, HasCrypto]>;
5877 class AES2Op
5878 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5879 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5880 Requires<[HasV8, HasCrypto]>;
5881 class N2SHA op17_16, bits<3> op10_8, bit op7, bit op6,
5882 SDPatternOperator Int>
5883 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5884 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5885 Requires<[HasV8, HasCrypto]>;
5886 class N2SHA2Op op17_16, bits<3> op10_8, bit op7, bit op6,
5887 SDPatternOperator Int>
5888 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5889 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5890 Requires<[HasV8, HasCrypto]>;
5891 class N3SHA3Op op27_23, bits<2> op21_20, SDPatternOperator Int>
5892 : N3VQInt3np
5893 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
5894 Requires<[HasV8, HasCrypto]>;
5895 }
5896
5897 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
5898 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
5899 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
5900 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
5901
5902 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, int_arm_neon_sha1h>;
5903 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
5904 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
5905 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, int_arm_neon_sha1c>;
5906 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, int_arm_neon_sha1m>;
5907 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, int_arm_neon_sha1p>;
5908 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
5909 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
5910 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
5911 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
58195912
58205913 //===----------------------------------------------------------------------===//
58215914 // NEON instructions for single-precision FP math
109109 FPOnlySP = false;
110110 HasPerfMon = false;
111111 HasTrustZone = false;
112 HasCrypto = false;
112113 AllowsUnalignedMem = false;
113114 Thumb2DSP = false;
114115 UseNaClTrap = false;
158158 /// HasTrustZone - if true, processor supports TrustZone security extensions
159159 bool HasTrustZone;
160160
161 /// HasCrypto - if true, processor supports Cryptography extensions
162 bool HasCrypto;
163
161164 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
162165 /// accesses for some types. For details, see
163166 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
247250 bool hasVFP4() const { return HasVFPv4; }
248251 bool hasFPARMv8() const { return HasFPARMv8; }
249252 bool hasNEON() const { return HasNEON; }
253 bool hasCrypto() const { return HasCrypto; }
250254 bool useNEONForSinglePrecisionFP() const {
251255 return hasNEON() && UseNEONForSinglePrecisionFP; }
252256
140140 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
141141 bool &CarrySetting, unsigned &ProcessorIMod,
142142 StringRef &ITMask);
143 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
144 bool &CanAcceptCarrySet,
144145 bool &CanAcceptPredicationCode);
145146
146147 bool isThumb() const {
47834784 //
47844785 // FIXME: It would be nice to autogen this.
47854786 void ARMAsmParser::
4786 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4787 bool &CanAcceptPredicationCode) {
4787 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4788 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
47884789 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
47894790 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
47904791 Mnemonic == "add" || Mnemonic == "adc" ||
48074808 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
48084809 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
48094810 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4810 Mnemonic == "vrintm") {
4811 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4812 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4813 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
48114814 // These mnemonics are never predicable
48124815 CanAcceptPredicationCode = false;
48134816 } else if (!isThumb()) {
50675070 // the matcher deal with finding the right instruction or generating an
50685071 // appropriate error.
50695072 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5070 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5073 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
50715074
50725075 // If we had a carry-set on an instruction that can't do that, issue an
50735076 // error.
506506 }
507507
508508 MI.clear();
509 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
510 this, STI);
511 if (result != MCDisassembler::Fail) {
512 Size = 4;
513 return result;
514 }
515
516 MI.clear();
509517 Size = 0;
510518 return MCDisassembler::Fail;
511519 }
822830 Check(result, AddThumbPredicate(MI));
823831 return result;
824832 }
833 }
834
835 MI.clear();
836 uint32_t NEONCryptoInsn = insn32;
837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
841 Address, this, STI);
842 if (result != MCDisassembler::Fail) {
843 Size = 4;
844 return result;
825845 }
826846
827847 MI.clear();
0 ; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
1
2 define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
3 %tmp = load <16 x i8>* %a
4 %tmp2 = load <16 x i8>* %b
5 %tmp3 = call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %tmp, <16 x i8> %tmp2)
6 ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
7 %tmp4 = call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %tmp3, <16 x i8> %tmp2)
8 ; CHECK: aese.8 q{{[0-9]+}}, q{{[0-9]+}}
9 %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %tmp4)
10 ; CHECK: aesimc.8 q{{[0-9]+}}, q{{[0-9]+}}
11 %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %tmp5)
12 ; CHECK: aesmc.8 q{{[0-9]+}}, q{{[0-9]+}}
13 ret <16 x i8> %tmp6
14 }
15
16 define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
17 %tmp = load <4 x i32>* %a
18 %tmp2 = load <4 x i32>* %b
19 %tmp3 = load <4 x i32>* %c
20 %res1 = call <4 x i32> @llvm.arm.neon.sha1h.v4i32(<4 x i32> %tmp)
21 ; CHECK: sha1h.32 q{{[0-9]+}}, q{{[0-9]+}}
22 %res2 = call <4 x i32> @llvm.arm.neon.sha1c.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3, <4 x i32> %res1)
23 ; CHECK: sha1c.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
24 %res3 = call <4 x i32> @llvm.arm.neon.sha1m.v4i32(<4 x i32> %res2, <4 x i32> %tmp3, <4 x i32> %res1)
25 ; CHECK: sha1m.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
26 %res4 = call <4 x i32> @llvm.arm.neon.sha1p.v4i32(<4 x i32> %res3, <4 x i32> %tmp3, <4 x i32> %res1)
27 ; CHECK: sha1p.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
28 %res5 = call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
29 ; CHECK: sha1su0.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
30 %res6 = call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %res5, <4 x i32> %res1)
31 ; CHECK: sha1su1.32 q{{[0-9]+}}, q{{[0-9]+}}
32 %res7 = call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
33 ; CHECK: sha256h.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
34 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
35 ; CHECK: sha256h2.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
36 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
37 ; CHECK: sha256su1.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
38 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %res9, <4 x i32> %tmp3)
39 ; CHECK: sha256su0.32 q{{[0-9]+}}, q{{[0-9]+}}
40 ret <4 x i32> %res10
41 }
42
43 declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>)
44 declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>)
45 declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>)
46 declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>)
47 declare <4 x i32> @llvm.arm.neon.sha1h.v4i32(<4 x i32>)
48 declare <4 x i32> @llvm.arm.neon.sha1c.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
49 declare <4 x i32> @llvm.arm.neon.sha1m.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
50 declare <4 x i32> @llvm.arm.neon.sha1p.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
51 declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
52 declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
53 declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
54 declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
55 declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>)
56 declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>)
None @ RUN: not llvm-mc -triple armv8 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck %s
0 @ RUN: not llvm-mc -triple armv8 -mattr=+neon,+crypto -show-encoding < %s 2>&1 | FileCheck %s
11
22 vmaxnm.f32 s4, d5, q1
33 @ CHECK: error: invalid operand for instruction
2323 @ CHECK: error: invalid operand for instruction
2424 vrintmge.f32.f32 d3, d4
2525 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
26
27 aesd.8 q0, s1
28 @ CHECK: error: invalid operand for instruction
29 aese.8 s0, q1
30 @ CHECK: error: invalid operand for instruction
31 aesimc.8 s0, q1
32 @ CHECK: error: invalid operand for instruction
33 aesmc.8 q0, d1
34 @ CHECK: error: invalid operand for instruction
35 aesdge.8 q0, q1
36 @ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
37
38 sha1h.32 d0, q1
39 @ CHECK: error: invalid operand for instruction
40 sha1su1.32 q0, s1
41 @ CHECK: error: invalid operand for instruction
42 sha256su0.32 s0, q1
43 @ CHECK: error: invalid operand for instruction
44 sha1heq.32 q0, q1
45 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
46
47 sha1c.32 s0, d1, q2
48 @ CHECK: error: invalid operand for instruction
49 sha1m.32 q0, s1, q2
50 @ CHECK: error: invalid operand for instruction
51 sha1p.32 s0, q1, q2
52 @ CHECK: error: invalid operand for instruction
53 sha1su0.32 d0, q1, q2
54 @ CHECK: error: invalid operand for instruction
55 sha256h.32 q0, s1, q2
56 @ CHECK: error: invalid operand for instruction
57 sha256h2.32 q0, q1, s2
58 @ CHECK: error: invalid operand for instruction
59 sha256su1.32 s0, d1, q2
60 @ CHECK: error: invalid operand for instruction
61 sha256su1lt.32 q0, d1, q2
62 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
63
64 vmull.p64 q0, s1, s3
65 @ CHECK: error: invalid operand for instruction
66 vmull.p64 s1, d2, d3
67 @ CHECK: error: invalid operand for instruction
68 vmullge.p64 q0, d16, d17
69 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
0 @ RUN: llvm-mc -triple armv8 -mattr=+neon,+crypto -show-encoding < %s | FileCheck %s
1 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
2
3 aesd.8 q0, q1
4 aese.8 q0, q1
5 aesimc.8 q0, q1
6 aesmc.8 q0, q1
7 @ CHECK: aesd.8 q0, q1 @ encoding: [0x42,0x03,0xb0,0xf3]
8 @ CHECK: aese.8 q0, q1 @ encoding: [0x02,0x03,0xb0,0xf3]
9 @ CHECK: aesimc.8 q0, q1 @ encoding: [0xc2,0x03,0xb0,0xf3]
10 @ CHECK: aesmc.8 q0, q1 @ encoding: [0x82,0x03,0xb0,0xf3]
11 @ CHECK-V7: instruction requires: crypto armv8
12 @ CHECK-V7: instruction requires: crypto armv8
13 @ CHECK-V7: instruction requires: crypto armv8
14 @ CHECK-V7: instruction requires: crypto armv8
15
16 sha1h.32 q0, q1
17 sha1su1.32 q0, q1
18 sha256su0.32 q0, q1
19 @ CHECK: sha1h.32 q0, q1 @ encoding: [0xc2,0x02,0xb9,0xf3]
20 @ CHECK: sha1su1.32 q0, q1 @ encoding: [0x82,0x03,0xba,0xf3]
21 @ CHECK: sha256su0.32 q0, q1 @ encoding: [0xc2,0x03,0xba,0xf3]
22 @ CHECK-V7: instruction requires: crypto armv8
23 @ CHECK-V7: instruction requires: crypto armv8
24 @ CHECK-V7: instruction requires: crypto armv8
25
26 sha1c.32 q0, q1, q2
27 sha1m.32 q0, q1, q2
28 sha1p.32 q0, q1, q2
29 sha1su0.32 q0, q1, q2
30 sha256h.32 q0, q1, q2
31 sha256h2.32 q0, q1, q2
32 sha256su1.32 q0, q1, q2
33 @ CHECK: sha1c.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x02,0xf2]
34 @ CHECK: sha1m.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xf2]
35 @ CHECK: sha1p.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x12,0xf2]
36 @ CHECK: sha1su0.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x32,0xf2]
37 @ CHECK: sha256h.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x02,0xf3]
38 @ CHECK: sha256h2.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x12,0xf3]
39 @ CHECK: sha256su1.32 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xf3]
40 @ CHECK-V7: instruction requires: crypto armv8
41 @ CHECK-V7: instruction requires: crypto armv8
42 @ CHECK-V7: instruction requires: crypto armv8
43 @ CHECK-V7: instruction requires: crypto armv8
44 @ CHECK-V7: instruction requires: crypto armv8
45 @ CHECK-V7: instruction requires: crypto armv8
46 @ CHECK-V7: instruction requires: crypto armv8
47
48 vmull.p64 q8, d16, d17
49 @ CHECK: vmull.p64 q8, d16, d17 @ encoding: [0xa1,0x0e,0xe0,0xf2]
50 @ CHECK-V7: instruction requires: crypto armv8
0 @ RUN: not llvm-mc -triple thumbv8 -mattr=+neon,+crypto -show-encoding < %s 2>&1 | FileCheck %s
1
2 iteee lo
3 aesdlo.8 q0, q1
4 @ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
5 aesimchs.8 q0, q1
6 @ CHECK: error: instruction 'aesimc' is not predicable, but condition code specified
7 aesmchs.8 q0, q1
8 @ CHECK: error: instruction 'aesmc' is not predicable, but condition code specified
9 aesehs.8 q0, q1
10 @ CHECK: error: instruction 'aese' is not predicable, but condition code specified
11
12 itee hs
13 sha1hhs.32 q0, q1
14 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
15 sha1su1lo.32 q0, q1
16 @ CHECK: error: instruction 'sha1su1' is not predicable, but condition code specified
17 sha256su0lo.32 q0, q1
18 @ CHECK: error: instruction 'sha256su0' is not predicable, but condition code specified
19
20 iteee lo
21 sha1clo.32 s0, d1, q2
22 @ CHECK: error: instruction 'sha1c' is not predicable, but condition code specified
23 sha1mhs.32 q0, s1, q2
24 @ CHECK: error: instruction 'sha1m' is not predicable, but condition code specified
25 sha1phs.32 s0, q1, q2
26 @ CHECK: error: instruction 'sha1p' is not predicable, but condition code specified
27 sha1su0hs.32 d0, q1, q2
28 @ CHECK: error: instruction 'sha1su0' is not predicable, but condition code specified
29 itee hs
30 sha256hhs.32 q0, s1, q2
31 @ CHECK: error: instruction 'sha256h' is not predicable, but condition code specified
32 sha256h2lo.32 q0, q1, s2
33 @ CHECK: error: instruction 'sha256h2' is not predicable, but condition code specified
34 sha256su1lo.32 s0, d1, q2
35 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
36
37 ite lo
38 vmulllo.p64 q0, s1, s3
39 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
40 vmullhs.p64 q0, d16, d17
41 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
0 @ RUN: llvm-mc -triple thumbv8 -mattr=+neon,+crypto -show-encoding < %s | FileCheck %s
1
2 aesd.8 q0, q1
3 @ CHECK: aesd.8 q0, q1 @ encoding: [0xb0,0xff,0x42,0x03]
4 aese.8 q0, q1
5 @ CHECK: aese.8 q0, q1 @ encoding: [0xb0,0xff,0x02,0x03]
6 aesimc.8 q0, q1
7 @ CHECK: aesimc.8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x03]
8 aesmc.8 q0, q1
9 @ CHECK: aesmc.8 q0, q1 @ encoding: [0xb0,0xff,0x82,0x03]
10
11 sha1h.32 q0, q1
12 @ CHECK: sha1h.32 q0, q1 @ encoding: [0xb9,0xff,0xc2,0x02]
13 sha1su1.32 q0, q1
14 @ CHECK: sha1su1.32 q0, q1 @ encoding: [0xba,0xff,0x82,0x03]
15 sha256su0.32 q0, q1
16 @ CHECK: sha256su0.32 q0, q1 @ encoding: [0xba,0xff,0xc2,0x03]
17
18 sha1c.32 q0, q1, q2
19 @ CHECK: sha1c.32 q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0c]
20 sha1m.32 q0, q1, q2
21 @ CHECK: sha1m.32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x0c]
22 sha1p.32 q0, q1, q2
23 @ CHECK: sha1p.32 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0c]
24 sha1su0.32 q0, q1, q2
25 @ CHECK: sha1su0.32 q0, q1, q2 @ encoding: [0x32,0xef,0x44,0x0c]
26 sha256h.32 q0, q1, q2
27 @ CHECK: sha256h.32 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x0c]
28 sha256h2.32 q0, q1, q2
29 @ CHECK: sha256h2.32 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x0c]
30 sha256su1.32 q0, q1, q2
31 @ CHECK: sha256su1.32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x0c]
32
33 vmull.p64 q8, d16, d17
34 @ CHECK: vmull.p64 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0e]
0 # RUN: llvm-mc -triple armv8-unknown-unknown -mattr=+neon,+crypto -disassemble < %s | FileCheck %s
1
2 0x42,0x03,0xb0,0xf3
3 # CHECK: aesd.8 q0, q1
4 0x02,0x03,0xb0,0xf3
5 # CHECK: aese.8 q0, q1
6 0xc2,0x03,0xb0,0xf3
7 # CHECK: aesimc.8 q0, q1
8 0x82,0x03,0xb0,0xf3
9 # CHECK: aesmc.8 q0, q1
10
11 0xc2,0x02,0xb9,0xf3
12 # CHECK: sha1h.32 q0, q1
13 0x82,0x03,0xba,0xf3
14 # CHECK: sha1su1.32 q0, q1
15 0xc2,0x03,0xba,0xf3
16 # CHECK: sha256su0.32 q0, q1
17
18 0x44,0x0c,0x02,0xf2
19 # CHECK: sha1c.32 q0, q1, q2
20 0x44,0x0c,0x22,0xf2
21 # CHECK: sha1m.32 q0, q1, q2
22 0x44,0x0c,0x12,0xf2
23 # CHECK: sha1p.32 q0, q1, q2
24 0x44,0x0c,0x32,0xf2
25 # CHECK: sha1su0.32 q0, q1, q2
26 0x44,0x0c,0x02,0xf3
27 # CHECK: sha256h.32 q0, q1, q2
28 0x44,0x0c,0x12,0xf3
29 # CHECK: sha256h2.32 q0, q1, q2
30 0x44,0x0c,0x22,0xf3
31 # CHECK: sha256su1.32 q0, q1, q2
32
33 0xa1,0x0e,0xe0,0xf2
34 # CHECK: vmull.p64 q8, d16, d17
0 # RUN: llvm-mc -triple thumbv8-unknown-unknown -mattr=+neon,+crypto -disassemble < %s | FileCheck %s
1
2 0xb0 0xff 0x42 0x03
3 # CHECK: aesd.8 q0, q1
4 0xb0 0xff 0x02 0x03
5 # CHECK: aese.8 q0, q1
6 0xb0 0xff 0xc2 0x03
7 # CHECK: aesimc.8 q0, q1
8 0xb0 0xff 0x82 0x03
9 # CHECK: aesmc.8 q0, q1
10
11 0xb9 0xff 0xc2 0x02
12 # CHECK: sha1h.32 q0, q1
13 0xba 0xff 0x82 0x03
14 # CHECK: sha1su1.32 q0, q1
15 0xba 0xff 0xc2 0x03
16 # CHECK: sha256su0.32 q0, q1
17
18 0x02 0xef 0x44 0x0c
19 # CHECK: sha1c.32 q0, q1, q2
20 0x22 0xef 0x44 0x0c
21 # CHECK: sha1m.32 q0, q1, q2
22 0x12 0xef 0x44 0x0c
23 # CHECK: sha1p.32 q0, q1, q2
24 0x32 0xef 0x44 0x0c
25 # CHECK: sha1su0.32 q0, q1, q2
26 0x02 0xff 0x44 0x0c
27 # CHECK: sha256h.32 q0, q1, q2
28 0x12 0xff 0x44 0x0c
29 # CHECK: sha256h2.32 q0, q1, q2
30 0x22 0xff 0x44 0x0c
31 # CHECK: sha256su1.32 q0, q1, q2
32
33 0xe0 0xef 0xa1 0x0e
34 # CHECK: vmull.p64 q8, d16, d17