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Convert more NEON tests to use FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83587 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
13 changed file(s) with 295 addition(s) and 100 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqabs\\.s8} %t | count 2
2 ; RUN: grep {vqabs\\.s16} %t | count 2
3 ; RUN: grep {vqabs\\.s32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
41
52 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
3 ;CHECK: vqabss8:
4 ;CHECK: vqabs.s8
65 %tmp1 = load <8 x i8>* %A
76 %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
87 ret <8 x i8> %tmp2
98 }
109
1110 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
11 ;CHECK: vqabss16:
12 ;CHECK: vqabs.s16
1213 %tmp1 = load <4 x i16>* %A
1314 %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
1415 ret <4 x i16> %tmp2
1516 }
1617
1718 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
19 ;CHECK: vqabss32:
20 ;CHECK: vqabs.s32
1821 %tmp1 = load <2 x i32>* %A
1922 %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
2023 ret <2 x i32> %tmp2
2124 }
2225
2326 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
27 ;CHECK: vqabsQs8:
28 ;CHECK: vqabs.s8
2429 %tmp1 = load <16 x i8>* %A
2530 %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
2631 ret <16 x i8> %tmp2
2732 }
2833
2934 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
35 ;CHECK: vqabsQs16:
36 ;CHECK: vqabs.s16
3037 %tmp1 = load <8 x i16>* %A
3138 %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
3239 ret <8 x i16> %tmp2
3340 }
3441
3542 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
43 ;CHECK: vqabsQs32:
44 ;CHECK: vqabs.s32
3645 %tmp1 = load <4 x i32>* %A
3746 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
3847 ret <4 x i32> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqadd\\.s8} %t | count 2
2 ; RUN: grep {vqadd\\.s16} %t | count 2
3 ; RUN: grep {vqadd\\.s32} %t | count 2
4 ; RUN: grep {vqadd\\.s64} %t | count 2
5 ; RUN: grep {vqadd\\.u8} %t | count 2
6 ; RUN: grep {vqadd\\.u16} %t | count 2
7 ; RUN: grep {vqadd\\.u32} %t | count 2
8 ; RUN: grep {vqadd\\.u64} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
91
102 define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vqadds8:
4 ;CHECK: vqadd.s8
115 %tmp1 = load <8 x i8>* %A
126 %tmp2 = load <8 x i8>* %B
137 %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
159 }
1610
1711 define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vqadds16:
13 ;CHECK: vqadd.s16
1814 %tmp1 = load <4 x i16>* %A
1915 %tmp2 = load <4 x i16>* %B
2016 %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2218 }
2319
2420 define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vqadds32:
22 ;CHECK: vqadd.s32
2523 %tmp1 = load <2 x i32>* %A
2624 %tmp2 = load <2 x i32>* %B
2725 %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2927 }
3028
3129 define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
30 ;CHECK: vqadds64:
31 ;CHECK: vqadd.s64
3232 %tmp1 = load <1 x i64>* %A
3333 %tmp2 = load <1 x i64>* %B
3434 %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
3636 }
3737
3838 define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
39 ;CHECK: vqaddu8:
40 ;CHECK: vqadd.u8
3941 %tmp1 = load <8 x i8>* %A
4042 %tmp2 = load <8 x i8>* %B
4143 %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
4345 }
4446
4547 define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
48 ;CHECK: vqaddu16:
49 ;CHECK: vqadd.u16
4650 %tmp1 = load <4 x i16>* %A
4751 %tmp2 = load <4 x i16>* %B
4852 %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
5054 }
5155
5256 define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
57 ;CHECK: vqaddu32:
58 ;CHECK: vqadd.u32
5359 %tmp1 = load <2 x i32>* %A
5460 %tmp2 = load <2 x i32>* %B
5561 %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
5763 }
5864
5965 define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
66 ;CHECK: vqaddu64:
67 ;CHECK: vqadd.u64
6068 %tmp1 = load <1 x i64>* %A
6169 %tmp2 = load <1 x i64>* %B
6270 %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
6472 }
6573
6674 define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
75 ;CHECK: vqaddQs8:
76 ;CHECK: vqadd.s8
6777 %tmp1 = load <16 x i8>* %A
6878 %tmp2 = load <16 x i8>* %B
6979 %tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
7181 }
7282
7383 define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
84 ;CHECK: vqaddQs16:
85 ;CHECK: vqadd.s16
7486 %tmp1 = load <8 x i16>* %A
7587 %tmp2 = load <8 x i16>* %B
7688 %tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
7890 }
7991
8092 define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
93 ;CHECK: vqaddQs32:
94 ;CHECK: vqadd.s32
8195 %tmp1 = load <4 x i32>* %A
8296 %tmp2 = load <4 x i32>* %B
8397 %tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
8599 }
86100
87101 define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
102 ;CHECK: vqaddQs64:
103 ;CHECK: vqadd.s64
88104 %tmp1 = load <2 x i64>* %A
89105 %tmp2 = load <2 x i64>* %B
90106 %tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
92108 }
93109
94110 define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
111 ;CHECK: vqaddQu8:
112 ;CHECK: vqadd.u8
95113 %tmp1 = load <16 x i8>* %A
96114 %tmp2 = load <16 x i8>* %B
97115 %tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
99117 }
100118
101119 define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
120 ;CHECK: vqaddQu16:
121 ;CHECK: vqadd.u16
102122 %tmp1 = load <8 x i16>* %A
103123 %tmp2 = load <8 x i16>* %B
104124 %tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
106126 }
107127
108128 define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
129 ;CHECK: vqaddQu32:
130 ;CHECK: vqadd.u32
109131 %tmp1 = load <4 x i32>* %A
110132 %tmp2 = load <4 x i32>* %B
111133 %tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
113135 }
114136
115137 define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
138 ;CHECK: vqaddQu64:
139 ;CHECK: vqadd.u64
116140 %tmp1 = load <2 x i64>* %A
117141 %tmp2 = load <2 x i64>* %B
118142 %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqdmlal\\.s16} %t | count 1
2 ; RUN: grep {vqdmlal\\.s32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
31
42 define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
3 ;CHECK: vqdmlals16:
4 ;CHECK: vqdmlal.s16
55 %tmp1 = load <4 x i32>* %A
66 %tmp2 = load <4 x i16>* %B
77 %tmp3 = load <4 x i16>* %C
1010 }
1111
1212 define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
13 ;CHECK: vqdmlals32:
14 ;CHECK: vqdmlal.s32
1315 %tmp1 = load <2 x i64>* %A
1416 %tmp2 = load <2 x i32>* %B
1517 %tmp3 = load <2 x i32>* %C
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqdmlsl\\.s16} %t | count 1
2 ; RUN: grep {vqdmlsl\\.s32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
31
42 define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
3 ;CHECK: vqdmlsls16:
4 ;CHECK: vqdmlsl.s16
55 %tmp1 = load <4 x i32>* %A
66 %tmp2 = load <4 x i16>* %B
77 %tmp3 = load <4 x i16>* %C
1010 }
1111
1212 define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
13 ;CHECK: vqdmlsls32:
14 ;CHECK: vqdmlsl.s32
1315 %tmp1 = load <2 x i64>* %A
1416 %tmp2 = load <2 x i32>* %B
1517 %tmp3 = load <2 x i32>* %C
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqdmulh\\.s16} %t | count 2
2 ; RUN: grep {vqdmulh\\.s32} %t | count 2
3 ; RUN: grep {vqrdmulh\\.s16} %t | count 2
4 ; RUN: grep {vqrdmulh\\.s32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
51
62 define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
3 ;CHECK: vqdmulhs16:
4 ;CHECK: vqdmulh.s16
75 %tmp1 = load <4 x i16>* %A
86 %tmp2 = load <4 x i16>* %B
97 %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
119 }
1210
1311 define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
12 ;CHECK: vqdmulhs32:
13 ;CHECK: vqdmulh.s32
1414 %tmp1 = load <2 x i32>* %A
1515 %tmp2 = load <2 x i32>* %B
1616 %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
1818 }
1919
2020 define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
21 ;CHECK: vqdmulhQs16:
22 ;CHECK: vqdmulh.s16
2123 %tmp1 = load <8 x i16>* %A
2224 %tmp2 = load <8 x i16>* %B
2325 %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
2527 }
2628
2729 define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
30 ;CHECK: vqdmulhQs32:
31 ;CHECK: vqdmulh.s32
2832 %tmp1 = load <4 x i32>* %A
2933 %tmp2 = load <4 x i32>* %B
3034 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
3842 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
3943
4044 define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
45 ;CHECK: vqrdmulhs16:
46 ;CHECK: vqrdmulh.s16
4147 %tmp1 = load <4 x i16>* %A
4248 %tmp2 = load <4 x i16>* %B
4349 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
4551 }
4652
4753 define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
54 ;CHECK: vqrdmulhs32:
55 ;CHECK: vqrdmulh.s32
4856 %tmp1 = load <2 x i32>* %A
4957 %tmp2 = load <2 x i32>* %B
5058 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
5260 }
5361
5462 define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
63 ;CHECK: vqrdmulhQs16:
64 ;CHECK: vqrdmulh.s16
5565 %tmp1 = load <8 x i16>* %A
5666 %tmp2 = load <8 x i16>* %B
5767 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
5969 }
6070
6171 define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
72 ;CHECK: vqrdmulhQs32:
73 ;CHECK: vqrdmulh.s32
6274 %tmp1 = load <4 x i32>* %A
6375 %tmp2 = load <4 x i32>* %B
6476 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqdmull\\.s16} %t | count 1
2 ; RUN: grep {vqdmull\\.s32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
31
42 define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
3 ;CHECK: vqdmulls16:
4 ;CHECK: vqdmull.s16
55 %tmp1 = load <4 x i16>* %A
66 %tmp2 = load <4 x i16>* %B
77 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
99 }
1010
1111 define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
12 ;CHECK: vqdmulls32:
13 ;CHECK: vqdmull.s32
1214 %tmp1 = load <2 x i32>* %A
1315 %tmp2 = load <2 x i32>* %B
1416 %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqmovn\\.s16} %t | count 1
2 ; RUN: grep {vqmovn\\.s32} %t | count 1
3 ; RUN: grep {vqmovn\\.s64} %t | count 1
4 ; RUN: grep {vqmovn\\.u16} %t | count 1
5 ; RUN: grep {vqmovn\\.u32} %t | count 1
6 ; RUN: grep {vqmovn\\.u64} %t | count 1
7 ; RUN: grep {vqmovun\\.s16} %t | count 1
8 ; RUN: grep {vqmovun\\.s32} %t | count 1
9 ; RUN: grep {vqmovun\\.s64} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
101
112 define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
3 ;CHECK: vqmovns16:
4 ;CHECK: vqmovn.s16
125 %tmp1 = load <8 x i16>* %A
136 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
147 ret <8 x i8> %tmp2
158 }
169
1710 define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
11 ;CHECK: vqmovns32:
12 ;CHECK: vqmovn.s32
1813 %tmp1 = load <4 x i32>* %A
1914 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
2015 ret <4 x i16> %tmp2
2116 }
2217
2318 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
19 ;CHECK: vqmovns64:
20 ;CHECK: vqmovn.s64
2421 %tmp1 = load <2 x i64>* %A
2522 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
2623 ret <2 x i32> %tmp2
2724 }
2825
2926 define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
27 ;CHECK: vqmovnu16:
28 ;CHECK: vqmovn.u16
3029 %tmp1 = load <8 x i16>* %A
3130 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
3231 ret <8 x i8> %tmp2
3332 }
3433
3534 define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
35 ;CHECK: vqmovnu32:
36 ;CHECK: vqmovn.u32
3637 %tmp1 = load <4 x i32>* %A
3738 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
3839 ret <4 x i16> %tmp2
3940 }
4041
4142 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
43 ;CHECK: vqmovnu64:
44 ;CHECK: vqmovn.u64
4245 %tmp1 = load <2 x i64>* %A
4346 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
4447 ret <2 x i32> %tmp2
4548 }
4649
4750 define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
51 ;CHECK: vqmovuns16:
52 ;CHECK: vqmovun.s16
4853 %tmp1 = load <8 x i16>* %A
4954 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
5055 ret <8 x i8> %tmp2
5156 }
5257
5358 define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
59 ;CHECK: vqmovuns32:
60 ;CHECK: vqmovun.s32
5461 %tmp1 = load <4 x i32>* %A
5562 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
5663 ret <4 x i16> %tmp2
5764 }
5865
5966 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
67 ;CHECK: vqmovuns64:
68 ;CHECK: vqmovun.s64
6069 %tmp1 = load <2 x i64>* %A
6170 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
6271 ret <2 x i32> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqneg\\.s8} %t | count 2
2 ; RUN: grep {vqneg\\.s16} %t | count 2
3 ; RUN: grep {vqneg\\.s32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
41
52 define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
3 ;CHECK: vqnegs8:
4 ;CHECK: vqneg.s8
65 %tmp1 = load <8 x i8>* %A
76 %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
87 ret <8 x i8> %tmp2
98 }
109
1110 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
11 ;CHECK: vqnegs16:
12 ;CHECK: vqneg.s16
1213 %tmp1 = load <4 x i16>* %A
1314 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
1415 ret <4 x i16> %tmp2
1516 }
1617
1718 define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
19 ;CHECK: vqnegs32:
20 ;CHECK: vqneg.s32
1821 %tmp1 = load <2 x i32>* %A
1922 %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
2023 ret <2 x i32> %tmp2
2124 }
2225
2326 define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
27 ;CHECK: vqnegQs8:
28 ;CHECK: vqneg.s8
2429 %tmp1 = load <16 x i8>* %A
2530 %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
2631 ret <16 x i8> %tmp2
2732 }
2833
2934 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
35 ;CHECK: vqnegQs16:
36 ;CHECK: vqneg.s16
3037 %tmp1 = load <8 x i16>* %A
3138 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
3239 ret <8 x i16> %tmp2
3340 }
3441
3542 define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
43 ;CHECK: vqnegQs32:
44 ;CHECK: vqneg.s32
3645 %tmp1 = load <4 x i32>* %A
3746 %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
3847 ret <4 x i32> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqrshl\\.s8} %t | count 2
2 ; RUN: grep {vqrshl\\.s16} %t | count 2
3 ; RUN: grep {vqrshl\\.s32} %t | count 2
4 ; RUN: grep {vqrshl\\.s64} %t | count 2
5 ; RUN: grep {vqrshl\\.u8} %t | count 2
6 ; RUN: grep {vqrshl\\.u16} %t | count 2
7 ; RUN: grep {vqrshl\\.u32} %t | count 2
8 ; RUN: grep {vqrshl\\.u64} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
91
102 define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vqrshls8:
4 ;CHECK: vqrshl.s8
115 %tmp1 = load <8 x i8>* %A
126 %tmp2 = load <8 x i8>* %B
137 %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
159 }
1610
1711 define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vqrshls16:
13 ;CHECK: vqrshl.s16
1814 %tmp1 = load <4 x i16>* %A
1915 %tmp2 = load <4 x i16>* %B
2016 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2218 }
2319
2420 define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vqrshls32:
22 ;CHECK: vqrshl.s32
2523 %tmp1 = load <2 x i32>* %A
2624 %tmp2 = load <2 x i32>* %B
2725 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2927 }
3028
3129 define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
30 ;CHECK: vqrshls64:
31 ;CHECK: vqrshl.s64
3232 %tmp1 = load <1 x i64>* %A
3333 %tmp2 = load <1 x i64>* %B
3434 %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
3636 }
3737
3838 define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
39 ;CHECK: vqrshlu8:
40 ;CHECK: vqrshl.u8
3941 %tmp1 = load <8 x i8>* %A
4042 %tmp2 = load <8 x i8>* %B
4143 %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
4345 }
4446
4547 define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
48 ;CHECK: vqrshlu16:
49 ;CHECK: vqrshl.u16
4650 %tmp1 = load <4 x i16>* %A
4751 %tmp2 = load <4 x i16>* %B
4852 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
5054 }
5155
5256 define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
57 ;CHECK: vqrshlu32:
58 ;CHECK: vqrshl.u32
5359 %tmp1 = load <2 x i32>* %A
5460 %tmp2 = load <2 x i32>* %B
5561 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
5763 }
5864
5965 define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
66 ;CHECK: vqrshlu64:
67 ;CHECK: vqrshl.u64
6068 %tmp1 = load <1 x i64>* %A
6169 %tmp2 = load <1 x i64>* %B
6270 %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
6472 }
6573
6674 define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
75 ;CHECK: vqrshlQs8:
76 ;CHECK: vqrshl.s8
6777 %tmp1 = load <16 x i8>* %A
6878 %tmp2 = load <16 x i8>* %B
6979 %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
7181 }
7282
7383 define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
84 ;CHECK: vqrshlQs16:
85 ;CHECK: vqrshl.s16
7486 %tmp1 = load <8 x i16>* %A
7587 %tmp2 = load <8 x i16>* %B
7688 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
7890 }
7991
8092 define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
93 ;CHECK: vqrshlQs32:
94 ;CHECK: vqrshl.s32
8195 %tmp1 = load <4 x i32>* %A
8296 %tmp2 = load <4 x i32>* %B
8397 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
8599 }
86100
87101 define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
102 ;CHECK: vqrshlQs64:
103 ;CHECK: vqrshl.s64
88104 %tmp1 = load <2 x i64>* %A
89105 %tmp2 = load <2 x i64>* %B
90106 %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
92108 }
93109
94110 define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
111 ;CHECK: vqrshlQu8:
112 ;CHECK: vqrshl.u8
95113 %tmp1 = load <16 x i8>* %A
96114 %tmp2 = load <16 x i8>* %B
97115 %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
99117 }
100118
101119 define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
120 ;CHECK: vqrshlQu16:
121 ;CHECK: vqrshl.u16
102122 %tmp1 = load <8 x i16>* %A
103123 %tmp2 = load <8 x i16>* %B
104124 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
106126 }
107127
108128 define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
129 ;CHECK: vqrshlQu32:
130 ;CHECK: vqrshl.u32
109131 %tmp1 = load <4 x i32>* %A
110132 %tmp2 = load <4 x i32>* %B
111133 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
113135 }
114136
115137 define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
138 ;CHECK: vqrshlQu64:
139 ;CHECK: vqrshl.u64
116140 %tmp1 = load <2 x i64>* %A
117141 %tmp2 = load <2 x i64>* %B
118142 %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqrshrn\\.s16} %t | count 1
2 ; RUN: grep {vqrshrn\\.s32} %t | count 1
3 ; RUN: grep {vqrshrn\\.s64} %t | count 1
4 ; RUN: grep {vqrshrn\\.u16} %t | count 1
5 ; RUN: grep {vqrshrn\\.u32} %t | count 1
6 ; RUN: grep {vqrshrn\\.u64} %t | count 1
7 ; RUN: grep {vqrshrun\\.s16} %t | count 1
8 ; RUN: grep {vqrshrun\\.s32} %t | count 1
9 ; RUN: grep {vqrshrun\\.s64} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
101
112 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
3 ;CHECK: vqrshrns8:
4 ;CHECK: vqrshrn.s16
125 %tmp1 = load <8 x i16>* %A
136 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
147 ret <8 x i8> %tmp2
158 }
169
1710 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
11 ;CHECK: vqrshrns16:
12 ;CHECK: vqrshrn.s32
1813 %tmp1 = load <4 x i32>* %A
1914 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
2015 ret <4 x i16> %tmp2
2116 }
2217
2318 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
19 ;CHECK: vqrshrns32:
20 ;CHECK: vqrshrn.s64
2421 %tmp1 = load <2 x i64>* %A
2522 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
2623 ret <2 x i32> %tmp2
2724 }
2825
2926 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
27 ;CHECK: vqrshrnu8:
28 ;CHECK: vqrshrn.u16
3029 %tmp1 = load <8 x i16>* %A
3130 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
3231 ret <8 x i8> %tmp2
3332 }
3433
3534 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
35 ;CHECK: vqrshrnu16:
36 ;CHECK: vqrshrn.u32
3637 %tmp1 = load <4 x i32>* %A
3738 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
3839 ret <4 x i16> %tmp2
3940 }
4041
4142 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
43 ;CHECK: vqrshrnu32:
44 ;CHECK: vqrshrn.u64
4245 %tmp1 = load <2 x i64>* %A
4346 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
4447 ret <2 x i32> %tmp2
4548 }
4649
4750 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
51 ;CHECK: vqrshruns8:
52 ;CHECK: vqrshrun.s16
4853 %tmp1 = load <8 x i16>* %A
4954 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
5055 ret <8 x i8> %tmp2
5156 }
5257
5358 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
59 ;CHECK: vqrshruns16:
60 ;CHECK: vqrshrun.s32
5461 %tmp1 = load <4 x i32>* %A
5562 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
5663 ret <4 x i16> %tmp2
5764 }
5865
5966 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
67 ;CHECK: vqrshruns32:
68 ;CHECK: vqrshrun.s64
6069 %tmp1 = load <2 x i64>* %A
6170 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
6271 ret <2 x i32> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqshl\\.s8} %t | count 4
2 ; RUN: grep {vqshl\\.s16} %t | count 4
3 ; RUN: grep {vqshl\\.s32} %t | count 4
4 ; RUN: grep {vqshl\\.s64} %t | count 4
5 ; RUN: grep {vqshl\\.u8} %t | count 4
6 ; RUN: grep {vqshl\\.u16} %t | count 4
7 ; RUN: grep {vqshl\\.u32} %t | count 4
8 ; RUN: grep {vqshl\\.u64} %t | count 4
9 ; RUN: grep {vqshl\\.s8.*#7} %t | count 2
10 ; RUN: grep {vqshl\\.s16.*#15} %t | count 2
11 ; RUN: grep {vqshl\\.s32.*#31} %t | count 2
12 ; RUN: grep {vqshl\\.s64.*#63} %t | count 2
13 ; RUN: grep {vqshl\\.u8.*#7} %t | count 2
14 ; RUN: grep {vqshl\\.u16.*#15} %t | count 2
15 ; RUN: grep {vqshl\\.u32.*#31} %t | count 2
16 ; RUN: grep {vqshl\\.u64.*#63} %t | count 2
17 ; RUN: grep {vqshlu\\.s8} %t | count 2
18 ; RUN: grep {vqshlu\\.s16} %t | count 2
19 ; RUN: grep {vqshlu\\.s32} %t | count 2
20 ; RUN: grep {vqshlu\\.s64} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
211
222 define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vqshls8:
4 ;CHECK: vqshl.s8
235 %tmp1 = load <8 x i8>* %A
246 %tmp2 = load <8 x i8>* %B
257 %tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
279 }
2810
2911 define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vqshls16:
13 ;CHECK: vqshl.s16
3014 %tmp1 = load <4 x i16>* %A
3115 %tmp2 = load <4 x i16>* %B
3216 %tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
3418 }
3519
3620 define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vqshls32:
22 ;CHECK: vqshl.s32
3723 %tmp1 = load <2 x i32>* %A
3824 %tmp2 = load <2 x i32>* %B
3925 %tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
4127 }
4228
4329 define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
30 ;CHECK: vqshls64:
31 ;CHECK: vqshl.s64
4432 %tmp1 = load <1 x i64>* %A
4533 %tmp2 = load <1 x i64>* %B
4634 %tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
4836 }
4937
5038 define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
39 ;CHECK: vqshlu8:
40 ;CHECK: vqshl.u8
5141 %tmp1 = load <8 x i8>* %A
5242 %tmp2 = load <8 x i8>* %B
5343 %tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
5545 }
5646
5747 define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
48 ;CHECK: vqshlu16:
49 ;CHECK: vqshl.u16
5850 %tmp1 = load <4 x i16>* %A
5951 %tmp2 = load <4 x i16>* %B
6052 %tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
6254 }
6355
6456 define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
57 ;CHECK: vqshlu32:
58 ;CHECK: vqshl.u32
6559 %tmp1 = load <2 x i32>* %A
6660 %tmp2 = load <2 x i32>* %B
6761 %tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
6963 }
7064
7165 define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
66 ;CHECK: vqshlu64:
67 ;CHECK: vqshl.u64
7268 %tmp1 = load <1 x i64>* %A
7369 %tmp2 = load <1 x i64>* %B
7470 %tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
7672 }
7773
7874 define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
75 ;CHECK: vqshlQs8:
76 ;CHECK: vqshl.s8
7977 %tmp1 = load <16 x i8>* %A
8078 %tmp2 = load <16 x i8>* %B
8179 %tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
8381 }
8482
8583 define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
84 ;CHECK: vqshlQs16:
85 ;CHECK: vqshl.s16
8686 %tmp1 = load <8 x i16>* %A
8787 %tmp2 = load <8 x i16>* %B
8888 %tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
9090 }
9191
9292 define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
93 ;CHECK: vqshlQs32:
94 ;CHECK: vqshl.s32
9395 %tmp1 = load <4 x i32>* %A
9496 %tmp2 = load <4 x i32>* %B
9597 %tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
9799 }
98100
99101 define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
102 ;CHECK: vqshlQs64:
103 ;CHECK: vqshl.s64
100104 %tmp1 = load <2 x i64>* %A
101105 %tmp2 = load <2 x i64>* %B
102106 %tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
104108 }
105109
106110 define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
111 ;CHECK: vqshlQu8:
112 ;CHECK: vqshl.u8
107113 %tmp1 = load <16 x i8>* %A
108114 %tmp2 = load <16 x i8>* %B
109115 %tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
111117 }
112118
113119 define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
120 ;CHECK: vqshlQu16:
121 ;CHECK: vqshl.u16
114122 %tmp1 = load <8 x i16>* %A
115123 %tmp2 = load <8 x i16>* %B
116124 %tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
118126 }
119127
120128 define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
129 ;CHECK: vqshlQu32:
130 ;CHECK: vqshl.u32
121131 %tmp1 = load <4 x i32>* %A
122132 %tmp2 = load <4 x i32>* %B
123133 %tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
125135 }
126136
127137 define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
138 ;CHECK: vqshlQu64:
139 ;CHECK: vqshl.u64
128140 %tmp1 = load <2 x i64>* %A
129141 %tmp2 = load <2 x i64>* %B
130142 %tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
132144 }
133145
134146 define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
147 ;CHECK: vqshls_n8:
148 ;CHECK: vqshl.s8{{.*#7}}
135149 %tmp1 = load <8 x i8>* %A
136150 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
137151 ret <8 x i8> %tmp2
138152 }
139153
140154 define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
155 ;CHECK: vqshls_n16:
156 ;CHECK: vqshl.s16{{.*#15}}
141157 %tmp1 = load <4 x i16>* %A
142158 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
143159 ret <4 x i16> %tmp2
144160 }
145161
146162 define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
163 ;CHECK: vqshls_n32:
164 ;CHECK: vqshl.s32{{.*#31}}
147165 %tmp1 = load <2 x i32>* %A
148166 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
149167 ret <2 x i32> %tmp2
150168 }
151169
152170 define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
171 ;CHECK: vqshls_n64:
172 ;CHECK: vqshl.s64{{.*#63}}
153173 %tmp1 = load <1 x i64>* %A
154174 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
155175 ret <1 x i64> %tmp2
156176 }
157177
158178 define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
179 ;CHECK: vqshlu_n8:
180 ;CHECK: vqshl.u8{{.*#7}}
159181 %tmp1 = load <8 x i8>* %A
160182 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
161183 ret <8 x i8> %tmp2
162184 }
163185
164186 define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
187 ;CHECK: vqshlu_n16:
188 ;CHECK: vqshl.u16{{.*#15}}
165189 %tmp1 = load <4 x i16>* %A
166190 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
167191 ret <4 x i16> %tmp2
168192 }
169193
170194 define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
195 ;CHECK: vqshlu_n32:
196 ;CHECK: vqshl.u32{{.*#31}}
171197 %tmp1 = load <2 x i32>* %A
172198 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
173199 ret <2 x i32> %tmp2
174200 }
175201
176202 define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
203 ;CHECK: vqshlu_n64:
204 ;CHECK: vqshl.u64{{.*#63}}
177205 %tmp1 = load <1 x i64>* %A
178206 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
179207 ret <1 x i64> %tmp2
180208 }
181209
182210 define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
211 ;CHECK: vqshlsu_n8:
212 ;CHECK: vqshlu.s8
183213 %tmp1 = load <8 x i8>* %A
184214 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
185215 ret <8 x i8> %tmp2
186216 }
187217
188218 define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
219 ;CHECK: vqshlsu_n16:
220 ;CHECK: vqshlu.s16
189221 %tmp1 = load <4 x i16>* %A
190222 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
191223 ret <4 x i16> %tmp2
192224 }
193225
194226 define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
227 ;CHECK: vqshlsu_n32:
228 ;CHECK: vqshlu.s32
195229 %tmp1 = load <2 x i32>* %A
196230 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
197231 ret <2 x i32> %tmp2
198232 }
199233
200234 define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
235 ;CHECK: vqshlsu_n64:
236 ;CHECK: vqshlu.s64
201237 %tmp1 = load <1 x i64>* %A
202238 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
203239 ret <1 x i64> %tmp2
204240 }
205241
206242 define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
243 ;CHECK: vqshlQs_n8:
244 ;CHECK: vqshl.s8{{.*#7}}
207245 %tmp1 = load <16 x i8>* %A
208246 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
209247 ret <16 x i8> %tmp2
210248 }
211249
212250 define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
251 ;CHECK: vqshlQs_n16:
252 ;CHECK: vqshl.s16{{.*#15}}
213253 %tmp1 = load <8 x i16>* %A
214254 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
215255 ret <8 x i16> %tmp2
216256 }
217257
218258 define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
259 ;CHECK: vqshlQs_n32:
260 ;CHECK: vqshl.s32{{.*#31}}
219261 %tmp1 = load <4 x i32>* %A
220262 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
221263 ret <4 x i32> %tmp2
222264 }
223265
224266 define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
267 ;CHECK: vqshlQs_n64:
268 ;CHECK: vqshl.s64{{.*#63}}
225269 %tmp1 = load <2 x i64>* %A
226270 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
227271 ret <2 x i64> %tmp2
228272 }
229273
230274 define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
275 ;CHECK: vqshlQu_n8:
276 ;CHECK: vqshl.u8{{.*#7}}
231277 %tmp1 = load <16 x i8>* %A
232278 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
233279 ret <16 x i8> %tmp2
234280 }
235281
236282 define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
283 ;CHECK: vqshlQu_n16:
284 ;CHECK: vqshl.u16{{.*#15}}
237285 %tmp1 = load <8 x i16>* %A
238286 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
239287 ret <8 x i16> %tmp2
240288 }
241289
242290 define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
291 ;CHECK: vqshlQu_n32:
292 ;CHECK: vqshl.u32{{.*#31}}
243293 %tmp1 = load <4 x i32>* %A
244294 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
245295 ret <4 x i32> %tmp2
246296 }
247297
248298 define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
299 ;CHECK: vqshlQu_n64:
300 ;CHECK: vqshl.u64{{.*#63}}
249301 %tmp1 = load <2 x i64>* %A
250302 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
251303 ret <2 x i64> %tmp2
252304 }
253305
254306 define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
307 ;CHECK: vqshlQsu_n8:
308 ;CHECK: vqshlu.s8
255309 %tmp1 = load <16 x i8>* %A
256310 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
257311 ret <16 x i8> %tmp2
258312 }
259313
260314 define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
315 ;CHECK: vqshlQsu_n16:
316 ;CHECK: vqshlu.s16
261317 %tmp1 = load <8 x i16>* %A
262318 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
263319 ret <8 x i16> %tmp2
264320 }
265321
266322 define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
323 ;CHECK: vqshlQsu_n32:
324 ;CHECK: vqshlu.s32
267325 %tmp1 = load <4 x i32>* %A
268326 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
269327 ret <4 x i32> %tmp2
270328 }
271329
272330 define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
331 ;CHECK: vqshlQsu_n64:
332 ;CHECK: vqshlu.s64
273333 %tmp1 = load <2 x i64>* %A
274334 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
275335 ret <2 x i64> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqshrn\\.s16} %t | count 1
2 ; RUN: grep {vqshrn\\.s32} %t | count 1
3 ; RUN: grep {vqshrn\\.s64} %t | count 1
4 ; RUN: grep {vqshrn\\.u16} %t | count 1
5 ; RUN: grep {vqshrn\\.u32} %t | count 1
6 ; RUN: grep {vqshrn\\.u64} %t | count 1
7 ; RUN: grep {vqshrun\\.s16} %t | count 1
8 ; RUN: grep {vqshrun\\.s32} %t | count 1
9 ; RUN: grep {vqshrun\\.s64} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
101
112 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
3 ;CHECK: vqshrns8:
4 ;CHECK: vqshrn.s16
125 %tmp1 = load <8 x i16>* %A
136 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
147 ret <8 x i8> %tmp2
158 }
169
1710 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
11 ;CHECK: vqshrns16:
12 ;CHECK: vqshrn.s32
1813 %tmp1 = load <4 x i32>* %A
1914 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
2015 ret <4 x i16> %tmp2
2116 }
2217
2318 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
19 ;CHECK: vqshrns32:
20 ;CHECK: vqshrn.s64
2421 %tmp1 = load <2 x i64>* %A
2522 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
2623 ret <2 x i32> %tmp2
2724 }
2825
2926 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
27 ;CHECK: vqshrnu8:
28 ;CHECK: vqshrn.u16
3029 %tmp1 = load <8 x i16>* %A
3130 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
3231 ret <8 x i8> %tmp2
3332 }
3433
3534 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
35 ;CHECK: vqshrnu16:
36 ;CHECK: vqshrn.u32
3637 %tmp1 = load <4 x i32>* %A
3738 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
3839 ret <4 x i16> %tmp2
3940 }
4041
4142 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
43 ;CHECK: vqshrnu32:
44 ;CHECK: vqshrn.u64
4245 %tmp1 = load <2 x i64>* %A
4346 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
4447 ret <2 x i32> %tmp2
4548 }
4649
4750 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
51 ;CHECK: vqshruns8:
52 ;CHECK: vqshrun.s16
4853 %tmp1 = load <8 x i16>* %A
4954 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
5055 ret <8 x i8> %tmp2
5156 }
5257
5358 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
59 ;CHECK: vqshruns16:
60 ;CHECK: vqshrun.s32
5461 %tmp1 = load <4 x i32>* %A
5562 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
5663 ret <4 x i16> %tmp2
5764 }
5865
5966 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
67 ;CHECK: vqshruns32:
68 ;CHECK: vqshrun.s64
6069 %tmp1 = load <2 x i64>* %A
6170 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
6271 ret <2 x i32> %tmp2
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vqsub\\.s8} %t | count 2
2 ; RUN: grep {vqsub\\.s16} %t | count 2
3 ; RUN: grep {vqsub\\.s32} %t | count 2
4 ; RUN: grep {vqsub\\.s64} %t | count 2
5 ; RUN: grep {vqsub\\.u8} %t | count 2
6 ; RUN: grep {vqsub\\.u16} %t | count 2
7 ; RUN: grep {vqsub\\.u32} %t | count 2
8 ; RUN: grep {vqsub\\.u64} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
91
102 define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vqsubs8:
4 ;CHECK: vqsub.s8
115 %tmp1 = load <8 x i8>* %A
126 %tmp2 = load <8 x i8>* %B
137 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
159 }
1610
1711 define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vqsubs16:
13 ;CHECK: vqsub.s16
1814 %tmp1 = load <4 x i16>* %A
1915 %tmp2 = load <4 x i16>* %B
2016 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2218 }
2319
2420 define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vqsubs32:
22 ;CHECK: vqsub.s32
2523 %tmp1 = load <2 x i32>* %A
2624 %tmp2 = load <2 x i32>* %B
2725 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2927 }
3028
3129 define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
30 ;CHECK: vqsubs64:
31 ;CHECK: vqsub.s64
3232 %tmp1 = load <1 x i64>* %A
3333 %tmp2 = load <1 x i64>* %B
3434 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
3636 }
3737
3838 define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
39 ;CHECK: vqsubu8:
40 ;CHECK: vqsub.u8
3941 %tmp1 = load <8 x i8>* %A
4042 %tmp2 = load <8 x i8>* %B
4143 %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
4345 }
4446
4547 define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
48 ;CHECK: vqsubu16:
49 ;CHECK: vqsub.u16
4650 %tmp1 = load <4 x i16>* %A
4751 %tmp2 = load <4 x i16>* %B
4852 %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
5054 }
5155
5256 define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
57 ;CHECK: vqsubu32:
58 ;CHECK: vqsub.u32
5359 %tmp1 = load <2 x i32>* %A
5460 %tmp2 = load <2 x i32>* %B
5561 %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
5763 }
5864
5965 define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
66 ;CHECK: vqsubu64:
67 ;CHECK: vqsub.u64
6068 %tmp1 = load <1 x i64>* %A
6169 %tmp2 = load <1 x i64>* %B
6270 %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
6472 }
6573
6674 define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
75 ;CHECK: vqsubQs8:
76 ;CHECK: vqsub.s8
6777 %tmp1 = load <16 x i8>* %A
6878 %tmp2 = load <16 x i8>* %B
6979 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
7181 }
7282
7383 define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
84 ;CHECK: vqsubQs16:
85 ;CHECK: vqsub.s16
7486 %tmp1 = load <8 x i16>* %A
7587 %tmp2 = load <8 x i16>* %B
7688 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
7890 }
7991
8092 define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
93 ;CHECK: vqsubQs32:
94 ;CHECK: vqsub.s32
8195 %tmp1 = load <4 x i32>* %A
8296 %tmp2 = load <4 x i32>* %B
8397 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
8599 }
86100
87101 define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
102 ;CHECK: vqsubQs64:
103 ;CHECK: vqsub.s64
88104 %tmp1 = load <2 x i64>* %A
89105 %tmp2 = load <2 x i64>* %B
90106 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
92108 }
93109
94110 define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
111 ;CHECK: vqsubQu8:
112 ;CHECK: vqsub.u8
95113 %tmp1 = load <16 x i8>* %A
96114 %tmp2 = load <16 x i8>* %B
97115 %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
99117 }
100118
101119 define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
120 ;CHECK: vqsubQu16:
121 ;CHECK: vqsub.u16
102122 %tmp1 = load <8 x i16>* %A
103123 %tmp2 = load <8 x i16>* %B
104124 %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
106126 }
107127
108128 define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
129 ;CHECK: vqsubQu32:
130 ;CHECK: vqsub.u32
109131 %tmp1 = load <4 x i32>* %A
110132 %tmp2 = load <4 x i32>* %B
111133 %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
113135 }
114136
115137 define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
138 ;CHECK: vqsubQu64:
139 ;CHECK: vqsub.u64
116140 %tmp1 = load <2 x i64>* %A
117141 %tmp2 = load <2 x i64>* %B
118142 %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)